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1. 发明授权

US09577074B2 Method for manufacturing finFET 有权
标题翻译： finFET的制造方法
公开(公告)号：US09577074B2
公开(公告)日：2017-02-21
申请号：US14905465
申请日：2013-10-22
申请人： Institute of Microelectronics, Chinese Academy of Sciences
发明人： Yunfei Liu , Haizhou Yin , Keke Zhang
IPC分类号： H01L29/49 , H01L29/66 , H01L21/8234 , H01L29/78 , H01L29/06
CPC分类号： H01L29/66795 , H01L21/823418 , H01L21/823431 , H01L29/0649 , H01L29/4966 , H01L29/66545 , H01L29/785 , H01L29/7853
摘要： A method of manufacturing a FinFET device is provided, comprising: a. providing a substrate (100); b. forming a fin (200) on the substrate; c. forming an shallow trench isolation structure (300) on the substrate; d. forming an sacrificial gate stack on the isolation structure, wherein the sacrificial gate stack intersects the fin; e. forming source/drain doping regions by ion implantation into the fin; f. depositing an interlayer dielectric layer (400) on the substrate; g. removing the sacrificial gate stack to form a sacrificial gate vacancy; h. forming an doped region (201) under the sacrificial gate vacancy; i. etching the shallow trench isolation structure (300) under the sacrificial gate vacancy until the top surface of the shallow trench isolation structure (300) levels with the bottom surface of the source/drain doping regions; j. forming a new gate stack in the sacrificial gate vacancy. Some advantages of the current invention may be, harmful effects produced in the source/drain regions by the triangle fin structure are eliminated, the device performance is improved, and the complexity of the process is reduce.
摘要翻译：提供一种制造FinFET器件的方法，包括：a。提供衬底（100）; b。在所述基板上形成翅片（200）; C。在衬底上形成浅沟槽隔离结构（300）; d。在所述隔离结构上形成牺牲栅极堆叠，其中所述牺牲栅极堆叠与所述鳍片相交; e。通过离子注入形成源极/漏极掺杂区域; F。在衬底上沉积层间电介质层（400）; G。去除牺牲栅极堆叠以形成牺牲栅极空位; H。在牺牲栅极空位下形成掺杂区域（201）; 一世。在牺牲栅极空位下蚀刻浅沟槽隔离结构（300），直到浅沟槽隔离结构（300）的顶表面与源极/漏极掺杂区域的底表面一致; j。在牺牲栅极空位中形成新的栅极堆叠。本发明的一些优点可以是消除由三角鳍结构在源极/漏极区域产生的有害影响，提高了器件性能，并且降低了工艺的复杂性。

2. 发明申请

US20150187892A1 METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE 审中-公开
标题翻译：制造半导体器件的方法
公开(公告)号：US20150187892A1
公开(公告)日：2015-07-02
申请号：US14416698
申请日：2012-08-03
申请人： Institute of Microelectronics, Chinese Academy of Sciences
发明人： Haizhou Yin , Keke Zhang
IPC分类号： H01L29/40 , H01L29/06 , H01L29/66
CPC分类号： H01L29/401 , H01L21/76224 , H01L29/0603 , H01L29/0649 , H01L29/1029 , H01L29/1083 , H01L29/41725 , H01L29/4966 , H01L29/517 , H01L29/66492 , H01L29/665 , H01L29/6653 , H01L29/66553 , H01L29/66583 , H01L29/66878 , H01L29/78 , H01L29/7846 , H01L29/812
摘要： A method for manufacturing a semiconductor device is disclosed, comprising: forming a contact sacrificial layer on the substrate, etching the contact sacrificial layer to form a contact sacrificial pattern, wherein the contact sacrificial pattern covers the source region and the drain region and has a gate trench that exposes the substrate; forming a gate spacer and a gate stack structure in the gate trench; partially or completely etching off the contact sacrificial pattern that covers the source region and the drain region so as to form a source/drain contact trench; and forming a source/drain contact in the source/drain contact trench. By means of the double-layer contact sacrificial layer, the method for manufacturing a semiconductor device in accordance with the present invention effectively reduces the spacing between the gate spacer and the contact region and increases the area of contact region, thus effectively reducing the parasitic resistance of the device.
摘要翻译：公开了一种用于制造半导体器件的方法，包括：在所述衬底上形成接触牺牲层，蚀刻所述接触牺牲层以形成接触牺牲图案，其中所述接触牺牲图案覆盖所述源极区域和所述漏极区域并具有栅极暴露基板的沟槽; 在所述栅极沟槽中形成栅极间隔物和栅极堆叠结构; 部分地或完全地蚀刻覆盖源极区域和漏极区域的接触牺牲图案，以便形成源极/漏极接触沟槽; 以及在源极/漏极接触沟槽中形成源极/漏极接触。通过双层接触牺牲层，根据本发明的半导体器件的制造方法有效地减小了栅极间隔物和接触区域之间的间隔并增加了接触区域的面积，从而有效地降低了寄生电阻的设备。

3. 发明授权

US10134983B2 Nonvolatile resistive switching memory device and manufacturing method thereof 有权
公开(公告)号：US10134983B2
公开(公告)日：2018-11-20
申请号：US15546212
申请日：2015-05-14
申请人： Institute of Microelectronics, Chinese Academy of Sciences
发明人： Qi Liu , Ming Liu , Haitao Sun , Keke Zhang , Shibing Long , Hangbing Lv , Writam Banerjee , Kangwei Zhang
IPC分类号： H01L45/00
摘要： A nonvolatile resistive switching memory, comprising an inert metal electrode, a resistive switching functional layer, and an easily oxidizable metal electrode, and characterized in that: a graphene barrier layer is inserted between the inert metal electrode and the resistive switching functional layer, which is capable of preventing the easily oxidizable metal ions from migrating into the inert metal electrode through the resistive switching functional layer under the action of electric field during the programming of the device. The manufacturing method therefore comprises adding a monolayer or multilayer graphene thin film between the inert electrode and the solid-state electrolyte resistive switching functional layer which services as a metal ion barrier layer to stop electrically-conductive metal filaments formed in the resistive switching layer from diffusing into the inert electrode layer during a RRAM device programming process, eliminating erroneous programming phenomenon occurring during the erasing process, improving device reliability.

4. 发明申请

US20160149027A1 ASYMMETRICAL FINFET STRUCTURE AND METHOD OF MANUFACTURING SAME 有权
标题翻译：非对称FINFET结构及其制造方法
公开(公告)号：US20160149027A1
公开(公告)日：2016-05-26
申请号：US14900594
申请日：2013-10-21
申请人： INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES
发明人： Haizhou Yin , Keke Zhang
IPC分类号： H01L29/78 , H01L29/06 , H01L29/40 , H01L29/66
CPC分类号： H01L29/785 , H01L29/0649 , H01L29/0688 , H01L29/401 , H01L29/66545 , H01L29/66818
摘要： A method of fabricating an asymmetric FinFET is provided in the invention, comprising: a. providing a substrate (101); b. forming a fin (102) on the substrate (101), wherein the width of the fin (102) is defined as a second channel thickness; c. forming a shallow trench isolation; d. forming a sacrificial gate stack on the top surface and sidewalls of the channel which is in the middle of the fin, and forming source/drain regions in both ends of the fin; e. depositing an interlayer dielectric layer to cover the sacrificial gate stack and the source/drain regions, planarizing the interlayer dielectric layer to expose sacrificial gate stack; f. removing the sacrificial gate stack to expose the channel; g. forming an etch-stop layer (106) on top of the channel; h. covering a photoresist film (400) on a portion of the semiconductor structure near the source region; i. thinning the channel which is not covered by the photoresist layer (400) from both direction vertical to the channel sidewalls until a first channel thickness obtained; j. removing the etch-stop layer (106). Harmful short channel effects can be restrained and device performance can be enhanced.
摘要翻译：本发明提供一种制造非对称FinFET的方法，包括：a。提供衬底（101）; b。在所述基板（101）上形成翅片（102），其中所述翅片（102）的宽度被定义为第二通道厚度; C。形成浅沟隔离; d。在鳍的中间的通道的顶表面和侧壁上形成牺牲栅叠层，并在鳍的两端形成源/漏区; e。沉积层间电介质层以覆盖牺牲栅极堆叠和源极/漏极区域，平坦化层间电介质层以暴露牺牲栅极堆叠; F。去除牺牲栅极堆叠以暴露通道; G。在所述通道的顶部上形成蚀刻停止层（106）; H。在源区附近的半导体结构的一部分上覆盖光致抗蚀剂膜（400）; 一世。从垂直于沟道侧壁的两个方向使未被光致抗蚀剂层（400）覆盖的沟道细化，直到得到第一沟道厚度; j。去除蚀刻停止层（106）。可以抑制有害的短通道效应，并可以提高设备性能。

5. 发明授权

US09640660B2 Asymmetrical FinFET structure and method of manufacturing same 有权
公开(公告)号：US09640660B2
公开(公告)日：2017-05-02
申请号：US14900594
申请日：2013-10-21
申请人： Institute of Microelectronics, Chinese Academy of Sciences
发明人： Haizhou Yin , Keke Zhang
IPC分类号： H01L29/78 , H01L29/66 , H01L29/06 , H01L29/40
CPC分类号： H01L29/785 , H01L29/0649 , H01L29/0688 , H01L29/401 , H01L29/66545 , H01L29/66818
摘要： A method of fabricating an asymmetric FinFET is provided in the invention, comprising: a. providing a substrate (101); b. forming a fin (102) on the substrate (101), wherein the width of the fin (102) is defined as a second channel thickness; c. forming a shallow trench isolation; d. forming a sacrificial gate stack on the top surface and sidewalls of the channel which is in the middle of the fin, and forming source/drain regions in both ends of the fin; e. depositing an interlayer dielectric layer to cover the sacrificial gate stack and the source/drain regions, planarizing the interlayer dielectric layer to expose sacrificial gate stack; f. removing the sacrificial gate stack to expose the channel; g. forming an etch-stop layer (106) on top of the channel; h. covering a photoresist film (400) on a portion of the semiconductor structure near the source region; i. thinning the channel which is not covered by the photoresist layer (400) from both direction vertical to the channel sidewalls until a first channel thickness obtained; j. removing the etch-stop layer (106). Harmful short channel effects can be restrained and device performance can be enhanced.

6. 发明申请

US20160276467A1 METHOD FOR MANUFACTURING FINFET 有权
标题翻译：制造FINFET的方法
公开(公告)号：US20160276467A1
公开(公告)日：2016-09-22
申请号：US14905465
申请日：2013-10-22
申请人： INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES
发明人： Yunfei Liu , Haizhou Yin , Keke Zhang
IPC分类号： H01L29/66 , H01L29/49 , H01L29/06
CPC分类号： H01L29/66795 , H01L21/823418 , H01L21/823431 , H01L29/0649 , H01L29/4966 , H01L29/66545 , H01L29/785 , H01L29/7853
摘要： A method of manufacturing a FinFET device is provided, comprising: a. providing a substrate (100); b. forming a fin (200) on the substrate; c. forming an shallow trench isolation structure (300) on the substrate; d. forming an sacrificial gate stack on the isolation structure, wherein the sacrificial gate stack intersects the fin; e. forming source/drain doping regions by ion implantation into the fin; f. depositing an interlayer dielectric layer (400) on the substrate; g. removing the sacrificial gate stack to form a sacrificial gate vacancy; h. forming an doped region (201) under the sacrificial gate vacancy; i. etching the shallow trench isolation structure (300) under the sacrificial gate vacancy until the top surface of the shallow trench isolation structure (300) levels with the bottom surface of the source/drain doping regions; j. forming a new gate stack in the sacrificial gate vacancy. Some advantages of the current invention may be, harmful effects produced in the source/drain regions by the triangle fin structure are eliminated, the device performance is improved, and the complexity of the process is reduce.
摘要翻译：提供一种制造FinFET器件的方法，包括：a。提供衬底（100）; b。在所述基板上形成翅片（200）; C。在衬底上形成浅沟槽隔离结构（300）; d。在所述隔离结构上形成牺牲栅极堆叠，其中所述牺牲栅极堆叠与所述鳍片相交; e。通过离子注入形成源极/漏极掺杂区域; F。在衬底上沉积层间电介质层（400）; G。去除牺牲栅极堆叠以形成牺牲栅极空位; H。在牺牲栅极空位下形成掺杂区域（201）; 一世。在牺牲栅极空位下蚀刻浅沟槽隔离结构（300），直到浅沟槽隔离结构（300）的顶表面与源极/漏极掺杂区域的底表面一致; j。在牺牲栅极空位中形成新的栅极堆叠。本发明的一些优点可以是消除由三角鳍结构在源极/漏极区域产生的有害影响，提高了器件性能，并且降低了工艺的复杂性。

7. 发明申请

US20180026183A1 NONVOLATILE RESISTIVE SWITCHING MEMORY DEVICE AND MANUFACTURING METHOD THEREOF 审中-公开
公开(公告)号：US20180026183A1
公开(公告)日：2018-01-25
申请号：US15546212
申请日：2015-05-14
申请人： Institute of Microelectronics, Chinese Academy of Sciences
发明人： Qi Liu , Ming Liu , Haitao Sun , Keke Zhang , Shibing Long , Hangbing Lv , Writam Banerjee , Kangwei Zhang
IPC分类号： H01L45/00
CPC分类号： H01L45/1246 , H01L45/08 , H01L45/085 , H01L45/1233 , H01L45/1266 , H01L45/142 , H01L45/143 , H01L45/146 , H01L45/16
摘要： A nonvolatile resistive switching memory, comprising an inert metal electrode, a resistive switching functional layer, and an easily oxidizable metal electrode, and characterized in that: a graphene barrier layer is inserted between the inert metal electrode and the resistive switching functional layer, which is capable of preventing the easily oxidizable metal ions from migrating into the inert metal electrode through the resistive switching functional layer under the action of electric field during the programming of the device. The manufacturing method therefore comprises adding a monolayer or multilayer graphene thin film between the inert electrode and the solid-state electrolyte resistive switching functional layer which services as a metal ion barrier layer to stop electrically-conductive metal filaments formed in the resistive switching layer from diffusing into the inert electrode layer during a RRAM device programming process, eliminating erroneous programming phenomenon occurring during the erasing process, improving device reliability.

8. 发明申请

US20160133696A1 FIN-FET STRUCTURE AND METHOD OF MANUFACTURING SAME 审中-公开
标题翻译： FIN-FET结构及其制造方法
公开(公告)号：US20160133696A1
公开(公告)日：2016-05-12
申请号：US14900491
申请日：2013-10-21
申请人： INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES
发明人： Haizhou Yin , Keke Zhang
IPC分类号： H01L29/06 , H01L29/10 , H01L29/78 , H01L29/66
CPC分类号： H01L29/0638 , H01L29/0653 , H01L29/1037 , H01L29/66537 , H01L29/66795 , H01L29/66803 , H01L29/785 , H01L29/7851
摘要： A method for fabricating a FinFET DEVICE is provided in the invention, comprising: a. providing a substrate (100);b. forming a fin (200) on the substrate (200); c. depositing a doping material layer (300) on the semiconductor structure formed after the step b; d. forming a first shallow trench isolation (400) on the semiconductor formed after the step c; e. removing a portion of the doping material layer (300) which is not covered by the first shallow trench isolation (400); f. performing an annealing process to form a doped region (500) in a channel region which is in the middle portion of the fin; g. forming a second shallow trench isolation (600) on the semiconductor formed after the step f; h. forming a source region and a drain region in opposite portions of the fin and forming a gate stack on the middle portion of the fin. Comparing with the prior art, punch through effect will be restrained and process complexity will be reduced.
摘要翻译：本发明提供一种制造FinFET器件的方法，包括：a。提供衬底（100）; b。在所述基板（200）上形成翅片（200）; C。在步骤b之后形成的半导体结构上沉积掺杂材料层（300）; d。在步骤c之后形成的半导体上形成第一浅沟槽隔离（400）; e。去除未被所述第一浅沟槽隔离（400）覆盖的所述掺杂材料层（300）的一部分; F。执行退火处理以在位于所述鳍片的中间部分的沟道区域中形成掺杂区域（500）; G。在步骤f之后形成的半导体上形成第二浅沟槽隔离（600）; H。在翅片的相对部分形成源极区域和漏极区域，并在鳍片的中间部分形成栅极叠层。与现有技术相比，冲击效应将受到限制，并且工艺复杂度将会降低。

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