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1. 发明授权

US09165920B2 Tunable protection system for integrated circuits 有权
标题翻译：集成电路可调保护系统
公开(公告)号：US09165920B2
公开(公告)日：2015-10-20
申请号：US11163349
申请日：2005-10-15
申请人： Indrajit Manna , Hin Kiong Yap , Keng Foo Lo , Jae Soo Park
发明人： Indrajit Manna , Hin Kiong Yap , Keng Foo Lo , Jae Soo Park
IPC分类号： H01L29/66 , H01L23/62 , H01L29/02 , H01L29/06 , H01L23/58 , H01L27/02
CPC分类号： H01L27/0262 , H01L29/7436 , H01L2924/0002 , H01L2924/00
摘要： A tunable protection system including forming a tunable trigger device providing an adjustable protection activation level, forming a circuit protection device providing protection for integrated circuits, and electrically connecting the tunable trigger device and the circuit protection device to an input/output pad.
摘要翻译：一种可调谐保护系统，包括形成提供可调保护激活电平的可调谐触发装置，形成为集成电路提供保护的电路保护装置，以及将可调谐触发装置和电路保护装置电连接到输入/输出垫。

2. 发明授权

US06998685B2 Electrostatic discharge protection device with complementary dual drain implant 有权
标题翻译：具有互补双漏极植入物的静电放电保护器件
公开(公告)号：US06998685B2
公开(公告)日：2006-02-14
申请号：US10662673
申请日：2003-09-15
申请人： Indrajit Manna , Keng Foo Lo , Pee Ya Tan , Michael Cheng
发明人： Indrajit Manna , Keng Foo Lo , Pee Ya Tan , Michael Cheng
IPC分类号： H01L23/62
CPC分类号： H01L29/0847 , H01L27/0266 , H01L29/1083 , H01L29/78 , H01L2924/0002 , H01L2924/00
摘要： Off-chip driver (OCD) NMOS transistors with ESD protection are formed by interposing an P-ESD implant between the N+ drain regions of OCD NMOS transistors and the N-well such that the P-ESD surrounds a section of the N-well. The P-ESD implant is dosed less than the N+ source/drain implants but higher than the N-well dose. In another embodiment, N-well doping is used along with P-ESD doping, where the P-ESD doping is chosen such that it counterdopes the N-well underneath the N+ drains. The N-well, however, still maintains electrical connection to the N+ drains. This procedure creates a larger surface under the area where the junction breakdown occurs and an increased radius of curvature of the junction. The P-ESD implant is covered by N-type on three sides creating better parasitic bipolar transistor characteristics.
摘要翻译：具有ESD保护的片外驱动器（OCD）NMOS晶体管通过在OCD NMOS晶体管的N +漏极区域和N阱之间插入P-ESD注入而形成，使得P-ESD围绕N阱的一部分。 P-ESD植入物的剂量小于N +源/漏植入物，但高于N阱剂量。在另一个实施例中，使用N阱掺杂以及P-ESD掺杂，其中选择P-ESD掺杂使得其对N +漏极下方的N阱进行反向。然而，N阱仍然保持与N +排水管的电气连接。该过程在结点发生的区域下面形成较大的表面，并且连接部的曲率半径增加。 P-ESD植入体在三面覆盖N型，产生更好的寄生双极晶体管特性。

3. 发明授权

US06936895B2 ESD protection device 失效
标题翻译： ESD保护装置
公开(公告)号：US06936895B2
公开(公告)日：2005-08-30
申请号：US10682055
申请日：2003-10-09
申请人： Indrajit Manna , Keng Foo Lo , Pee Ya Tan , Raymond Filippi
发明人： Indrajit Manna , Keng Foo Lo , Pee Ya Tan , Raymond Filippi
IPC分类号： H01L21/425 , H01L21/8234 , H01L23/62 , H01L27/02 , H01L29/49 , H01L29/868 , H01L31/075
CPC分类号： H01L29/4983 , H01L27/0255 , H01L27/0266 , H01L29/868 , H01L2924/0002 , H01L2924/00
摘要： A new method to form an integrated circuit device is achieved. The method comprises forming a dielectric layer overlying a semiconductor substrate. An intrinsic semiconductor layer is formed overlying the dielectric layer. The intrinsic semiconductor layer is patterned. A p+ region is formed in the intrinsic semiconductor layer. An n+ region is formed in the intrinsic semiconductor layer. The p+ region and said n+ region are laterally separated by an intrinsic region to thereby form a PIN diode device. A source region and a drain region are formed in the semiconductor substrate to thereby complete a MOSFET device. The PIN diode device is a gate electrode for the MOSFET device.
摘要翻译：实现了形成集成电路器件的新方法。该方法包括形成覆盖半导体衬底的电介质层。形成覆盖在介电层上的本征半导体层。本征半导体层被图案化。在本征半导体层中形成p +区。在本征半导体层中形成n +区。 p +区域和所述n +区域被本征区域横向分开，从而形成PIN二极管器件。在半导体衬底中形成源极区和漏极区，从而完成MOSFET器件。 PIN二极管器件是用于MOSFET器件的栅电极。

4. 发明授权

US07135743B2 Electrostatic discharge protection device with complementary dual drain implant 有权
公开(公告)号：US07135743B2
公开(公告)日：2006-11-14
申请号：US11291757
申请日：2005-12-01
申请人： Indrajit Manna , Keng Foo Lo , Pee Ya Tan , Michael Cheng
发明人： Indrajit Manna , Keng Foo Lo , Pee Ya Tan , Michael Cheng
IPC分类号： H01L23/62
CPC分类号： H01L29/0847 , H01L27/0266 , H01L29/1083 , H01L29/78 , H01L2924/0002 , H01L2924/00
摘要： Off-chip driver (OCD) NMOS transistors with ESD protection are formed by interposing an P-ESD implant between the N+ drain regions of OCD NMOS transistors and the N-well such that the P-ESD surrounds a section of the N-well. The P-ESD implant is dosed less than the N+ source/drain implants but higher than the N-well dose. In another embodiment, N-well doping is used along with P-ESD doping, where the P-ESD doping is chosen such that it counterdopes the N-well underneath the N+ drains. The N-well, however, still maintains electrical connection to the N+ drains. This procedure creates a larger surface under the area where the junction breakdown occurs and an increased radius of curvature of the junction. The P-ESD implant is covered by N-type on three sides creating better parasitic bipolar transistor characteristics.

5. 发明授权

US06835985B2 ESD protection structure 失效
标题翻译： ESD保护结构
公开(公告)号：US06835985B2
公开(公告)日：2004-12-28
申请号：US09733836
申请日：2000-12-09
申请人： Jun Cai , Guang Ping Hua , Jun Song , Keng Foo Lo
发明人： Jun Cai , Guang Ping Hua , Jun Song , Keng Foo Lo
IPC分类号： H01L2362
CPC分类号： H01L27/0266 , H01L2924/0002 , H01L2924/00
摘要： A transistor structure is provided for ESD protection in an integrated circuit device. A semiconductor substrate has source and drain diffusion regions and respective source and drain wells under the source and drain diffusion regions. A shallow trench isolation formed over the semiconductor substrate and into the semiconductor substrate separates the source and drain diffusion regions and a portion of the source and drain wells. Source and drain contact structures respectively formed on the shallow trench isolation over the source and drain diffusion regions and extend through the shallow trench isolation to contact the source and drain diffusion regions. An ion implantation is performed through the contact openings into the bottoms of the source and drain wells to control the device trigger voltage and position the discharge current far away from the surface, which increases the device ESD performance significantly.

6. 发明授权

US06265251B1 Method to fabricate a thick oxide MOS transistor for electrostatic discharge protection in an STI process 有权
标题翻译：在STI工艺中制造用于静电放电保护的厚氧化物MOS晶体管的方法
公开(公告)号：US06265251B1
公开(公告)日：2001-07-24
申请号：US09566471
申请日：2000-05-08
申请人： Cai Jun , Keng Foo Lo
发明人： Cai Jun , Keng Foo Lo
IPC分类号： H01L21338
CPC分类号： H01L29/6659 , H01L27/0266 , H01L2924/0002 , H01L2924/00
摘要： A new method of forming a thick oxide MOS transistor for electrostatic discharge protection in a standard sub-micron STI CMOS process for an integrated circuit device has been achieved. A first well and a second well are implanted. The wells are counter-doped to the substrate type. The first well forms the drain, and the second well forms the source. A thin oxide layer is formed. A polysilicon layer is deposited. The polysilicon layer is patterned to form a dummy floating gate. Ions are implanted into the first well to form a first lightly-doped region and into the second well to form a second lightly-doped region of the same type as the wells. The lightly-doped regions are self-aligned to the dummy floating gate. Sidewall spacers are formed on the floating dummy gates. Ions are implanted into the first well to form a first heavily-doped region and the second well to to form a second heavily-doped region of the same type as the wells. The heavily-doped regions are self-aligned to the sidewall spacers. An interlevel dielectric layer is deposited. A metal layer is deposited overlying the interlevel dielectric layer. The metal layer is patterned to form the gate electrode.
摘要翻译：已经实现了在用于集成电路器件的标准亚微米STI CMOS工艺中形成用于静电放电保护的厚氧化物MOS晶体管的新方法。植入第一口井和第二口井。这些阱被反掺杂到衬底类型。第一口井形成排水沟，第二口井形成排水沟。形成薄的氧化物层。沉积多晶硅层。图案化多晶硅层以形成虚拟浮动栅极。将离子注入到第一阱中以形成第一轻掺杂区域并进入第二阱以形成与孔相同类型的第二轻掺杂区域。轻掺杂区域与虚拟浮栅自对准。侧壁间隔件形成在浮动虚拟门上。将离子注入到第一阱中以形成第一重掺杂区，而第二阱形成与阱相同类型的第二重掺杂区。重掺杂区域与侧壁间隔物自对准。沉积层间电介质层。沉积层叠介质层上的金属层。图案化金属层以形成栅电极。

7. 发明授权

US07205612B2 Fully silicided NMOS device for electrostatic discharge protection 有权
标题翻译：用于静电放电保护的全硅化NMOS器件
公开(公告)号：US07205612B2
公开(公告)日：2007-04-17
申请号：US10978627
申请日：2004-11-01
申请人： Jun Cai , Keng Foo Lo
发明人： Jun Cai , Keng Foo Lo
IPC分类号： H01L23/62 , H01L29/72 , H01L29/74 , H01L31/111 , H01L31/119
CPC分类号： H01L29/0847 , H01L27/0266 , H01L29/1083 , H01L29/7833 , Y10S257/90
摘要： A device and method are described for forming a grounded gate NMOS (GGNMOS) device used to provide protection against electrostatic discharge (ESD) in an integrated circuit (IC). The device is achieved by adding n-wells below the source and drain regions. By tailoring the dopant concentration profiles of the p-well and n-wells provided in the fabrication process, peak dopant concentrations are moved below the silicon surface. This moves ESD conduction deeper into the IC where thermal conductivity is improved, thereby avoiding thermal damage occurring with surface conduction. The device does not require a salicidation block or additional implantation and uses standard NMOS fabrication processing steps, making it advantageous over prior art solutions.
摘要翻译：描述了用于形成用于提供集成电路（IC）中的静电放电（ESD）保护的接地栅极NMOS（GGNMOS）器件的器件和方法。该器件通过在源极和漏极区域下方添加n阱来实现。通过调整在制造过程中提供的p阱和n阱的掺杂浓度分布，峰值掺杂剂浓度移动到硅表面以下。这将ESD传导更深地传导到IC中，其中导热性得到改善，从而避免了表面传导引起的热损伤。该器件不需要一个盐化阻滞或额外的植入，并且使用标准的NMOS制造处理步骤，使其优于现有技术的解决方案。

8. 发明授权

US06830966B2 Fully silicided NMOS device for electrostatic discharge protection 失效
标题翻译：用于静电放电保护的全硅化NMOS器件
公开(公告)号：US06830966B2
公开(公告)日：2004-12-14
申请号：US10170248
申请日：2002-06-12
申请人： Jun Cai , Keng Foo Lo
发明人： Jun Cai , Keng Foo Lo
IPC分类号： H01L21336
CPC分类号： H01L29/0847 , H01L27/0266 , H01L29/1083 , H01L29/7833 , Y10S257/90
摘要： A device and method are described for forming a grounded gate NMOS (GGNMOS) device used to provide protection against electrostatic discharge (ESD) in an integrated circuit (IC). The device is achieved by adding n-wells below the source and drain regions. By tailoring the dopant concentration profiles of the p-well and n-wells provided in the fabrication process, peak dopant concentrations are moved below the silicon surface. This moves ESD conduction deeper into the IC where thermal conductivity is improved, thereby avoiding thermal damage occurring with surface conduction. The device does not require a salicidation block or additional implantation and uses standard NMOS fabrication processing steps, making it advantageous over prior art solutions.
摘要翻译：描述了用于形成用于提供集成电路（IC）中的静电放电（ESD）保护的接地栅极NMOS（GGNMOS）器件的器件和方法。该器件通过在源极和漏极区域下方添加n阱来实现。通过调整在制造过程中提供的p阱和n阱的掺杂浓度分布，峰值掺杂剂浓度移动到硅表面以下。这将ESD传导更深地传导到IC中，其中导热性得到改善，从而避免了表面传导引起的热损伤。该器件不需要一个盐化阻滞或额外的植入，并且使用标准的NMOS制造处理步骤，使其优于现有技术的解决方案。

9. 发明授权

US06417541B1 ESD protection network with field oxide device and bonding pad 失效
标题翻译： ESD保护网络与场氧化物和接合焊盘
公开(公告)号：US06417541B1
公开(公告)日：2002-07-09
申请号：US09759492
申请日：2001-01-12
申请人： Jun Cai , Keng Foo Lo
发明人： Jun Cai , Keng Foo Lo
IPC分类号： H01L2362
CPC分类号： H01L27/0277
摘要： An electrostatic discharge protection structure is provided with a dielectric gate, source and drain contacts, and a semiconductor substrate. The semiconductor substrate is of a first conductivity type having the dielectric gate disposed partially on its surface. The source and drain contacts are connected to source and drain diffusion regions of a second conductivity type separated by the dielectric gate. Deep source and drain wells of the second conductivity type respectively disposed under the source and drain diffusion regions define a channel region of the first conductivity type. The channel region is doped so that the surface breakdown voltage is exceeded before the subsurface depletion region punch-through voltage is exceeded between the deep source and drain wells upon an electrostatic discharge at the drain contact.
摘要翻译：静电放电保护结构设置有电介质栅极，源极和漏极触点以及半导体衬底。半导体衬底是第一导电类型，其中介电栅极部分地设置在其表面上。源极和漏极触点连接到由电介质栅极隔开的第二导电类型的源极和漏极扩散区域。分别设置在源极和漏极扩散区域下方的第二导电类型的深源极和漏极阱限定第一导电类型的沟道区。在漏极接触处的静电放电之后，在深源极和漏极阱之间超过地下耗尽区穿透电压之前，掺杂沟道区域，使得超过表面击穿电压。

10. 发明授权

US07064358B2 Triggered back-to-back diodes for ESD protection in triple-well CMOS process 失效
标题翻译：触发式背对背二极管，用于三阱CMOS工艺中的ESD保护
公开(公告)号：US07064358B2
公开(公告)日：2006-06-20
申请号：US10743596
申请日：2003-12-22
申请人： Indrajlt Manna , Keng Foo Lo , Pee Ya Tan , Raymond Filippi
发明人： Indrajlt Manna , Keng Foo Lo , Pee Ya Tan , Raymond Filippi
IPC分类号： H01L29/72
CPC分类号： H01L27/0259
摘要： An embodiment is a Electro Static Discharge (ESD) protection device comprising: a n-doped region and a p-doped region in a p-well in a semiconductor structure. The n-doped region and the p-doped region are spaced. A n-well and a deep n-well surrounding the p-well on the sides and bottom. A first I/O pad connected to the n-doped region. A trigger circuit connected the first I/O pad and the p-doped region. A second I/O pad connected to the n-well. A parasitic bipolar transistor is comprised of the n-doped region that functions as a collector terminal, the P-well that functions as a base terminal, and the deep N-well that functions as the emitter terminal. Whereby under an ESD condition, the p-well is charged positive using the trigger circuit and the parasitic bipolar transistor can be turned on.
摘要翻译：一个实施例是一种静电放电（ESD）保护装置，其包括：半导体结构中的p阱中的n掺杂区域和p掺杂区域。 n掺杂区域和p掺杂区域间隔开。围绕p-well的两侧和底部的n井和深n井。连接到n掺杂区域的第一I / O焊盘。连接第一I / O焊盘和p掺杂区域的触发电路。连接到n阱的第二个I / O焊盘。寄生双极晶体管由用作集电极端子的n掺杂区域，用作基极端子的P阱和用作发射极端子的深N阱组成。在ESD条件下，使用触发电路将p阱充电为正极，并且可以接通寄生双极晶体管。

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