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1. 发明授权

US06835985B2 ESD protection structure 失效
标题翻译： ESD保护结构
公开(公告)号：US06835985B2
公开(公告)日：2004-12-28
申请号：US09733836
申请日：2000-12-09
申请人： Jun Cai , Guang Ping Hua , Jun Song , Keng Foo Lo
发明人： Jun Cai , Guang Ping Hua , Jun Song , Keng Foo Lo
IPC分类号： H01L2362
CPC分类号： H01L27/0266 , H01L2924/0002 , H01L2924/00
摘要： A transistor structure is provided for ESD protection in an integrated circuit device. A semiconductor substrate has source and drain diffusion regions and respective source and drain wells under the source and drain diffusion regions. A shallow trench isolation formed over the semiconductor substrate and into the semiconductor substrate separates the source and drain diffusion regions and a portion of the source and drain wells. Source and drain contact structures respectively formed on the shallow trench isolation over the source and drain diffusion regions and extend through the shallow trench isolation to contact the source and drain diffusion regions. An ion implantation is performed through the contact openings into the bottoms of the source and drain wells to control the device trigger voltage and position the discharge current far away from the surface, which increases the device ESD performance significantly.

2. 发明授权

US06855609B2 Method of manufacturing ESD protection structure 失效
标题翻译：制造ESD保护结构的方法
公开(公告)号：US06855609B2
公开(公告)日：2005-02-15
申请号：US10670918
申请日：2003-09-24
申请人： Jun Cai , Guang Ping Hua , Jun Song , Keng Foo Lo
发明人： Jun Cai , Guang Ping Hua , Jun Song , Keng Foo Lo
IPC分类号： H01L27/02 , H01L21/336
CPC分类号： H01L27/0266 , H01L2924/0002 , H01L2924/00
摘要： A transistor structure is manufactured for ESD protection in an integrated circuit device. A semiconductor substrate has source and drain diffusion regions and respective source and drain wells under the source and drain diffusion regions. A shallow trench isolation formed over the semiconductor substrate and into the semiconductor substrate separates the source and drain diffusion regions and a portion of the source and drain wells. Source and drain contact structures respectively formed on the shallow trench isolation over the source and drain diffusion regions and extend through the shallow trench isolation to contact the source and drain diffusion regions. An ion implantation is performed through the contact openings into the bottoms of the source and drain wells to control the device trigger voltage and position the discharge current far away from the surface, which increases the device ESD performance significantly.
摘要翻译：在集成电路器件中制造用于ESD保护的晶体管结构。半导体衬底具有源极和漏极扩散区域以及源极和漏极扩散区域下的源极和漏极阱。形成在半导体衬底上并进入半导体衬底的浅沟槽隔离件分离源极和漏极扩散区域以及源极和漏极阱的一部分。源极和漏极接触结构分别形成在源极和漏极扩散区上的浅沟槽隔离上，并延伸穿过浅沟槽隔离以接触源极和漏极扩散区域。通过接触开口进入离子注入到源阱和漏极的底部，以控制器件触发电压并将放电电流定位远离表面，从而显着提高器件ESD性能。

3. 发明授权

US07205612B2 Fully silicided NMOS device for electrostatic discharge protection 有权
标题翻译：用于静电放电保护的全硅化NMOS器件
公开(公告)号：US07205612B2
公开(公告)日：2007-04-17
申请号：US10978627
申请日：2004-11-01
申请人： Jun Cai , Keng Foo Lo
发明人： Jun Cai , Keng Foo Lo
IPC分类号： H01L23/62 , H01L29/72 , H01L29/74 , H01L31/111 , H01L31/119
CPC分类号： H01L29/0847 , H01L27/0266 , H01L29/1083 , H01L29/7833 , Y10S257/90
摘要： A device and method are described for forming a grounded gate NMOS (GGNMOS) device used to provide protection against electrostatic discharge (ESD) in an integrated circuit (IC). The device is achieved by adding n-wells below the source and drain regions. By tailoring the dopant concentration profiles of the p-well and n-wells provided in the fabrication process, peak dopant concentrations are moved below the silicon surface. This moves ESD conduction deeper into the IC where thermal conductivity is improved, thereby avoiding thermal damage occurring with surface conduction. The device does not require a salicidation block or additional implantation and uses standard NMOS fabrication processing steps, making it advantageous over prior art solutions.
摘要翻译：描述了用于形成用于提供集成电路（IC）中的静电放电（ESD）保护的接地栅极NMOS（GGNMOS）器件的器件和方法。该器件通过在源极和漏极区域下方添加n阱来实现。通过调整在制造过程中提供的p阱和n阱的掺杂浓度分布，峰值掺杂剂浓度移动到硅表面以下。这将ESD传导更深地传导到IC中，其中导热性得到改善，从而避免了表面传导引起的热损伤。该器件不需要一个盐化阻滞或额外的植入，并且使用标准的NMOS制造处理步骤，使其优于现有技术的解决方案。

4. 发明授权

US06830966B2 Fully silicided NMOS device for electrostatic discharge protection 失效
标题翻译：用于静电放电保护的全硅化NMOS器件
公开(公告)号：US06830966B2
公开(公告)日：2004-12-14
申请号：US10170248
申请日：2002-06-12
申请人： Jun Cai , Keng Foo Lo
发明人： Jun Cai , Keng Foo Lo
IPC分类号： H01L21336
CPC分类号： H01L29/0847 , H01L27/0266 , H01L29/1083 , H01L29/7833 , Y10S257/90
摘要： A device and method are described for forming a grounded gate NMOS (GGNMOS) device used to provide protection against electrostatic discharge (ESD) in an integrated circuit (IC). The device is achieved by adding n-wells below the source and drain regions. By tailoring the dopant concentration profiles of the p-well and n-wells provided in the fabrication process, peak dopant concentrations are moved below the silicon surface. This moves ESD conduction deeper into the IC where thermal conductivity is improved, thereby avoiding thermal damage occurring with surface conduction. The device does not require a salicidation block or additional implantation and uses standard NMOS fabrication processing steps, making it advantageous over prior art solutions.
摘要翻译：描述了用于形成用于提供集成电路（IC）中的静电放电（ESD）保护的接地栅极NMOS（GGNMOS）器件的器件和方法。该器件通过在源极和漏极区域下方添加n阱来实现。通过调整在制造过程中提供的p阱和n阱的掺杂浓度分布，峰值掺杂剂浓度移动到硅表面以下。这将ESD传导更深地传导到IC中，其中导热性得到改善，从而避免了表面传导引起的热损伤。该器件不需要一个盐化阻滞或额外的植入，并且使用标准的NMOS制造处理步骤，使其优于现有技术的解决方案。

5. 发明授权

US06417541B1 ESD protection network with field oxide device and bonding pad 失效
标题翻译： ESD保护网络与场氧化物和接合焊盘
公开(公告)号：US06417541B1
公开(公告)日：2002-07-09
申请号：US09759492
申请日：2001-01-12
申请人： Jun Cai , Keng Foo Lo
发明人： Jun Cai , Keng Foo Lo
IPC分类号： H01L2362
CPC分类号： H01L27/0277
摘要： An electrostatic discharge protection structure is provided with a dielectric gate, source and drain contacts, and a semiconductor substrate. The semiconductor substrate is of a first conductivity type having the dielectric gate disposed partially on its surface. The source and drain contacts are connected to source and drain diffusion regions of a second conductivity type separated by the dielectric gate. Deep source and drain wells of the second conductivity type respectively disposed under the source and drain diffusion regions define a channel region of the first conductivity type. The channel region is doped so that the surface breakdown voltage is exceeded before the subsurface depletion region punch-through voltage is exceeded between the deep source and drain wells upon an electrostatic discharge at the drain contact.
摘要翻译：静电放电保护结构设置有电介质栅极，源极和漏极触点以及半导体衬底。半导体衬底是第一导电类型，其中介电栅极部分地设置在其表面上。源极和漏极触点连接到由电介质栅极隔开的第二导电类型的源极和漏极扩散区域。分别设置在源极和漏极扩散区域下方的第二导电类型的深源极和漏极阱限定第一导电类型的沟道区。在漏极接触处的静电放电之后，在深源极和漏极阱之间超过地下耗尽区穿透电压之前，掺杂沟道区域，使得超过表面击穿电压。

6. 发明授权

US06310380B1 Electrostatic discharge protection transistor structure with a trench extending through the source or drain silicide layers 有权
标题翻译：具有延伸穿过源极或漏极硅化物层的沟槽的静电放电保护晶体管结构
公开(公告)号：US06310380B1
公开(公告)日：2001-10-30
申请号：US09519838
申请日：2000-03-06
申请人： Jun Cai , Keng Foo Lo
发明人： Jun Cai , Keng Foo Lo
IPC分类号： H01L2362
CPC分类号： H01L29/0847 , H01L27/0277 , H01L29/0653 , H01L29/456 , H01L29/7833
摘要： A MOS transistor structure is provided for ESD protection in an integrated circuit device. A trench controls salicide deposition to prevent hot spot formation and allows control of the turn-on voltage. The structure includes source and drain diffusion regions formed in the silicon substrate, a gate, and n-wells formed under the source and drain diffusions on either side of the gate. A drain trench is located to separate the salicide between a drain contact and the gate edge, and by controlling the size and location of the drain trench, the turn-on voltages can be controlled; i.e., the turn-on voltage due to drain diffusion region to substrate avalanche breakdown and the turn-on voltage due to source well to drain well punch-through. Thus, very low turn-on voltages may be achieved for ESD protection.
摘要翻译：在集成电路器件中提供用于ESD保护的MOS晶体管结构。沟槽控制硅化物沉积以防止热点形成并且允许控制导通电压。该结构包括在硅衬底中形成的源极和漏极扩散区域，栅极和形成在栅极两侧的源极和漏极扩散之下的n阱。漏极沟槽被定位成在漏极接触和栅极边缘之间分离硅化物，并且通过控制漏极沟槽的尺寸和位置，可以控制导通电压; 即由于漏极扩散区域到衬底雪崩击穿引起的导通电压以及由于源极而导致漏极穿透的导通电压。因此，ESD保护可以实现非常低的导通电压。

7. 发明授权

US06329253B1 Thick oxide MOS device used in ESD protection circuit 有权
标题翻译： ESD保护电路中使用的厚氧化物MOS器件
公开(公告)号：US06329253B1
公开(公告)日：2001-12-11
申请号：US09434922
申请日：1999-11-05
申请人： Jun Song , Yonqzang Zhang , Shyue Fong Quek , Ting Cheong Ang , Jun Cai , Puay Ing Ong
发明人： Jun Song , Yonqzang Zhang , Shyue Fong Quek , Ting Cheong Ang , Jun Cai , Puay Ing Ong
IPC分类号： H01L21336
CPC分类号： H01L29/66621 , H01L21/76224 , H01L27/0266 , H01L29/7834
摘要： A method for forming a novel thick oxide electrostatic discharge device using shallow trench isolation technology is described. A trench is etched into a semiconductor substrate. An oxide layer is deposited overlying the semiconductor substrate and filling the trench. The oxide within the trench is partially etched away leaving the oxide on the sidewalls and bottom of the trench. The oxide is polished away to the surface of the semiconductor substrate whereby oxide remains only on the sidewalls and bottom of the trench. A gate is formed within the trench whereby the gate is surrounded by the oxide. First ions are implanted into the semiconductor substrate adjacent to the trench to form N-wells. Second ions are implanted into the semiconductor substrate in a top portion of the N-wells to form source/drain regions. Third ions are implanted into the semiconductor substrate underlying the N-wells and underlying the trench to form electrostatic discharge trigger taps. This completes formation of an electrostatic discharge device in the fabrication of integrated circuits.
摘要翻译：描述了使用浅沟槽隔离技术形成新的厚氧化物静电放电装置的方法。将沟槽蚀刻到半导体衬底中。沉积在半导体衬底上并填充沟槽的氧化物层。部分地蚀刻沟槽内的氧化物，留下沟槽的侧壁和底部上的氧化物。氧化物被抛光到半导体衬底的表面，由此氧化物仅保留在沟槽的侧壁和底部上。在沟槽内形成栅极，由此栅极被氧化物包围。将第一离子注入到与沟槽相邻的半导体衬底中以形成N阱。在N阱的顶部将第二离子注入到半导体衬底中以形成源/漏区。将第三离子注入位于N阱下方并位于沟槽下方的半导体衬底中以形成静电放电触发抽头。这就形成了集成电路制造中的静电放电装置。

8. 发明授权

US09745227B2 Method for applying discriminating layer onto porous ceramic filters 有权
公开(公告)号：US09745227B2
公开(公告)日：2017-08-29
申请号：US13812515
申请日：2011-08-17
申请人： Jun Cai , Aleksander J. Pyzik , James J. O'Brien , Robin P. Ziebarth
发明人： Jun Cai , Aleksander J. Pyzik , James J. O'Brien , Robin P. Ziebarth
IPC分类号： C04B38/00 , B05D5/00 , B01J35/04 , B01J37/02 , C04B41/00 , C04B41/45 , C04B41/87 , B01J23/10 , B01J29/40 , C04B111/00
CPC分类号： C04B38/0038 , B01J23/10 , B01J29/40 , B01J35/04 , B01J37/0215 , B01J37/0246 , B05D5/005 , B05D2203/30 , C04B41/009 , C04B41/4545 , C04B41/87 , C04B2111/00793 , C04B35/00 , C04B38/0006 , C04B35/185 , C04B41/455 , C04B41/457 , C04B41/5037 , C04B41/5027
摘要： A porous discriminating layer is formed on a ceramic support having at least one porous wall by (a) establishing a flow of a gas stream containing agglomerates of particles and (b) calcining said deposited layer to form the discriminating layer. At least a portion of the particles are of a sinter-resistant material or a sinter-resistant material precursor. The particles have a size from 0.01 to 5 microns and the agglomerates have a size of from 10 to 200 microns. This method is an inexpensive and effective route to forming a discriminating layer onto the porous wall.

9. 发明授权

US09303872B2 Fuel injector 有权
标题翻译：喷油器
公开(公告)号：US09303872B2
公开(公告)日：2016-04-05
申请号：US13233127
申请日：2011-09-15
申请人： Mark Allan Hadley , Jun Cai , Lucas John Stoia , Geoffrey David Myers , Jayaprakash Natarajan
发明人： Mark Allan Hadley , Jun Cai , Lucas John Stoia , Geoffrey David Myers , Jayaprakash Natarajan
IPC分类号： F23R3/20 , F23R3/34
CPC分类号： F23R3/20 , F23R3/346 , F23R2900/03341
摘要： A fuel injector is provided and includes a member defining a flowpath through which a first fluid flows, the flowpath having a cross-section with transverse elongate and short axes, a head defining a plenum storing a supply of a second fluid and a system fluidly coupled to the flowpath and the plenum to inject the second fluid from the plenum and into the flowpath at first and second locations along the elongate axis. The injected second fluid is formed into jets at the first and second locations, the first fluid entrains the jets such that the injected second fluid flows through the flowpath and mixes with the first fluid, and the short axis has a sufficient dimension such that the jets remain spaced from a sidewall of the member.
摘要翻译：燃料喷射器被设置并且包括限定第一流体流过的流路的构件，流路具有横向具有横向细长轴线和短轴线的横截面，头部限定储存第二流体供应的气室和流体耦合的系统到流路和通气室，以将来自气室的第二流体注入到沿着细长轴线的第一和第二位置处的流路中。注入的第二流体在第一和第二位置处形成为射流，第一流体夹带射流，使得注入的第二流体流过流路并与第一流体混合，并且短轴具有足够的尺寸，使得喷嘴保持与构件的侧壁间隔开。

10. 发明授权

US09080938B2 Extremum seeking algorithm in a variable time interval to detect anode pressure sensor stuck failure in a fuel cell system 有权
标题翻译：极值寻求算法在可变时间间隔内检测燃料电池系统中的阳极压力传感器卡死故障
公开(公告)号：US09080938B2
公开(公告)日：2015-07-14
申请号：US13560352
申请日：2012-07-27
申请人： Jun Cai , Daniel C. Di Fiore , Steven R. Falta , Sergio E. Garcia , Carol A. Galskoy
发明人： Jun Cai , Daniel C. Di Fiore , Steven R. Falta , Sergio E. Garcia , Carol A. Galskoy
IPC分类号： G01L27/00 , H01M8/04 , G01N27/00
CPC分类号： G01N27/007 , H01M8/04 , H01M8/0438 , H01M8/04388 , H01M8/04402 , H01M8/04425 , H01M8/04649 , H01M8/04664 , H01M8/04686 , H01M8/04753 , Y02E60/50
摘要： A system and method for detecting an anode pressure sensor failure in a fuel cell system. The system and method include a controller that sets an initial minimum anode pressure sensor value and an initial maximum anode pressure sensor value. The controller determines a desired time interval for sampling anode pressure measurements and determines a total number of samples of anode pressure measurements to be collected by the controller from an anode pressure sensor. The controller also compares a pressure difference between the initial or a measured minimum anode pressure and the initial or a measured maximum anode pressure to a predetermined pressure difference threshold and sets a pressure sensor fault if the pressure difference between the initial or measured minimum anode pressure and the initial or maximum anode pressure is less than the predetermined pressure difference threshold.
摘要翻译：一种用于检测燃料电池系统中的阳极压力传感器故障的系统和方法。该系统和方法包括设置初始最小阳极压力传感器值和初始最大阳极压力传感器值的控制器。控制器确定用于采样阳极压力测量值的期望时间间隔，并确定由控制器从阳极压力传感器收集的阳极压力测量的样本总数。控制器还将初始或测量的最小阳极压力与初始或测量的最大阳极压力之间的压力差与预定的压力差阈值进行比较，并设定压力传感器故障，如果初始或测量的最小阳极压力与初始或最大阳极压力小于预定的压力差阈值。

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