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1. 发明申请

US20130188426A1 NONVOLATILE MEMORY DEVICE, NONVOLATILE MEMORY SYSTEM, PROGRAM METHOD THEREOF, AND OPERATION METHOD OF CONTROLLER CONTROLLING THE SAME 有权
标题翻译：非易失性存储器件，非易失性存储器系统，其程序方法及其控制器的操作方法
公开(公告)号：US20130188426A1
公开(公告)日：2013-07-25
申请号：US13618605
申请日：2012-09-14
申请人： Il Han PARK , Yongsung CHO , Sang-Soo PARK
发明人： Il Han PARK , Yongsung CHO , Sang-Soo PARK
IPC分类号： G11C16/10
CPC分类号： G11C16/10 , G11C16/24 , G11C16/3427
摘要： According to example embodiments, a nonvolatile memory device includes a first memory cell configured to store a first data pattern, a second memory cell configured to be programmed using a program voltage, and a coupling program control unit. The coupling program control unit may be configured to perform a verification operation for verifying whether the first memory cell is programmed with the first data pattern. The verification operation may provide to the first memory cell a verification voltage corresponding to the first data pattern. The coupling program control unit may be configured to end programming the second memory cell when the verification operation on the first memory cell indicates a pass.
摘要翻译：根据示例性实施例，非易失性存储器件包括被配置为存储第一数据模式的第一存储器单元，被配置为使用编程电压进行编程的第二存储器单元和耦合程序控制单元。耦合程序控制单元可以被配置为执行用于验证第一存储单元是否用第一数据模式编程的验证操作。验证操作可以向第一存储器单元提供对应于第一数据模式的验证电压。耦合程序控制单元可以被配置为当对第一存储器单元的验证操作指示通过时，结束对第二存储器单元的编程。

2. 发明申请

US20090061639A1 METHOD FOR FABRICATING SEMICONDUCTOR DEVICE 失效
标题翻译：制造半导体器件的方法
公开(公告)号：US20090061639A1
公开(公告)日：2009-03-05
申请号：US11951195
申请日：2007-12-05
申请人： Sang-Soo PARK , Su-Bum Shin
发明人： Sang-Soo PARK , Su-Bum Shin
IPC分类号： H01L21/302
CPC分类号： H01L21/31122 , H01L21/3081 , H01L21/31116 , H01L21/31144
摘要： A method for fabricating a semiconductor device includes stacking a spin on carbon (SOC) layer and an multifunction hard mask (MFHM) layer on a substrate, forming a photoresist pattern over the MFHM layer, first etching the MFHM layer using a first amount of a fluorine-based gas, second etching the MFHM layer using a second amount of a fluorine-based gas, wherein the second amount is less than the first amount, etching the SOC layer using the MFHM layer as an etch barrier, and etching the substrate using the SOC layer and the MFHM layer as an etch barrier.
摘要翻译：一种制造半导体器件的方法包括在基片上层叠自旋碳（SOC）层和多功能硬掩模（MFHM）层，在MFHM层上形成光致抗蚀剂图案，首先使用第一量的氟基气体，使用第二量的氟基气体二次蚀刻MFHM层，其中第二量小于第一量，使用MFHM层蚀刻SOC层作为蚀刻阻挡层，并使用 SOC层和MFHM层作为蚀刻阻挡层。

3. 发明申请

US20170125116A1 NONVOLATILE MEMORY DEVICE, STORAGE DEVICE INCLUDING NONVOLATILE MEMORY DEVICE AND OPERATING METHOD OF NONVOLATILE MEMORY DEVICE 有权
公开(公告)号：US20170125116A1
公开(公告)日：2017-05-04
申请号：US15340957
申请日：2016-11-01
申请人： Dongkyo SHIM , Sang-Soo PARK
发明人： Dongkyo SHIM , Sang-Soo PARK
IPC分类号： G11C16/34 , G11C16/10 , G11C16/04 , G11C16/08 , G11C16/16 , G11C16/26
CPC分类号： G11C16/3445 , G11C11/5635 , G11C16/0483 , G11C16/08 , G11C16/10 , G11C16/14 , G11C16/16 , G11C16/26
摘要： A nonvolatile memory device may include a memory cell array, an address decoder circuit, a page buffer circuit, and a control logic circuit. An erase operation includes iteratively performing an erase loop which includes an erase section where an erase voltage is applied to the memory cells of the selected memory block and an erase verification section where the memory cells of the selected memory block are verified using an erase verification voltage. If the memory cells of the selected memory block are determined as an erase pass in the erase verification section, the control logic circuit monitors the memory cells of the selected memory block. If the monitored result indicates that the memory cells of the selected memory block are at an abnormal state, the control logic circuit applies an extra erase voltage to the memory cells of the selected memory block.

4. 发明申请

US20100033084A1 ORGANIC ELECTROLUMINESCENCE DISPLAY INCLUDING A SPACER AND METHOD FOR FABRICATING THE SAME 有权
标题翻译：包括间隔物的有机电致发光显示器及其制造方法
公开(公告)号：US20100033084A1
公开(公告)日：2010-02-11
申请号：US12489167
申请日：2009-06-22
申请人： Jung-Woo KO , Sang-Shin LEE , Sang-Soo PARK , Taek-Kyo KANG , Seung-Ju HONG
发明人： Jung-Woo KO , Sang-Shin LEE , Sang-Soo PARK , Taek-Kyo KANG , Seung-Ju HONG
IPC分类号： H01J1/54 , H01J9/20
CPC分类号： H01L27/3246 , H01L51/5012
摘要： Embodiments of the present disclosure provide an organic electroluminescence display device. The display device may include a set of multi-directional spacers that are interposed between the pixels of the display. In one embodiment, the spacers are positioned in both lengthwise and crosswise directions. In another embodiment, the spacers include a first portion that is extends lengthwise between pixels and one or more portions that extend laterally from the first portion between pixels. In yet another embodiment, the spacers include portions that extend in multiple directions between pixels. The spacers may substantially surround each of the pixels and may serve as a boundary, for example, that prevents organic material for one pixel from being incorrectly deposited in another pixel. The spacers can be configured as a support structure, such as, for a metal mask during fabrication of the display device. In addition, the multi-directional aspect of the spacers may be useful in protecting the pixels from damage, such as, when a metal mask is moved during mounting or during fabrication of the display device.
摘要翻译：本公开的实施方案提供了一种有机电致发光显示装置。显示装置可以包括插入在显示器的像素之间的一组多方向间隔物。在一个实施例中，间隔件沿长度方向和横向方向定位。在另一个实施例中，间隔物包括在像素之间纵向延伸的第一部分和从像素之间的第一部分横向延伸的一个或多个部分。在另一个实施例中，间隔物包括在像素之间沿多个方向延伸的部分。间隔件可以基本上围绕每个像素并且可以用作边界，例如，阻止一个像素的有机材料被错误地沉积在另一个像素中。间隔件可以被配置为支撑结构，例如在显示装置制造期间用于金属掩模。此外，间隔物的多方面方面可用于保护像素免受损坏，例如当金属掩模在安装期间或在制造显示装置期间移动时。

5. 发明申请

US20170133087A1 NONVOLATILE MEMORY DEVICE AND READ METHOD THEREOF 审中-公开
公开(公告)号：US20170133087A1
公开(公告)日：2017-05-11
申请号：US15341253
申请日：2016-11-02
申请人： Sang-Soo PARK , June-Hong PARK , Dongkyo SHIM
发明人： Sang-Soo PARK , June-Hong PARK , Dongkyo SHIM
IPC分类号： G11C11/56 , G11C16/28 , G11C16/08
CPC分类号： G11C11/5671 , G11C11/5642 , G11C16/08 , G11C16/10 , G11C16/28 , G11C29/021 , G11C29/028 , G11C29/52
摘要： Disclosed is a nonvolatile memory device. The nonvolatile memory device includes a cell array including a plurality of memory cells, a page buffer including a plurality of latch sets, and a control logic. The page buffer is connected to the cell array through bit lines. The latch sets respectively are configured to sense data from selected memory cells among the memory cells through the bit lines. The latch sets respectively are configured to perform a plurality of read operations to determine one data state. The latch sets are respectively configured to store results of the read operations. The control logic configured to control the page buffer such that the latch sets sequentially and respectively store the results of the read operations, to compare data stored in the latch sets with each other, and to select one latch set among the latch sets based on the comparison result.

6. 发明申请

US20080160653A1 METHOD FOR FABRICATING A SEMICONDUCTOR DEVICE 失效
标题翻译：制造半导体器件的方法
公开(公告)号：US20080160653A1
公开(公告)日：2008-07-03
申请号：US11765673
申请日：2007-06-20
申请人： Sang-Soo PARK , Chang-Heon Park , Dong-Ryeol Lee
发明人： Sang-Soo PARK , Chang-Heon Park , Dong-Ryeol Lee
IPC分类号： H01L21/311 , H01L21/66
CPC分类号： H01L21/32139 , H01L21/31116 , H01L21/31122 , H01L21/31138 , H01L21/3146 , H01L21/318
摘要： A method for fabricating a semiconductor device includes forming an etch target layer over a substrate that includes a cell region and a peripheral region. A first hard mask layer, a second hard mask layer, and an anti-reflective coating layer are formed over the etch target layer. A photosensitive pattern is formed over the anti-reflective coating layer. The anti-reflective coating layer is etched to have a width smaller than the width of the photosensitive pattern. The second hard mask layer is etched. A main etching and an over-etching are performed on the first hard mask layer. The etch target layer is then etched.
摘要翻译：一种制造半导体器件的方法包括在包括单元区域和周边区域的衬底上形成蚀刻目标层。第一硬掩模层，第二硬掩模层和抗反射涂层形成在蚀刻目标层上。在抗反射涂层上形成感光图案。抗反射涂层被蚀刻成具有比感光图案的宽度小的宽度。蚀刻第二硬掩模层。在第一硬掩模层上进行主蚀刻和过蚀刻。然后蚀刻目标层。

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