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1. 发明申请

US20080160653A1 METHOD FOR FABRICATING A SEMICONDUCTOR DEVICE 失效
标题翻译：制造半导体器件的方法
公开(公告)号：US20080160653A1
公开(公告)日：2008-07-03
申请号：US11765673
申请日：2007-06-20
申请人： Sang-Soo PARK , Chang-Heon Park , Dong-Ryeol Lee
发明人： Sang-Soo PARK , Chang-Heon Park , Dong-Ryeol Lee
IPC分类号： H01L21/311 , H01L21/66
CPC分类号： H01L21/32139 , H01L21/31116 , H01L21/31122 , H01L21/31138 , H01L21/3146 , H01L21/318
摘要： A method for fabricating a semiconductor device includes forming an etch target layer over a substrate that includes a cell region and a peripheral region. A first hard mask layer, a second hard mask layer, and an anti-reflective coating layer are formed over the etch target layer. A photosensitive pattern is formed over the anti-reflective coating layer. The anti-reflective coating layer is etched to have a width smaller than the width of the photosensitive pattern. The second hard mask layer is etched. A main etching and an over-etching are performed on the first hard mask layer. The etch target layer is then etched.
摘要翻译：一种制造半导体器件的方法包括在包括单元区域和周边区域的衬底上形成蚀刻目标层。第一硬掩模层，第二硬掩模层和抗反射涂层形成在蚀刻目标层上。在抗反射涂层上形成感光图案。抗反射涂层被蚀刻成具有比感光图案的宽度小的宽度。蚀刻第二硬掩模层。在第一硬掩模层上进行主蚀刻和过蚀刻。然后蚀刻目标层。

2. 发明授权

US06465321B1 Method of forming a storage node in a semiconductor device 失效
标题翻译：在半导体器件中形成存储节点的方法
公开(公告)号：US06465321B1
公开(公告)日：2002-10-15
申请号：US09722505
申请日：2000-11-28
申请人： Hyeon Sang Shin , Chang Heon Park , Myung Pil Kim
发明人： Hyeon Sang Shin , Chang Heon Park , Myung Pil Kim
IPC分类号： H01L2120
CPC分类号： H01L28/60 , H01L21/32139 , H01L28/55
摘要： There is disclosed a method of forming a storage node in a semiconductor device capable of forming a storage node in a vertical structure, by forming a hard mask used to form a noble storage node using a TiN film deposited in a spacer shape on an oxide film and over the oxide film.
摘要翻译：公开了一种在能够形成垂直结构的存储节点的半导体器件中形成存储节点的方法，通过使用在氧化膜上以间隔物形式沉积的TiN膜形成用于形成贵重存储节点的硬掩模并在氧化膜上方。

3. 发明授权

US09871045B2 Semiconductor device with damascene bit line and method for manufacturing the same 有权
公开(公告)号：US09871045B2
公开(公告)日：2018-01-16
申请号：US13334000
申请日：2011-12-21
申请人： Seung-Jin Yeom , Noh-Jung Kwak , Chang-Heon Park , Sun-Hwan Hwang
发明人： Seung-Jin Yeom , Noh-Jung Kwak , Chang-Heon Park , Sun-Hwan Hwang
IPC分类号： H01L21/768 , H01L27/108
CPC分类号： H01L27/10855 , H01L27/10885
摘要： A semiconductor device includes first conductive patterns adjacent to each other and isolated by a trench including first and second trenches, a second conductive pattern formed in the first trench, and an insulating pattern partially filling the second trench under the second conductive pattern and formed between the first conductive patterns and the second conductive pattern.

4. 发明授权

US07608546B2 Method for fabricating a semiconductor device 失效
标题翻译：半导体器件的制造方法
公开(公告)号：US07608546B2
公开(公告)日：2009-10-27
申请号：US11765673
申请日：2007-06-20
申请人： Sang-Soo Park , Chang-Heon Park , Dong-Ryeol Lee
发明人： Sang-Soo Park , Chang-Heon Park , Dong-Ryeol Lee
IPC分类号： H01L21/302 , H01L21/461
CPC分类号： H01L21/32139 , H01L21/31116 , H01L21/31122 , H01L21/31138 , H01L21/3146 , H01L21/318
摘要： A method for fabricating a semiconductor device includes forming an etch target layer over a substrate that includes a cell region and a peripheral region. A first hard mask layer, a second hard mask layer, and an anti-reflective coating layer are formed over the etch target layer. A photosensitive pattern is formed over the anti-reflective coating layer. The anti-reflective coating layer is etched to have a width smaller than the width of the photosensitive pattern. The second hard mask layer is etched. A main etching and an over-etching are performed on the first hard mask layer. The etch target layer is then etched.
摘要翻译：一种制造半导体器件的方法包括在包括单元区域和周边区域的衬底上形成蚀刻目标层。第一硬掩模层，第二硬掩模层和抗反射涂层形成在蚀刻目标层上。在抗反射涂层上形成感光图案。抗反射涂层被蚀刻成具有比感光图案的宽度小的宽度。蚀刻第二硬掩模层。在第一硬掩模层上进行主蚀刻和过蚀刻。然后蚀刻目标层。

5. 发明申请

US20090117748A1 METHOD FOR MANUFACTURING A PHASE CHANGE MEMORY DEVICE CAPABLE OF IMPROVING THERMAL EFFICIENCY OF PHASE CHANGE MATERIAL 审中-公开
标题翻译：制造可改善相变材料热效率的相变存储器件的方法
公开(公告)号：US20090117748A1
公开(公告)日：2009-05-07
申请号：US12146172
申请日：2008-06-25
申请人： Dong Ryeol LEE , Chang Heon PARK , Hee Seung SHIN
发明人： Dong Ryeol LEE , Chang Heon PARK , Hee Seung SHIN
IPC分类号： H01L21/306
CPC分类号： H01L45/1675 , H01L45/06 , H01L45/1233 , H01L45/144
摘要： A method for manufacturing a phase change memory device, capable of improving reset current characteristics of a phase change layer by preventing thermal loss of the phase change layer. An interlayer dielectric layer having a lower electrode contact is formed on a semiconductor substrate. A phase change layer and an upper electrode layer are sequentially formed on the interlayer dielectric layer. Then, an upper electrode and a phase change pattern are formed by etching predetermined portions of the upper electrode layer and the phase change layer using an etching gas having chlorine gas.
摘要翻译：一种相变存储器件的制造方法，其能够通过防止相变层的热损失来提高相变层的复位电流特性。在半导体衬底上形成具有下部电极接触的层间绝缘层。在层间电介质层上依次形成相变层和上电极层。然后，通过使用具有氯气的蚀刻气体蚀刻上电极层和相变层的预定部分来形成上电极和相变图案。

6. 发明申请

US20080182395A1 METHOD FOR FORMING PATTERN IN SEMICONDUCTOR DEVICE 审中-公开
标题翻译：在半导体器件中形成图案的方法
公开(公告)号：US20080182395A1
公开(公告)日：2008-07-31
申请号：US11967201
申请日：2007-12-30
申请人： Chang-Heon PARK , Dong-Ryeol Lee
发明人： Chang-Heon PARK , Dong-Ryeol Lee
IPC分类号： H01L21/283
CPC分类号： H01L29/4236 , H01L21/32137 , H01L21/823842 , H01L29/4916
摘要： A method for fabricating a dual polysilicon gate includes providing a substrate, forming a gate oxide layer over the substrate, forming a polysilicon layer over the gate oxide layer, patterning the polysilicon layer in a condition of applying a relatively low first pressure or a relatively high first bias power, thereby forming gate patterns and exposing a given portion of the gate oxide layer, and forming an oxide layer over the exposed given portion of the gate oxide layer by using a plasma oxidation process while performing an over-etch process on the gate patterns in a condition of applying a second pressure higher than the first pressure or a second bias power lower than the first bias power.
摘要翻译：制造双多晶硅栅极的方法包括提供衬底，在衬底上形成栅极氧化层，在栅极氧化物层上形成多晶硅层，在施加相对低的第一压力或相对高的条件下对多晶硅层进行构图从而形成栅极图案并暴露栅极氧化物层的给定部分，并且通过使用等离子体氧化工艺在栅极氧化层的暴露的给定部分上形成氧化物层，同时在栅极上执行过蚀刻工艺在施加比第一压力高的第二压力或低于第一偏压功率的第二偏压功率的条件下的图案。

7. 发明授权

US06589861B2 Method for fabricating a semiconductor device 失效
公开(公告)号：US06589861B2
公开(公告)日：2003-07-08
申请号：US10015672
申请日：2001-12-17
申请人： Chang Heon Park , Yun Seok Cho
发明人： Chang Heon Park , Yun Seok Cho
IPC分类号： H01L214763
CPC分类号： H01L21/7682
摘要： A method for fabricating a semiconductor device includes sequentially forming a stopping layer, an intermetal dielectric, and a capping layer on an interlayer dielectric, selectively removing the capping layer, the intermetal dielectric, and the stopping layer to partially expose a surface of the interlayer dielectric to form a hole, selectively removing a side of the intermetal dielectric within the hole, depositing a metal film on an entire surface including the hole to form an air gap in a portion where the side of the intermetal dielectric is removed, and planarizing an entire surface of the metal film to expose a surface of the capping layer to form a plurality of metal lines.

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