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1. 发明申请

US20110246955A1 METHOD, PROGRAM, AND APPARATUS FOR AIDING WIRING DESIGN 有权
标题翻译：用于辅助接线设计的方法，程序和装置
公开(公告)号：US20110246955A1
公开(公告)日：2011-10-06
申请号：US13075632
申请日：2011-03-30
申请人： Ikuo OHTSUKA , Eiichi Konno , Takahiko Orita , Yoshitaka Nishio , Toshiyasu Sakata
发明人： Ikuo OHTSUKA , Eiichi Konno , Takahiko Orita , Yoshitaka Nishio , Toshiyasu Sakata
IPC分类号： G06F17/50
CPC分类号： G06F17/5077
摘要： A wiring-design aiding method for causing a computer to execute generating paths for buses so that the buses do not cross each other with respect to a wiring area including at least one wiring layer, the paths being represented by corresponding graphics The computer further executes verifying, for each bus, whether wires for nets belonging to the bus are successfully extracted from a component to which the bus is connected; and recording, in the wiring area, graphics representing the nets belonging to a bus for which it is determined in the verification that all the nets belonging to the bus are successfully extracted. The bus-path generation is re-executed with respect to the bus for which it is determined in the verification that at least one of the nets is not successfully extracted.
摘要翻译：一种用于使计算机执行总线的产生路径的布线设计辅助方法，使得总线相对于包括至少一个布线层的布线区域彼此不相交，所述路径由相应的图形表示。计算机还对每个总线进一步验证是否从总线连接的部件成功提取属于总线的网线; 并且在布线区域中记录表示属于总线的网络的图形，在该验证中确定属于总线的所有网络被成功提取。相对于在验证中确定的总线，重新执行总线路径生成至少一个网络未成功提取。

2. 发明授权

US08930869B2 Method, program, and apparatus for aiding wiring design 有权
标题翻译：用于辅助接线设计的方法，程序和设备
公开(公告)号：US08930869B2
公开(公告)日：2015-01-06
申请号：US13075632
申请日：2011-03-30
申请人： Ikuo Ohtsuka , Eiichi Konno , Takahiko Orita , Yoshitaka Nishio , Toshiyasu Sakata
发明人： Ikuo Ohtsuka , Eiichi Konno , Takahiko Orita , Yoshitaka Nishio , Toshiyasu Sakata
IPC分类号： G06F17/50
CPC分类号： G06F17/5077
摘要： A wiring-design aiding method for causing a computer to execute generating paths for buses so that the buses do not cross each other with respect to a wiring area including at least one wiring layer, the paths being represented by corresponding graphics The computer further executes verifying, for each bus, whether wires for nets belonging to the bus are successfully extracted from a component to which the bus is connected; and recording, in the wiring area, graphics representing the nets belonging to a bus for which it is determined in the verification that all the nets belonging to the bus are successfully extracted. The bus-path generation is re-executed with respect to the bus for which it is determined in the verification that at least one of the nets is not successfully extracted.
摘要翻译：一种用于使计算机执行总线的产生路径的布线设计辅助方法，使得总线相对于包括至少一个布线层的布线区域彼此不相交，所述路径由相应的图形表示。计算机还对每个总线进一步验证是否从总线连接的部件成功提取属于总线的网线; 并且在布线区域中记录表示属于总线的网络的图形，在该验证中确定属于总线的所有网络被成功提取。相对于在验证中确定的总线，重新执行总线路径生成至少一个网络未成功提取。

3. 发明授权

US08402413B2 Wiring design apparatus and method 有权
标题翻译：接线设计装置及方法
公开(公告)号：US08402413B2
公开(公告)日：2013-03-19
申请号：US12721716
申请日：2010-03-11
申请人： Ikuo Ohtsuka , Takao Yamaguchi , Eiichi Konno , Toshiyasu Sakata , Takahiko Orita
发明人： Ikuo Ohtsuka , Takao Yamaguchi , Eiichi Konno , Toshiyasu Sakata , Takahiko Orita
IPC分类号： G06F17/50
CPC分类号： H05K3/0005 , G06F17/5077 , H05K2201/10734
摘要： A wiring design apparatus for designing a plurality of wiring lines of a printed circuit board including a plurality of connection posts arranged in a matrix, includes a processor, the processor providing an orthogonal grid including a plurality of rows and columns running over and between the connection posts, providing a plurality of diagonal paths each connecting at least one of the rows with at least one of the columns each running between each of adjacent pairs of the connection posts, and determining a route for each of the wiring lines by exclusively allocating to each of the wiring lines a selected part of the rows, the columns and the paths so that the selected part connects both ends of each of the wiring lines.
摘要翻译：一种用于设计包括以矩阵形式布置的多个连接柱的印刷电路板的多条布线的布线设计装置，包括处理器，所述处理器提供正交网格，所述正交网格包括在所述连接之间和之间运行的多个行和列柱，其提供多个对角线路径，每个对角线路径至少连接一条行，每条列中的至少一列在相邻的每对连接柱之间运行，并且通过专门地分配给每个布线来确定每个布线的路线的布线选定部分的列，列和路径，使得所选择的部分连接每条布线的两端。

4. 发明授权

US08307322B2 Wiring design apparatus 有权
标题翻译：接线设计设备
公开(公告)号：US08307322B2
公开(公告)日：2012-11-06
申请号：US12574071
申请日：2009-10-06
申请人： Eiichi Konno , Yoshitaka Nishio , Takao Yamaguchi , Toshiyasu Sakata , Takahiko Orita
发明人： Eiichi Konno , Yoshitaka Nishio , Takao Yamaguchi , Toshiyasu Sakata , Takahiko Orita
IPC分类号： G06F17/50
CPC分类号： G06F17/5077
摘要： A wiring design apparatus includes a first acquirer that acquires a first wiring block whose region has a maximum number of crossings with regions of other wiring blocks from printed circuit board data of a printed circuit board having a plurality of wiring blocks with a specific region on a wiring layer, a second acquirer that acquires second wiring blocks whose region does not cross the first wiring block from the printed circuit board data, and a wiring execution requester that causes a wiring processor to perform wiring processing on the first wiring block and the second wiring blocks in parallel.
摘要翻译：布线设计装置包括：第一获取器，其获取与具有特定区域的多个布线块的印刷电路板的印刷电路板数据的区域具有与其他布线块的区域最大交叉数的第一布线块，布线层，从印刷电路板数据获取区域不与第一布线块相交的第二布线块的第二获取器以及使布线处理器对第一布线块和第二布线进行布线处理的布线执行请求器块并行

5. 发明授权

US08286124B2 Printed circuit board design assisting method, printed circuit board design assisting device, and storage medium 有权
标题翻译：印刷电路板设计辅助方法，印刷电路板设计辅助装置和存储介质
公开(公告)号：US08286124B2
公开(公告)日：2012-10-09
申请号：US12819580
申请日：2010-06-21
申请人： Toshiyasu Sakata , Eiichi Konno , Takahiko Orita , Yoshitaka Nishio , Kazunori Kumagai
发明人： Toshiyasu Sakata , Eiichi Konno , Takahiko Orita , Yoshitaka Nishio , Kazunori Kumagai
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： A printed circuit board design assisting method, device and storage medium are provided. The assisting method includes referring to the position of terminals of a grid array package part, and attributes indicating whether each of the terminals is a power source terminal or a ground terminal, and selecting the power source terminals as a terminal to be researched, searching for a new connection path between the terminal which has been selected, and one of the ground terminals, by way of a first decoupling capacitor, determining whether there is duplication of paths between the new connection path and an connection path between the terminals connected by way of a second decoupling capacitor, changing the position of the second decoupling capacitor if duplication is detected, and re-searching a connection path between the terminals by way of the second decoupling capacitor, which is not in duplicate with the new connection path.
摘要翻译：提供印刷电路板设计辅助方法，装置和存储介质。辅助方法包括参考网格阵列封装部件的端子的位置以及指示每个端子是电源端子还是接地端子的属性，并且将电源端子选择为要研究的端子，搜索通过第一解耦电容器确定已经选择的终端与接地终端之一的新的连接路径，确定新连接路径和通过以下方式连接的终端之间的连接路径之间的连接路径是否重复第二去耦电容器，如果检测到复制，则改变第二去耦电容器的位置，并且通过与新连接路径不重复的第二去耦电容器重新搜索端子之间的连接路径。

6. 发明申请

US20100325594A1 PRINTED CIRCUIT BOARD DESIGN ASSISTING METHOD, PRINTED CIRCUIT BOARD DESIGN ASSISTING DEVICE, AND STORAGE MEDIUM 有权
标题翻译：印刷电路板设计辅助方法，印刷电路板设计辅助设备和存储介质
公开(公告)号：US20100325594A1
公开(公告)日：2010-12-23
申请号：US12819580
申请日：2010-06-21
申请人： Toshiyasu SAKATA , Eiichi Konno , Takahiko Orita , Yoshitaka Nishio , Kazunori Kumagai
发明人： Toshiyasu SAKATA , Eiichi Konno , Takahiko Orita , Yoshitaka Nishio , Kazunori Kumagai
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： A printed circuit board design assisting method, device and storage medium are provided. The assisting method includes referring to the position of terminals of a grid array package part, and attributes indicating whether each of the terminals is a power source terminal or a ground terminal, and selecting the power source terminals as a terminal to be researched, searching for a new connection path between the terminal which has been selected, and one of the ground terminals, by way of a first decoupling capacitor, determining whether there is duplication of paths between the new connection path and an connection path between the terminals connected by way of a second decoupling capacitor, changing the position of the second decoupling capacitor if duplication is detected, and re-searching a connection path between the terminals by way of the second decoupling capacitor, which is not in duplicate with the new connection path.
摘要翻译：提供印刷电路板设计辅助方法，装置和存储介质。辅助方法包括参考网格阵列封装部件的端子的位置以及指示每个端子是电源端子还是接地端子的属性，并且将电源端子选择为要研究的端子，搜索通过第一解耦电容器确定已经选择的终端与接地终端之一的新的连接路径，确定新连接路径和通过以下方式连接的终端之间的连接路径之间的连接路径是否重复第二去耦电容器，如果检测到复制，则改变第二去耦电容器的位置，并且通过与新连接路径不重复的第二去耦电容器重新搜索端子之间的连接路径。

7. 发明授权

US08402422B2 Wiring design device, method and recording medium 有权
标题翻译：接线设计装置，方法和记录介质
公开(公告)号：US08402422B2
公开(公告)日：2013-03-19
申请号：US13048687
申请日：2011-03-15
申请人： Toshiyasu Sakata , Eiichi Konno , Takahiko Orita , Kazunori Kumagai
发明人： Toshiyasu Sakata , Eiichi Konno , Takahiko Orita , Kazunori Kumagai
IPC分类号： G06F17/50
CPC分类号： G06F17/5077
摘要： A wiring design device to conduct wiring design on a printed wiring board that includes a plurality of conductive layers, the wiring design device including: noise contaminating part extracting means for extracting a part in a condition where noise contaminates a signal, the part being on a wiring-designed line, based on a route of the line and a physical condition around the route; route modification processing means for modifying the route of the line by moving the extracted part on the line in the condition where noise contaminates the signal to a position that avoids the condition where noise contaminates the signal; and line length adjusting means for conducting a line length adjustment on the line to compensate for a variation of the line length of the line when the variation of the line length of the line occurs due to modifying the route of the line.
摘要翻译：一种布线设计装置，用于在包括多个导电层的印刷线路板上进行布线设计，所述布线设计装置包括：噪声污染部分提取装置，用于在噪声污染信号的情况下提取部分，所述部分在基于线路的路线和路线周围的物理条件进行布线设计的线路; 路线修改处理装置，用于通过在噪声污染信号的情况下将提取的部分移动到行上来修改行的路线到避免噪声污染信号的状况的位置; 以及线长调整装置，用于当线路的线路长度的变化由于改变线路的路线而发生时，进行线路上的线路长度调整以补偿线路的线路长度的变化。

8. 发明申请

US20110231809A1 WIRING DESIGN DEVICE, METHOD AND RECORDING MEDIUM 有权
标题翻译：接线设计，方法和记录介质
公开(公告)号：US20110231809A1
公开(公告)日：2011-09-22
申请号：US13048687
申请日：2011-03-15
申请人： Toshiyasu Sakata , Eiichi Konno , Takahiko Orita , Kazunori Kumagai
发明人： Toshiyasu Sakata , Eiichi Konno , Takahiko Orita , Kazunori Kumagai
IPC分类号： G06F17/50
CPC分类号： G06F17/5077
摘要： A wiring design device to conduct wiring design on a printed wiring board that includes a plurality of conductive layers, the wiring design device including: noise contaminating part extracting means for extracting a part in a condition where noise contaminates a signal, the part being on a wiring-designed line, based on a route of the line and a physical condition around the route; route modification processing means for modifying the route of the line by moving the extracted part on the line in the condition where noise contaminates the signal to a position that avoids the condition where noise contaminates the signal; and line length adjusting means for conducting a line length adjustment on the line to compensate for a variation of the line length of the line when the variation of the line length of the line occurs due to modifying the route of the line.
摘要翻译：一种布线设计装置，用于在包括多个导电层的印刷线路板上进行布线设计，所述布线设计装置包括：噪声污染部分提取装置，用于在噪声污染信号的情况下提取部分，所述部分在基于线路的路线和路线周围的物理条件进行布线设计的线路; 路线修改处理装置，用于通过在噪声污染信号的情况下将提取的部分移动到行上来修改行的路线到避免噪声污染信号的状况的位置; 以及线长调整装置，用于当线路的线路长度的变化由于改变线路的路线而发生时，进行线路上的线路长度调整以补偿线路的线路长度的变化。

9. 发明授权

US08484600B2 Apparatus, design method and recording medium 有权
标题翻译：仪器，设计方法和记录介质
公开(公告)号：US08484600B2
公开(公告)日：2013-07-09
申请号：US13221572
申请日：2011-08-30
申请人： Yoshitaka Nishio , Eiichi Konno , Kazunori Kumagai , Motoyuki Tanisho , Toshiyasu Sakata
发明人： Yoshitaka Nishio , Eiichi Konno , Kazunori Kumagai , Motoyuki Tanisho , Toshiyasu Sakata
IPC分类号： G06F17/50
CPC分类号： G06F17/5077
摘要： A computer-readable medium storing a design program causing a computer to execute a process is provided. The process includes virtually routing, when routing of a wire to be connected between a first component and a second component at least one of which includes a swapping pin is being designed, the wire to be connected between a first pin of the first component and a first counterpart pin of the second component such that implementation of an actual routed wire connected therebetween is secured regardless of a net allocated to the swapping pin, and swapping one of the virtually routed first pin and the virtually routed first counterpart pin with the swapping pin such that the net allocated to the swapping pin is identical to a net allocated to the other one of the virtually routed first pin and the virtually routed first counterpart pin.
摘要翻译：提供了存储使计算机执行处理的设计程序的计算机可读介质。该过程包括虚拟地布线，当布线要被连接在第一部件和第二部件之间的导线时，其中至少其中之一包括交换引脚正被设计，待连接在第一部件的第一引脚与第一部件之间的导线第二组件的第一对应销，使得连接在其间的实际布线的实现被确保，而不管分配给交换引脚的网络如何，并且与交换引脚交换虚拟路由的第一引脚和虚拟路由的第一对应引脚中的一个，分配给交换引脚的网与分配给虚拟路由的第一引脚和虚拟路由的第一对应引脚中的另一个的网相同。

10. 发明申请

US20120117529A1 APPARATUS, DESIGN METHOD AND RECORDING MEDIUM 有权
标题翻译：设备，设计方法和记录介质
公开(公告)号：US20120117529A1
公开(公告)日：2012-05-10
申请号：US13221572
申请日：2011-08-30
申请人： Yoshitaka Nishio , Eiichi Konno , Kazunori Kumagai , Motoyuki Tanisho , Toshiyasu Sakata
发明人： Yoshitaka Nishio , Eiichi Konno , Kazunori Kumagai , Motoyuki Tanisho , Toshiyasu Sakata
IPC分类号： G06F17/50
CPC分类号： G06F17/5077
摘要： A computer-readable medium storing a design program causing a computer to execute a process is provided. The process includes virtually routing, when routing of a wire to be connected between a first component and a second component at least one of which includes a swapping pin is being designed, the wire to be connected between a first pin of the first component and a first counterpart pin of the second component such that implementation of an actual routed wire connected therebetween is secured regardless of a net allocated to the swapping pin, and swapping one of the virtually routed first pin and the virtually routed first counterpart pin with the swapping pin such that the net allocated to the swapping pin is identical to a net allocated to the other one of the virtually routed first pin and the virtually routed first counterpart pin.
摘要翻译：提供了存储使计算机执行处理的设计程序的计算机可读介质。该过程包括虚拟地布线，当布线要被连接在第一部件和第二部件之间的导线时，其中至少其中之一包括交换引脚正被设计，待连接在第一部件的第一引脚与第一部件之间的导线第二组件的第一对应销，使得连接在其间的实际布线的实现被确保，而不管分配给交换引脚的网络如何，并且与交换引脚交换虚拟路由的第一引脚和虚拟路由的第一对应引脚中的一个，分配给交换引脚的网与分配给虚拟路由的第一引脚和虚拟路由的第一对应引脚中的另一个的网相同。

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