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1. 发明授权

US08832630B2 Apparatus and method for aiding in designing electronic circuits 有权
标题翻译：有助于设计电子电路的装置和方法
公开(公告)号：US08832630B2
公开(公告)日：2014-09-09
申请号：US13555245
申请日：2012-07-23
申请人： Ikuo Ohtsuka , Toshiyasu Sakata
发明人： Ikuo Ohtsuka , Toshiyasu Sakata
IPC分类号： G06F17/50 , H05K3/00
CPC分类号： G06F17/5077 , G06F17/5072 , G06F2217/40 , H05K3/0005
摘要： First and second pin groups are each formed from a plurality of pins associated with specific nets. Pins in the first pin group are to be wired to pins in the second pin group according to their associated nets. A candidate selection unit selects a set of pair candidates each specifying a first pair of pins in the first pin group and a second pair of pins in the second pin group. The first and second pairs of pins are associated with the same pair of nets, and their respective distances are within a specified range. A pair determination unit determines which pins in the first and second pin groups are to be wired in pairs, based on the pair candidates selected by the candidate selection unit.
摘要翻译：第一和第二引脚组各自由与特定网络相关联的多个引脚形成。第一个引脚组中的引脚将根据其相关的网络连接到第二个引脚组中的引脚。候选选择单元选择一组配对候选，每组候选对象指定第一引脚组中的第一对引脚和第二引脚组中的第二对引脚。第一和第二对引脚与同一对网络相关联，并且它们各自的距离在指定范围内。对决定单元基于由候选选择单元选择的配对候选，确定第一和第二引脚组中哪些引脚成对布线。

2. 发明授权

US08423948B2 Wiring design support device and wiring design supporting method 有权
标题翻译：接线设计支持装置及接线设计配套方法
公开(公告)号：US08423948B2
公开(公告)日：2013-04-16
申请号：US13418470
申请日：2012-03-13
申请人： Kazunori Kumagai , Toshiyasu Sakata , Eiichi Konno
发明人： Kazunori Kumagai , Toshiyasu Sakata , Eiichi Konno
IPC分类号： G06F17/50
CPC分类号： G06F17/5077 , G06F17/509
摘要： A device includes a definition unit which defines a directional graph having a grid point as a node and a line connecting adjacent grid points as a branch, a generation unit which sets a branch connecting a grid pointing a wiring prohibited area in the branches of the directional graph to the capacity of “0”, and which sets another branch to the capacity of “1”, and which connects the starting point or the end point to each grid point of the wiring terminal indicated by wiring information, thereby generating a flow network, a search unit which searches the flow network for a path of a flow having the maximum amount of flow from the starting point to the end point, and a determination unit which determines a wiring path connecting the grid point indicated by the wiring information according to the search result of the path.
摘要翻译：一种设备包括定义单元，其定义具有网格点作为节点的方向图和连接相邻网格点作为分支的线;生成单元，其设置连接指向所述方向的分支中的布线禁止区域的网格的分支图示为0的容量，并且将另一分支设置为1的容量，并且将起始点或终点连接到由布线信息指示的接线端子的每个网格点，从而生成流网络，搜索单元其在流网络中搜索具有从起始点到终点的最大流量的路径，以及确定单元，其确定根据接线信息指示的网格点的布线路径，根据搜索结果路径。

3. 发明申请

US20130031525A1 APPARATUS AND METHOD FOR AIDING IN DESIGNING ELECTRONIC CIRCUITS 有权
标题翻译：用于设计电子电路的装置和方法
公开(公告)号：US20130031525A1
公开(公告)日：2013-01-31
申请号：US13555245
申请日：2012-07-23
申请人： Ikuo OHTSUKA , Toshiyasu SAKATA
发明人： Ikuo OHTSUKA , Toshiyasu SAKATA
IPC分类号： G06F17/50
CPC分类号： G06F17/5077 , G06F17/5072 , G06F2217/40 , H05K3/0005
摘要： First and second pin groups are each formed from a plurality of pins associated with specific nets. Pins in the first pin group are to be wired to pins in the second pin group according to their associated nets. A candidate selection unit selects a set of pair candidates each specifying a first pair of pins in the first pin group and a second pair of pins in the second pin group. The first and second pairs of pins are associated with the same pair of nets, and their respective distances are within a specified range. A pair determination unit determines which pins in the first and second pin groups are to be wired in pairs, based on the pair candidates selected by the candidate selection unit.
摘要翻译：第一和第二引脚组各自由与特定网络相关联的多个引脚形成。第一个引脚组中的引脚将根据其相关的网络连接到第二个引脚组中的引脚。候选选择单元选择一组配对候选，每组候选对象指定第一引脚组中的第一对引脚和第二引脚组中的第二对引脚。第一和第二对引脚与同一对网络相关联，并且它们各自的距离在指定范围内。对决定单元基于由候选选择单元选择的配对候选，确定第一和第二引脚组中哪些引脚成对布线。

4. 发明授权

US08286124B2 Printed circuit board design assisting method, printed circuit board design assisting device, and storage medium 有权
标题翻译：印刷电路板设计辅助方法，印刷电路板设计辅助装置和存储介质
公开(公告)号：US08286124B2
公开(公告)日：2012-10-09
申请号：US12819580
申请日：2010-06-21
申请人： Toshiyasu Sakata , Eiichi Konno , Takahiko Orita , Yoshitaka Nishio , Kazunori Kumagai
发明人： Toshiyasu Sakata , Eiichi Konno , Takahiko Orita , Yoshitaka Nishio , Kazunori Kumagai
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： A printed circuit board design assisting method, device and storage medium are provided. The assisting method includes referring to the position of terminals of a grid array package part, and attributes indicating whether each of the terminals is a power source terminal or a ground terminal, and selecting the power source terminals as a terminal to be researched, searching for a new connection path between the terminal which has been selected, and one of the ground terminals, by way of a first decoupling capacitor, determining whether there is duplication of paths between the new connection path and an connection path between the terminals connected by way of a second decoupling capacitor, changing the position of the second decoupling capacitor if duplication is detected, and re-searching a connection path between the terminals by way of the second decoupling capacitor, which is not in duplicate with the new connection path.
摘要翻译：提供印刷电路板设计辅助方法，装置和存储介质。辅助方法包括参考网格阵列封装部件的端子的位置以及指示每个端子是电源端子还是接地端子的属性，并且将电源端子选择为要研究的端子，搜索通过第一解耦电容器确定已经选择的终端与接地终端之一的新的连接路径，确定新连接路径和通过以下方式连接的终端之间的连接路径之间的连接路径是否重复第二去耦电容器，如果检测到复制，则改变第二去耦电容器的位置，并且通过与新连接路径不重复的第二去耦电容器重新搜索端子之间的连接路径。

5. 发明申请

US20120240094A1 WIRING DESIGN SUPPORT DEVICE AND WIRING DESIGN SUPPORTING METHOD 有权
标题翻译：接线设计支持设备和接线设计支持方法
公开(公告)号：US20120240094A1
公开(公告)日：2012-09-20
申请号：US13418470
申请日：2012-03-13
申请人： Kazunori KUMAGAI , Toshiyasu Sakata , Eiichi Konno
发明人： Kazunori KUMAGAI , Toshiyasu Sakata , Eiichi Konno
IPC分类号： G06F17/50
CPC分类号： G06F17/5077 , G06F17/509
摘要： A device includes a definition unit which defines a directional graph having a grid point as a node and a line connecting adjacent grid points as a branch, a generation unit which sets a branch connecting a grid pointing a wiring prohibited area in the branches of the directional graph to the capacity of “0”, and which sets another branch to the capacity of “1”, and which connects the starting point or the end point to each grid point of the wiring terminal indicated by wiring information, thereby generating a flow network, a search unit which searches the flow network for a path of a flow having the maximum amount of flow from the starting point to the end point, and a determination unit which determines a wiring path connecting the grid point indicated by the wiring information according to the search result of the path.
摘要翻译：一种设备包括定义单元，其定义具有网格点作为节点的方向图和连接相邻网格点作为分支的线;生成单元，其设置连接指向所述方向的分支中的布线禁止区域的网格的分支以“0”的容量图表示，并将另一个分支设置为“1”的容量，并且将起始点或终点连接到由布线信息指示的接线端子的每个网格点，从而生成流网络搜索单元，其搜索流网络具有从起始点到终点的最大流量的路径，以及确定单元，确定连接由布线信息指示的网格点的布线路径，根据路径的搜索结果。

6. 发明申请

US20110231809A1 WIRING DESIGN DEVICE, METHOD AND RECORDING MEDIUM 有权
标题翻译：接线设计，方法和记录介质
公开(公告)号：US20110231809A1
公开(公告)日：2011-09-22
申请号：US13048687
申请日：2011-03-15
申请人： Toshiyasu Sakata , Eiichi Konno , Takahiko Orita , Kazunori Kumagai
发明人： Toshiyasu Sakata , Eiichi Konno , Takahiko Orita , Kazunori Kumagai
IPC分类号： G06F17/50
CPC分类号： G06F17/5077
摘要： A wiring design device to conduct wiring design on a printed wiring board that includes a plurality of conductive layers, the wiring design device including: noise contaminating part extracting means for extracting a part in a condition where noise contaminates a signal, the part being on a wiring-designed line, based on a route of the line and a physical condition around the route; route modification processing means for modifying the route of the line by moving the extracted part on the line in the condition where noise contaminates the signal to a position that avoids the condition where noise contaminates the signal; and line length adjusting means for conducting a line length adjustment on the line to compensate for a variation of the line length of the line when the variation of the line length of the line occurs due to modifying the route of the line.
摘要翻译：一种布线设计装置，用于在包括多个导电层的印刷线路板上进行布线设计，所述布线设计装置包括：噪声污染部分提取装置，用于在噪声污染信号的情况下提取部分，所述部分在基于线路的路线和路线周围的物理条件进行布线设计的线路; 路线修改处理装置，用于通过在噪声污染信号的情况下将提取的部分移动到行上来修改行的路线到避免噪声污染信号的状况的位置; 以及线长调整装置，用于当线路的线路长度的变化由于改变线路的路线而发生时，进行线路上的线路长度调整以补偿线路的线路长度的变化。

7. 发明申请

US20100325594A1 PRINTED CIRCUIT BOARD DESIGN ASSISTING METHOD, PRINTED CIRCUIT BOARD DESIGN ASSISTING DEVICE, AND STORAGE MEDIUM 有权
标题翻译：印刷电路板设计辅助方法，印刷电路板设计辅助设备和存储介质
公开(公告)号：US20100325594A1
公开(公告)日：2010-12-23
申请号：US12819580
申请日：2010-06-21
申请人： Toshiyasu SAKATA , Eiichi Konno , Takahiko Orita , Yoshitaka Nishio , Kazunori Kumagai
发明人： Toshiyasu SAKATA , Eiichi Konno , Takahiko Orita , Yoshitaka Nishio , Kazunori Kumagai
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： A printed circuit board design assisting method, device and storage medium are provided. The assisting method includes referring to the position of terminals of a grid array package part, and attributes indicating whether each of the terminals is a power source terminal or a ground terminal, and selecting the power source terminals as a terminal to be researched, searching for a new connection path between the terminal which has been selected, and one of the ground terminals, by way of a first decoupling capacitor, determining whether there is duplication of paths between the new connection path and an connection path between the terminals connected by way of a second decoupling capacitor, changing the position of the second decoupling capacitor if duplication is detected, and re-searching a connection path between the terminals by way of the second decoupling capacitor, which is not in duplicate with the new connection path.
摘要翻译：提供印刷电路板设计辅助方法，装置和存储介质。辅助方法包括参考网格阵列封装部件的端子的位置以及指示每个端子是电源端子还是接地端子的属性，并且将电源端子选择为要研究的端子，搜索通过第一解耦电容器确定已经选择的终端与接地终端之一的新的连接路径，确定新连接路径和通过以下方式连接的终端之间的连接路径之间的连接路径是否重复第二去耦电容器，如果检测到复制，则改变第二去耦电容器的位置，并且通过与新连接路径不重复的第二去耦电容器重新搜索端子之间的连接路径。

8. 发明申请

US20100235804A1 WIRING DESIGN APPARATUS AND METHOD 有权
标题翻译：接线设计和方法
公开(公告)号：US20100235804A1
公开(公告)日：2010-09-16
申请号：US12721716
申请日：2010-03-11
申请人： Ikuo OHTSUKA , Takao YAMAGUCHI , Eiichi KONNO , Toshiyasu SAKATA , Takahiko ORITA
发明人： Ikuo OHTSUKA , Takao YAMAGUCHI , Eiichi KONNO , Toshiyasu SAKATA , Takahiko ORITA
IPC分类号： G06F17/50
CPC分类号： H05K3/0005 , G06F17/5077 , H05K2201/10734
摘要： A wiring design apparatus for designing a plurality of wiring lines of a printed circuit board including a plurality of connection posts arranged in a matrix, includes a processor, the processor providing an orthogonal grid including a plurality of rows and columns running over and between the connection posts, providing a plurality of diagonal paths each connecting at least one of the rows with at least one of the columns each running between each of adjacent pairs of the connection posts, and determining a route for each of the wiring lines by exclusively allocating to each of the wiring lines a selected part of the rows, the columns and the paths so that the selected part connects both ends of each of the wiring lines.
摘要翻译：一种用于设计包括以矩阵形式布置的多个连接柱的印刷电路板的多条布线的布线设计装置，包括处理器，所述处理器提供正交网格，所述正交网格包括在所述连接之间和之间运行的多个行和列柱，其提供多个对角线路径，每个对角线路径至少连接一条行，每条列中的至少一列在相邻的每对连接柱之间运行，并且通过专门地分配给每个布线来确定每个布线的路线的布线选定部分的列，列和路径，使得所选择的部分连接每条布线的两端。

9. 发明授权

US08484840B2 Leading wiring method, leading wiring program, and leading wiring apparatus 有权
标题翻译：领先的布线方式，导线接线方案和导线接线装置
公开(公告)号：US08484840B2
公开(公告)日：2013-07-16
申请号：US12659697
申请日：2010-03-17
申请人： Toshiyasu Sakata , Eiichi Konno
发明人： Toshiyasu Sakata , Eiichi Konno
IPC分类号： H01R43/00 , H05K13/00
CPC分类号： H05K1/0231 , G06F17/5077 , H05K3/0005 , H05K2201/10545 , H05K2201/10734 , Y10T29/49004 , Y10T29/49128 , Y10T29/4913 , Y10T29/49147 , Y10T29/49155 , Y10T29/49165 , Y10T29/49169
摘要： When a formed position of a via formed on a board is the same as a position of a footprint of a chip component located on the back surface of the board corresponding to an area on which a BGA is mounted, a board designing apparatus determines that the chip component and the BGA can be connected using chip on hole. When it is determined that the chip component and the BGA can be connected, the board designing apparatus carries out chip on hole by forming a via in an area of the board on which the BGA is mounted, the via leading to the footprint of the chip component located on the back surface of the board.
摘要翻译：当在板上形成的通孔的形成位置与位于板的背面上的与安装有BGA的区域相对应的芯片部件的覆盖区的位置相同时，板设计装置确定芯片组件和BGA可以使用芯片上的孔连接。当确定芯片组件和BGA可以连接时，板设计设备通过在其上安装有BGA的板的区域中形成通孔来执行芯片上的通孔，通孔导致芯片的占用面积组件位于板的背面。

10. 发明申请

US20100170083A1 Leading wiring method, leading wiring program, and leading wiring apparatus 有权
标题翻译：领先的布线方式，导线接线方案和导线接线装置
公开(公告)号：US20100170083A1
公开(公告)日：2010-07-08
申请号：US12659697
申请日：2010-03-17
申请人： Toshiyasu Sakata , Eiichi Konno
发明人： Toshiyasu Sakata , Eiichi Konno
IPC分类号： G01R31/28 , G06F17/50
CPC分类号： H05K1/0231 , G06F17/5077 , H05K3/0005 , H05K2201/10545 , H05K2201/10734 , Y10T29/49004 , Y10T29/49128 , Y10T29/4913 , Y10T29/49147 , Y10T29/49155 , Y10T29/49165 , Y10T29/49169
摘要： When a formed position of a via formed on a board is the same as a position of a footprint of a chip component located on the back surface of the board corresponding to an area on which a BGA is mounted, a board designing apparatus determines that the chip component and the BGA can be connected using chip on hole. When it is determined that the chip component and the BGA can be connected, the board designing apparatus carries out chip on hole by forming a via in an area of the board on which the BGA is mounted, the via leading to the footprint of the chip component located on the back surface of the board.
摘要翻译：当在板上形成的通孔的形成位置与位于板的背面上的与安装有BGA的区域相对应的芯片部件的覆盖区的位置相同时，板设计装置确定芯片组件和BGA可以使用芯片上的孔连接。当确定芯片组件和BGA可以连接时，板设计设备通过在其上安装有BGA的板的区域中形成通孔来执行芯片上的通孔，通孔导致芯片的占用面积组件位于板的背面。

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