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1. 发明授权

US08244987B2 Memory access device including multiple processors 有权
标题翻译：内存访问设备包括多个处理器
公开(公告)号：US08244987B2
公开(公告)日：2012-08-14
申请号：US12629721
申请日：2009-12-02
申请人： Ik Jae Chun , Tae Moon Roh , Jongdae Kim
发明人： Ik Jae Chun , Tae Moon Roh , Jongdae Kim
IPC分类号： G06F12/00
CPC分类号： G06F13/4234
摘要： Provided is a memory access device including multiple processors accessing a specific memory. The memory access device includes first and second processors, first and second transaction controllers, a memory access switch, and a memory controller. The first and second transaction controllers are connected respectively to the first and second processors. The memory access switch is connected to the first and second transaction controllers. The memory controller is connected to the memory access switch to control a memory device. Herein, if the first and second processors simultaneously access the memory device, the second processor stores an address or data in the second transaction controller while the first processor is accessing the memory device.
摘要翻译：提供了包括访问特定存储器的多个处理器的存储器访问设备。存储器访问设备包括第一和第二处理器，第一和第二事务控制器，存储器访问开关和存储器控制器。第一和第二事务控制器分别连接到第一和第二处理器。存储器访问开关连接到第一和第二事务控制器。存储器控制器连接到存储器访问开关以控制存储器件。这里，如果第一处理器和第二处理器同时访问存储器件，则第二处理器在第一处理器访问存储器件时将地址或数据存储在第二事务控制器中。

2. 发明申请

US20100146219A1 MEMORY ACCESS DEVICE INCLUDING MULTIPLE PROCESSORS 有权
标题翻译：包括多个处理器的存储器访问设备
公开(公告)号：US20100146219A1
公开(公告)日：2010-06-10
申请号：US12629721
申请日：2009-12-02
申请人： Ik Jae Chun , Tae Moon Roh , Jongdae Kim
发明人： Ik Jae Chun , Tae Moon Roh , Jongdae Kim
IPC分类号： G06F12/08
CPC分类号： G06F13/4234
摘要： Provided is a memory access device including multiple processors accessing a specific memory. The memory access device includes first and second processors, first and second transaction controllers, a memory access switch, and a memory controller. The first and second transaction controllers are connected respectively to the first and second processors. The memory access switch is connected to the first and second transaction controllers. The memory controller is connected to the memory access switch to control a memory device. Herein, if the first and second processors simultaneously access the memory device, the second processor stores an address or data in the second transaction controller while the first processor is accessing the memory device. Accordingly, the memory access device enables multiple processors, which are to simultaneously access a specific memory, to perform other operations during the standby time taken to access the specific memory.
摘要翻译：提供了包括访问特定存储器的多个处理器的存储器访问设备。存储器访问设备包括第一和第二处理器，第一和第二事务控制器，存储器访问开关和存储器控制器。第一和第二事务控制器分别连接到第一和第二处理器。存储器访问开关连接到第一和第二事务控制器。存储器控制器连接到存储器访问开关以控制存储器件。这里，如果第一处理器和第二处理器同时访问存储器件，则第二处理器在第一处理器访问存储器件时将地址或数据存储在第二事务控制器中。因此，存储器访问装置使得能够同时访问特定存储器的多个处理器在访问特定存储器的待机时间期间执行其他操作。

3. 发明授权

US09275304B2 Feature vector classification device and method thereof 有权
标题翻译：特征向量分类装置及其方法
公开(公告)号：US09275304B2
公开(公告)日：2016-03-01
申请号：US13494906
申请日：2012-06-12
申请人： Sanghun Yoon , Chun-Gi Lyuh , Ik Jae Chun , Jung Hee Suk , Tae Moon Roh
发明人： Sanghun Yoon , Chun-Gi Lyuh , Ik Jae Chun , Jung Hee Suk , Tae Moon Roh
IPC分类号： G06K9/62 , G06N99/00
CPC分类号： G06K9/6228 , G06K9/6269 , G06N99/005
摘要： Disclosed is a feature vector classification device which includes an initial condition setting unit; a variable calculating unit configured to receive a training vector and to calculate an error and a weight according to setting of the initial condition setting unit; a loop deciding unit configured to determine whether re-calculation is required, based on a comparison result between the calculated error and an error threshold; and a hyperplane generating unit configured to generate a hyperplane when an end signal is received from the loop deciding unit.
摘要翻译：公开了一种特征矢量分类装置，其包括初始状态设定单元，可变计算单元，被配置为接收训练向量，并且根据初始条件设置单元的设置来计算误差和权重; 基于计算出的误差和误差阈值之间的比较结果，确定是否需要重新计算的循环判定单元; 以及超平面生成单元，被配置为当从所述循环判定单元接收到结束信号时，生成超平面。

4. 发明申请

US20120076408A1 METHOD AND SYSTEM FOR DETECTING OBJECT 有权
标题翻译：检测对象的方法和系统
公开(公告)号：US20120076408A1
公开(公告)日：2012-03-29
申请号：US12949438
申请日：2010-11-18
申请人： Jung Hee SUK , Chun Gi Lyuh , Ik Jae Chun , Jeong Hwan Lee , Jae Chang Shim , Mi Soon Choi , Wook Jin Chung , Yeung Hak LEE , Tae Moon Roh
发明人： Jung Hee SUK , Chun Gi Lyuh , Ik Jae Chun , Jeong Hwan Lee , Jae Chang Shim , Mi Soon Choi , Wook Jin Chung , Yeung Hak LEE , Tae Moon Roh
IPC分类号： G06K9/34
CPC分类号： G06K9/3241 , G06K9/4642 , G06K9/6256
摘要： Provided are a system and method for detecting an object. The method includes selecting a macroscopic scan mode in which there are a small number of divided regions or a microscopic scan mode in which there are a large number of divided regions according to complexity of a background including an object to be detected, dividing an input image into one or more regions according to the selected scan mode, merging adjacent regions having similar characteristics among the divided regions, extracting a search region by excluding a region having a high probability that the object to be detected does not exist from the divided or merged regions, extracting feature data including a feature vector for detecting the object in the search region, and detecting the object in the search region using the extracted feature data.
摘要翻译：提供了用于检测对象的系统和方法。该方法包括选择宏数据扫描模式，其中存在少量分割区域或微观扫描模式，其中根据包括要检测的对象的背景的复杂度存在大量分割区域，划分输入图像根据所选择的扫描模式进入一个或多个区域，在分割区域中合并具有相似特征的相邻区域，通过从分割或合并区域排除具有高可能性的待检测对象不存在的区域来提取搜索区域提取包括用于检测搜索区域中的对象的特征向量的特征数据，以及使用所提取的特征数据来检测搜索区域中的对象。

5. 发明申请

US20110153878A1 MEMORY SYSTEM AND INTEGRATED MANAGEMENT METHOD FOR PLURALITY OF DMA CHANNELS 有权
标题翻译：用于DMA通道多重的存储系统和集成管理方法
公开(公告)号：US20110153878A1
公开(公告)日：2011-06-23
申请号：US12882141
申请日：2010-09-14
申请人： Ik Jae CHUN , Chun Gi Lyuh , Se Wan Heo , Sang Hun Yoon , Tae Moon Roh , Jong Kee Kwon , Jong Dae Kim
发明人： Ik Jae CHUN , Chun Gi Lyuh , Se Wan Heo , Sang Hun Yoon , Tae Moon Roh , Jong Kee Kwon , Jong Dae Kim
IPC分类号： G06F13/28
CPC分类号： G06F13/28
摘要： Provided are a memory system and an integrated management method for a plurality of direct memory access (DMA) channels. The memory system includes a memory controller exchanging data with a memory and having a plurality of channels physically separated from each other, and a DMA controller having a plurality of DMA channels physically separated from each other and in contact with the plurality of channels of the memory controller, and exchanging data with the memory via the plurality of DMA channels and the memory controller.
摘要翻译：提供了用于多个直接存储器访问（DMA）通道的存储器系统和集成管理方法。存储器系统包括存储器控制器，其与存储器交换数据并且具有物理上彼此分离的多个通道;以及DMA控制器，其具有彼此物理上彼此分离并与存储器的多个通道接触的多个DMA通道控制器，并且经由多个DMA通道和存储器控制器与存储器交换数据。

6. 发明授权

US07576582B2 Low-power clock gating circuit 有权
标题翻译：低功耗时钟门控电路
公开(公告)号：US07576582B2
公开(公告)日：2009-08-18
申请号：US11945387
申请日：2007-11-27
申请人： Dae Woo Lee , Yil Suk Yang , Ik Jae Chun , Chun Gi Lyuh , Tae Moon Roh , Jong Dae Kim
发明人： Dae Woo Lee , Yil Suk Yang , Ik Jae Chun , Chun Gi Lyuh , Tae Moon Roh , Jong Dae Kim
IPC分类号： H03K3/289
CPC分类号： H03K3/0375
摘要： Provided is a low-power clock gating circuit using a Multi-Threshold CMOS (MTCMOS) technique. The low-power clock gating circuit includes a latch circuit of an input stage and an AND gate circuit of an output stage, in which power consumption caused by leakage current in the clock gating circuit is reduced in a sleep mode, and supply of a clock to a unused device of a targeted logic circuit is prevented by the control of a clock enable signal in an active mode, thereby reducing power consumption. The low-power clock gating circuit using an MTCMOS technique uses devices having a low threshold voltage and devices having a high threshold voltage, which makes it possible to implement a high-speed, low-power circuit, unlike a conventional clock gating circuit using a single threshold voltage.
摘要翻译：提供了使用多阈值CMOS（MTCMOS）技术的低功率时钟选通电路。低功率时钟选通电路包括输入级的锁存电路和输出级的与门电路，其中由休眠模式中的时钟门控电路中的漏电流引起的功耗降低，并且提供时钟通过控制活动模式中的时钟使能信号来防止目标逻辑电路的未使用的装置，从而降低功耗。使用MTCMOS技术的低功率时钟选通电路使用具有低阈值电压的器件和具有高阈值电压的器件，这使得可以实现高速，低功率电路，这与使用单阈值电压。

7. 发明授权

US08755624B2 Image registration device and method thereof 有权
标题翻译：图像配准装置及其方法
公开(公告)号：US08755624B2
公开(公告)日：2014-06-17
申请号：US13585726
申请日：2012-08-14
申请人： Jung Hee Suk , Sanghun Yoon , Chun-Gi Lyuh , Ik Jae Chun , Tae Moon Roh
发明人： Jung Hee Suk , Sanghun Yoon , Chun-Gi Lyuh , Ik Jae Chun , Tae Moon Roh
IPC分类号： G06K9/40
CPC分类号： G06T3/0068
摘要： Disclosed is an image registration device which includes an image input unit which receives an image; an image information generating unit which generates a homography matrix from the input image; and a warping unit which registers an image based on the homography matrix. The registration information generating unit comprises a distance information generator which generates distance information on subjects of the input image; a distance information modeler which approximates the generated distance information; an overlap information generator which generates overlap information from the approximated distance information; a matching pair determiner which determines a matching pair from the overlap information; and a homography matrix generator which generates a homography matrix from the matching pair.
摘要翻译：公开了一种图像注册装置，其包括接收图像的图像输入单元; 图像信息生成单元，其从输入图像生成单应性矩阵; 以及基于单应性矩阵来登记图像的翘曲单元。所述登记信息生成部包括距离信息生成部，其生成与所述输入图像对象相对应的距离信息; 距离信息建模器近似所生成的距离信息; 重叠信息生成器，其从所述近似距离信息生成重叠信息; 匹配对确定器，其从所述重叠信息确定匹配对; 以及从匹配对生成单应性矩阵的单应性矩阵生成器。

8. 发明授权

US08520893B2 Method and system for detecting object 有权
标题翻译：检测物体的方法和系统
公开(公告)号：US08520893B2
公开(公告)日：2013-08-27
申请号：US12949438
申请日：2010-11-18
申请人： Jung Hee Suk , Chun Gi Lyuh , Ik Jae Chun , Jeong Hwan Lee , Jae Chang Shim , Mi Soon Choi , Wook Jin Chung , Yeung Hak Lee , Tae Moon Roh
发明人： Jung Hee Suk , Chun Gi Lyuh , Ik Jae Chun , Jeong Hwan Lee , Jae Chang Shim , Mi Soon Choi , Wook Jin Chung , Yeung Hak Lee , Tae Moon Roh
IPC分类号： G06K9/00 , H04N7/12
CPC分类号： G06K9/3241 , G06K9/4642 , G06K9/6256
摘要： Provided are a system and method for detecting an object. The method includes selecting a macroscopic scan mode in which there are a small number of divided regions or a microscopic scan mode in which there are a large number of divided regions according to complexity of a background including an object to be detected, dividing an input image into one or more regions according to the selected scan mode, merging adjacent regions having similar characteristics among the divided regions, extracting a search region by excluding a region having a high probability that the object to be detected does not exist from the divided or merged regions, extracting feature data including a feature vector for detecting the object in the search region, and detecting the object in the search region using the extracted feature data.
摘要翻译：提供了用于检测对象的系统和方法。该方法包括选择宏数据扫描模式，其中存在少量分割区域或微观扫描模式，其中根据包括要检测的对象的背景的复杂度存在大量分割区域，划分输入图像根据所选择的扫描模式进入一个或多个区域，在分割区域中合并具有相似特征的相邻区域，通过从分割或合并区域排除具有高可能性的待检测对象不存在的区域来提取搜索区域提取包括用于检测搜索区域中的对象的特征向量的特征数据，以及使用所提取的特征数据来检测搜索区域中的对象。

9. 发明申请

US20120159015A1 DIRECT MEMORY ACCESS CONTROLLER AND OPERATING METHOD THEREOF 有权
标题翻译：直接存储器访问控制器及其操作方法
公开(公告)号：US20120159015A1
公开(公告)日：2012-06-21
申请号：US13243470
申请日：2011-09-23
申请人： Ik Jae Chun , Chun-Gi Lyuh , Jung Hee Suk , Sanghun Yoon , Tae Moon Roh
发明人： Ik Jae Chun , Chun-Gi Lyuh , Jung Hee Suk , Sanghun Yoon , Tae Moon Roh
IPC分类号： G06F13/28
CPC分类号： G06F13/28
摘要： Disclosed is an operating method of a direct memory access (DMA) controller having first and second DMA channels. The operating method includes iteratively performing a DMA transfer operation of the first DMA channel based upon loop information and transfer information of the first DMA channel; iteratively performing a DMA transfer operation of the second DMA channel based upon loop information and transfer information of the second DMA channel; reconfiguring the transfer and loop information of the first and second DMA channels; and again performing the iteratively performing a DMA transfer operation of the first DMA channel and the iteratively performing a DMA transfer operation of the first DMA channel based upon the reconfigured transfer and loop information of the first and second DMA channels.
摘要翻译：公开了具有第一和第二DMA通道的直接存储器访问（DMA）控制器的操作方法。操作方法包括：基于第一DMA通道的循环信息和传送信息来迭代地执行第一DMA通道的DMA传送操作; 基于所述第二DMA通道的循环信息和传送信息迭代地执行所述第二DMA通道的DMA传送操作; 重新配置第一和第二DMA通道的传送和循环信息; 并且基于第一和第二DMA通道的重新配置的传输和循环信息，再次执行迭代地执行第一DMA通道的DMA传送操作和迭代地执行第一DMA通道的DMA传送操作。

10. 发明申请

US20120148164A1 IMAGE MATCHING DEVICES AND IMAGE MATCHING METHODS THEREOF 有权
标题翻译：图像匹配装置及其图像匹配方法
公开(公告)号：US20120148164A1
公开(公告)日：2012-06-14
申请号：US13211912
申请日：2011-08-17
申请人： Jung Hee SUK , Sanghun Yoon , Chun-Gi Lyuh , Ik Jae Chun , Tae Moon Roh
发明人： Jung Hee SUK , Sanghun Yoon , Chun-Gi Lyuh , Ik Jae Chun , Tae Moon Roh
IPC分类号： G06K9/64 , G06K9/46
CPC分类号： G06K9/46 , G06K9/4671 , G06K9/6206 , G06K9/64
摘要： Provided is an image matching method of matching at least two images. The image matching method extracts feature points of a reference image and feature points of a target image, changes a feature point, selected from among the feature points of the reference image, to a reference point in the target image, sets a matching candidate region on the basis of the reference point, in the target image, and performs a similarity operation between the selected feature point in the reference image and a plurality of feature points included in the matching candidate region among the feature points of the target image. The image matching method decreases the number of similarity operations performed in the image matching operation, thereby guaranteeing a high-speed operation.
摘要翻译：提供了一种匹配至少两个图像的图像匹配方法。图像匹配方法提取参考图像的特征点和目标图像的特征点，将从参考图像的特征点中选择的特征点改变为目标图像中的参考点，将匹配的候选区域设置在在目标图像中的参考点的基础，并且执行参考图像中的所选特征点与目标图像的特征点中的匹配候选区域中包括的多个特征点之间的相似度操作。图像匹配方法减少了在图像匹配操作中执行的相似度操作的数量，从而保证了高速操作。

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