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1. 发明申请

US20120226831A1 MEMORY SYSTEM AND INTEGRATED MANAGEMENT METHOD FOR PLURALITY OF DMA CHANNELS 审中-公开
标题翻译：用于DMA通道多重的存储系统和集成管理方法
公开(公告)号：US20120226831A1
公开(公告)日：2012-09-06
申请号：US13471236
申请日：2012-05-14
申请人： Ik Jae CHUN , Chun Gi Lyuh , Se Wan Heo , Sang Hun Yoon , Tae Moon Roh , Jong Kee Kwon , Jong Dae Kim
发明人： Ik Jae CHUN , Chun Gi Lyuh , Se Wan Heo , Sang Hun Yoon , Tae Moon Roh , Jong Kee Kwon , Jong Dae Kim
IPC分类号： G06F13/28
CPC分类号： G06F13/28
摘要： Provided are a memory system and an integrated management method for a plurality of direct memory access (DMA) channels. The memory system includes a memory controller exchanging data with a memory and having a plurality of channels physically separated from each other, and a DMA controller having a plurality of DMA channels physically separated from each other and in contact with the plurality of channels of the memory controller, and exchanging data with the memory via the plurality of DMA channels and the memory controller.
摘要翻译：提供了用于多个直接存储器访问（DMA）通道的存储器系统和集成管理方法。存储器系统包括存储器控制器，其与存储器交换数据并且具有物理上彼此分离的多个通道;以及DMA控制器，其具有彼此物理上彼此分离并与存储器的多个通道接触的多个DMA通道控制器，并且经由多个DMA通道和存储器控制器与存储器交换数据。

2. 发明授权

US08205021B2 Memory system and integrated management method for plurality of DMA channels 有权
标题翻译：用于多个DMA通道的存储系统和集成管理方法
公开(公告)号：US08205021B2
公开(公告)日：2012-06-19
申请号：US12882141
申请日：2010-09-14
申请人： Ik Jae Chun , Chun Gi Lyuh , Se Wan Heo , Sang Hun Yoon , Tae Moon Roh , Jong Kee Kwon , Jong Dae Kim
发明人： Ik Jae Chun , Chun Gi Lyuh , Se Wan Heo , Sang Hun Yoon , Tae Moon Roh , Jong Kee Kwon , Jong Dae Kim
IPC分类号： G06F13/28
CPC分类号： G06F13/28
摘要： Provided are a memory system and an integrated management method for a plurality of direct memory access (DMA) channels. The memory system includes a memory controller exchanging data with a memory and having a plurality of channels physically separated from each other, and a DMA controller having a plurality of DMA channels physically separated from each other and in contact with the plurality of channels of the memory controller, and exchanging data with the memory via the plurality of DMA channels and the memory controller.
摘要翻译：提供了用于多个直接存储器访问（DMA）通道的存储器系统和集成管理方法。存储器系统包括存储器控制器，其与存储器交换数据并且具有物理上彼此分离的多个通道;以及DMA控制器，其具有彼此物理上彼此分离并与存储器的多个通道接触的多个DMA通道控制器，并且经由多个DMA通道和存储器控制器与存储器交换数据。

3. 发明申请

US20110153878A1 MEMORY SYSTEM AND INTEGRATED MANAGEMENT METHOD FOR PLURALITY OF DMA CHANNELS 有权
标题翻译：用于DMA通道多重的存储系统和集成管理方法
公开(公告)号：US20110153878A1
公开(公告)日：2011-06-23
申请号：US12882141
申请日：2010-09-14
申请人： Ik Jae CHUN , Chun Gi Lyuh , Se Wan Heo , Sang Hun Yoon , Tae Moon Roh , Jong Kee Kwon , Jong Dae Kim
发明人： Ik Jae CHUN , Chun Gi Lyuh , Se Wan Heo , Sang Hun Yoon , Tae Moon Roh , Jong Kee Kwon , Jong Dae Kim
IPC分类号： G06F13/28
CPC分类号： G06F13/28
摘要： Provided are a memory system and an integrated management method for a plurality of direct memory access (DMA) channels. The memory system includes a memory controller exchanging data with a memory and having a plurality of channels physically separated from each other, and a DMA controller having a plurality of DMA channels physically separated from each other and in contact with the plurality of channels of the memory controller, and exchanging data with the memory via the plurality of DMA channels and the memory controller.
摘要翻译：提供了用于多个直接存储器访问（DMA）通道的存储器系统和集成管理方法。存储器系统包括存储器控制器，其与存储器交换数据并且具有物理上彼此分离的多个通道;以及DMA控制器，其具有彼此物理上彼此分离并与存储器的多个通道接触的多个DMA通道控制器，并且经由多个DMA通道和存储器控制器与存储器交换数据。

4. 发明申请

US20110145549A1 PIPELINED DECODING APPARATUS AND METHOD BASED ON PARALLEL PROCESSING 审中-公开
标题翻译：基于并行处理的管道解码设备和方法
公开(公告)号：US20110145549A1
公开(公告)日：2011-06-16
申请号：US12862565
申请日：2010-08-24
申请人： Jung Hee SUK , Chun Gi Lyuh , Ik Jae Chun , Se Wan Heo , Soon II Yeo , Tae Moon Roh , Jong Kee Kwon , Jong Dae Kim
发明人： Jung Hee SUK , Chun Gi Lyuh , Ik Jae Chun , Se Wan Heo , Soon II Yeo , Tae Moon Roh , Jong Kee Kwon , Jong Dae Kim
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： H04N19/436 , H04N19/44
摘要： An apparatus and method for decoding moving images based on parallel processing are provided. The apparatus for decoding images based on parallel processing can improve operational performance by pipelining massive-data transmission between processors while performing context-adaptive variable length decoding (CAVLD), inverse quantization (IQ), inverse transformation (IT), motion compensation (MC), intra prediction (IP) and deblocking filter (DF) operations in parallel in units of pluralities of macroblocks (MBs).
摘要翻译：提供了一种基于并行处理来解码运动图像的装置和方法。用于基于并行处理的图像解码装置可以通过在执行上下文自适应可变长度解码（CAVLD），逆量化（IQ），逆变换（IT），运动补偿（MC））之间流水线处理大规模数据传输来提高操作性能，，帧内预测（IP）和去块滤波器（DF）操作以多个宏块（MB）为单位并行。

5. 发明申请

US20110142345A1 APPARATUS AND METHOD FOR RECOGNIZING IMAGE 审中-公开
标题翻译：用于识别图像的装置和方法
公开(公告)号：US20110142345A1
公开(公告)日：2011-06-16
申请号：US12783180
申请日：2010-05-19
申请人： Sang Hun Yoon , Ik Jae Chun , Chun Gi Lyuh , Jung Hee Suk , Tae Moon Roh , Jong Kee Kwon , Jong Dae Kim
发明人： Sang Hun Yoon , Ik Jae Chun , Chun Gi Lyuh , Jung Hee Suk , Tae Moon Roh , Jong Kee Kwon , Jong Dae Kim
IPC分类号： G06K9/46
CPC分类号： G06K9/4614
摘要： Provided are an apparatus and method for recognizing an image. In the apparatus and method for recognizing an image, various features can be extracted by a Haar-like filter using 1st to nth order gradients of the x- and y-axis of an input image, and the input image is correctly classified as a true or false image using, in stages, the extracted features of the input image, multiple threshold values for a true image and multiple threshold values for a false image. Accordingly, the apparatus and method achieve a high recognition rate by performing a small amount of computation. Consequently, it is possible to rapidly and correctly recognize an image, enabling real-time image recognition.
摘要翻译：提供了一种用于识别图像的装置和方法。在用于识别图像的装置和方法中，可以通过输入图像的x轴和y轴的第1至n阶梯度的Haar样滤波器提取各种特征，并且输入图像被正确地分类为真或分别使用输入图像的提取特征，用于真实图像的多个阈值和用于假图像的多个阈值的假图像。因此，该装置和方法通过执行少量的计算来实现高识别率。因此，可以快速且正确地识别图像，从而实现图像识别。

6. 发明申请

US20110022767A1 DMA CONTROLLER WITH INTERRUPT CONTROL PROCESSOR 审中-公开
标题翻译：具有中断控制处理器的DMA控制器
公开(公告)号：US20110022767A1
公开(公告)日：2011-01-27
申请号：US12843801
申请日：2010-07-26
申请人： Ik Jae CHUN , Chun Gi Lyuh , Jung Hee Suk , Tae Moon Roh , Jong Kee Kwon , Jong Dae Kim
发明人： Ik Jae CHUN , Chun Gi Lyuh , Jung Hee Suk , Tae Moon Roh , Jong Kee Kwon , Jong Dae Kim
IPC分类号： G06F13/28 , G06F13/24
CPC分类号： G06F13/32
摘要： Provided is a direct memory access (DMA) controller having an interrupt control processor that can process DMA transmission-related interrupts according to a control program modifiable by a user. The DMA controller includes the interrupt control processor that can process a DMA transmission-related interrupt and a DMA request interrupt transmitted from peripheral devices and control the DMA channel through the control program that can be modified by the user, so that DMA channel control and relevant interrupt processing loads caused by a plurality of DMA data transmissions are reduced, and the flexibility of DMA channel control and interrupt processing in control of the DMA controller is provided to the user.
摘要翻译：提供了具有中断控制处理器的直接存储器访问（DMA）控制器，其可以根据用户可修改的控制程序来处理与DMA传输相关的中断。 DMA控制器包括可处理DMA传输相关中断的中断控制处理器和从外围设备发送的DMA请求中断，并通过可由用户修改的控制程序控制DMA通道，从而使DMA通道控制和相关减少由多个DMA数据传输引起的中断处理负载，并且向用户提供DMA控制的DMA通道控制和中断处理的灵活性。

7. 发明授权

US08407276B2 Apparatus for calculating absolute difference 有权
标题翻译：用于计算绝对差的装置
公开(公告)号：US08407276B2
公开(公告)日：2013-03-26
申请号：US12843550
申请日：2010-07-26
申请人： Chun Gi Lyuh , Ik Jae Chun , Jung Hee Suk , Tae Moon Roh , Jong Kee Kwon , Jong Dae Kim
发明人： Chun Gi Lyuh , Ik Jae Chun , Jung Hee Suk , Tae Moon Roh , Jong Kee Kwon , Jong Dae Kim
IPC分类号： G06F7/50
CPC分类号： G06F7/544
摘要： Provided is an apparatus for calculating an absolute difference capable of efficiently performing an absolute difference using an adder. The apparatus for calculating an absolute difference includes a comparator comparing values of two integers, first and second selectors each selecting and outputting one of the two integers according to the comparison results of the comparator, an inverter complementing the result value selected by the second selector; and an adder adding up the result value selected by the first selector, the value complemented by the inverter, and 1.
摘要翻译：提供了一种用于计算能够使用加法器有效地执行绝对差的绝对差的装置。用于计算绝对差的装置包括比较器，比较器比较两个整数的值，第一和第二选择器，每个选择器根据比较器的比较结果选择和输出两个整数中的一个;逆变器，补偿由第二选择器选择的结果值; 和加法器将由第一选择器选择的结果值相加，由逆变器补充的值，以及1。

8. 发明授权

US07769981B2 Row of floating point accumulators coupled to respective PEs in uppermost row of PE array for performing addition operation 有权
标题翻译：耦合到PE阵列的最上排中的相应PE的浮点累加器的行，用于执行附加操作
公开(公告)号：US07769981B2
公开(公告)日：2010-08-03
申请号：US12045844
申请日：2008-03-11
申请人： Chun Gi Lyuh , Yil Suk Yang , Se Wan Heo , Soon Il Yeo , Tae Moon Roh , Jong Dae Kim , Ki Chul Kim , Se Hoon Yoo
发明人： Chun Gi Lyuh , Yil Suk Yang , Se Wan Heo , Soon Il Yeo , Tae Moon Roh , Jong Dae Kim , Ki Chul Kim , Se Hoon Yoo
IPC分类号： G06F15/80
CPC分类号： G06F15/8007
摘要： Provided is a parallel processor for supporting a floating-point operation. The parallel processor has a flexible structure for easy development of a parallel algorithm involving multimedia computing, requires low hardware cost, and consumes low power. To support floating-point operations, the parallel processor uses floating-point accumulators and a flag for floating-point multiplication. Using the parallel processor, it is possible to process a geometric transformation operation in a 3-dimensional (3D) graphics process at low cost. Also, the cost of a bus width for instructions can be minimized by a partitioned Single-Instruction Multiple-Data (SIMD) method and a method of conditionally executing instructions.
摘要翻译：提供了一种用于支持浮点运算的并行处理器。并行处理器具有灵活的结构，便于开发涉及多媒体计算的并行算法，需要较低的硬件成本，并且消耗低功耗。为了支持浮点运算，并行处理器使用浮点累加器和浮点乘法的标志。使用并行处理器，可以以低成本在三维（3D）图形处理中处理几何变换操作。此外，可以通过分区单指令多数据（SIMD）方法和有条件执行指令的方法来最小化用于指令的总线宽度的成本。

9. 发明授权

US08731059B2 Apparatus and method for calculating sum of absolute differences for motion estimation of variable block 有权
标题翻译：用于计算可变块运动估计的绝对差和的装置和方法
公开(公告)号：US08731059B2
公开(公告)日：2014-05-20
申请号：US12105745
申请日：2008-04-18
申请人： Yil Suk Yang , Jung Hee Suk , Chun Gi Lyuh , Ik Jae Chun , Tae Moon Roh , Jong Dae Kim , Ki Chul Kim , Jung Hoon Kim
发明人： Yil Suk Yang , Jung Hee Suk , Chun Gi Lyuh , Ik Jae Chun , Tae Moon Roh , Jong Dae Kim , Ki Chul Kim , Jung Hoon Kim
IPC分类号： H04N7/12 , H04N11/02 , H04N11/04 , H04N7/26 , H04N7/50 , H04N7/36
CPC分类号： H04N19/00521 , H04N19/102 , H04N19/122 , H04N19/134 , H04N19/436 , H04N19/57 , H04N19/61 , H04N19/86
摘要： An apparatus that calculates a Sum of Absolute Differences (SAD) for motion estimation of a variable block capable of parallelly calculating SAD values with respect to multiple current frame macroblocks at a time is presented. The apparatus includes a PE array unit including at least one Processing Element (PE) that is aligned in the form of a matrix, and parallelly calculating a SAD value of at least one pixel provided in multiple serial current frame macroblocks, a local memory including current frame macroblock data, reference frame macroblock data, and reference frame search area data, and transmitting the data to each PE that is provided in the PE array unit, and a controller for making a command for the data that are provided in the local memory to be transmitted corresponding to at least one pixel, on which each PE provided in the PE array unit performs calculation.
摘要翻译：提出了一种计算能够相对于多个当前帧宏块同时计算SAD值的可变块的运动估计的绝对差（SAD）的装置。该装置包括PE阵列单元，该PE阵列单元包括以矩阵的形式排列的至少一个处理元件（PE），并且并行地计算在多个串行当前帧宏块中提供的至少一个像素的SAD值，包括电流帧宏块数据，参考帧宏块数据和参考帧搜索区域数据，并且将数据发送到在PE阵列单元中提供的每个PE，以及用于对提供在本地存储器中的数据进行命令的控制器对应于至少一个像素，其中PE阵列单元中提供的每个PE执行计算。

10. 发明授权

US07576582B2 Low-power clock gating circuit 有权
标题翻译：低功耗时钟门控电路
公开(公告)号：US07576582B2
公开(公告)日：2009-08-18
申请号：US11945387
申请日：2007-11-27
申请人： Dae Woo Lee , Yil Suk Yang , Ik Jae Chun , Chun Gi Lyuh , Tae Moon Roh , Jong Dae Kim
发明人： Dae Woo Lee , Yil Suk Yang , Ik Jae Chun , Chun Gi Lyuh , Tae Moon Roh , Jong Dae Kim
IPC分类号： H03K3/289
CPC分类号： H03K3/0375
摘要： Provided is a low-power clock gating circuit using a Multi-Threshold CMOS (MTCMOS) technique. The low-power clock gating circuit includes a latch circuit of an input stage and an AND gate circuit of an output stage, in which power consumption caused by leakage current in the clock gating circuit is reduced in a sleep mode, and supply of a clock to a unused device of a targeted logic circuit is prevented by the control of a clock enable signal in an active mode, thereby reducing power consumption. The low-power clock gating circuit using an MTCMOS technique uses devices having a low threshold voltage and devices having a high threshold voltage, which makes it possible to implement a high-speed, low-power circuit, unlike a conventional clock gating circuit using a single threshold voltage.
摘要翻译：提供了使用多阈值CMOS（MTCMOS）技术的低功率时钟选通电路。低功率时钟选通电路包括输入级的锁存电路和输出级的与门电路，其中由休眠模式中的时钟门控电路中的漏电流引起的功耗降低，并且提供时钟通过控制活动模式中的时钟使能信号来防止目标逻辑电路的未使用的装置，从而降低功耗。使用MTCMOS技术的低功率时钟选通电路使用具有低阈值电压的器件和具有高阈值电压的器件，这使得可以实现高速，低功率电路，这与使用单阈值电压。

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