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1. 发明申请

US20130031447A1 FAST DETECTION OF CONVERGENCE OR DIVERGENCE IN ITERATIVE DECODING 失效
标题翻译：快速检测迭代解码中的合并或多样性
公开(公告)号：US20130031447A1
公开(公告)日：2013-01-31
申请号：US13194952
申请日：2011-07-31
申请人： Eran SHARON , Idan ALROD , Ariel NAVON , Omer FAINZILBER , Simon LITSYN
发明人： Eran SHARON , Idan ALROD , Ariel NAVON , Omer FAINZILBER , Simon LITSYN
IPC分类号： H03M13/15 , G06F11/10
CPC分类号： H03M13/1128
摘要： A termination indication is computed during an iteration of an iterative decoding of a representation of a codeword according to a schedule. The termination indication is tested to see if the decoding has converged or is not likely to converge. The testing of the termination indication shows convergence or lack of likelihood thereof even if a codeword bit estimate was flipped during an immediately preceding traversal of the schedule. Preferably, the termination indication includes an error correction syndrome weight, a zero value whereof indicates convergence, and the computing of the termination indication includes, in response to the flipping of a codeword bit estimate, flipping the error correction syndrome bits that are influenced by that codeword bit estimate.
摘要翻译：在根据时间表对码字的表示的迭代解码的迭代期间计算终止指示。测试终止指示以查看解码是否收敛或不可能收敛。终止指示的测试显示出收敛或缺乏可能性，即使在紧接着的日程表遍历期间翻转了码字比特估计。优选地，终止指示包括纠错综合征权重，其值指示收敛的零值，并且终止指示的计算响应于码字比特估计的翻转而包括翻转受该比特估计影响的纠错综合征比特码字比特估计。

2. 发明申请

US20090319868A1 READING A FLASH MEMORY BY JOINT DECODING AND CELL VOLTAGE DISTRIBUTION TRACKING 有权
标题翻译：通过联机解码和电池电压分配跟踪读取闪存
公开(公告)号：US20090319868A1
公开(公告)日：2009-12-24
申请号：US12407098
申请日：2009-03-19
申请人： Eran SHARON , Idan ALROD , Simon LITSYN
发明人： Eran SHARON , Idan ALROD , Simon LITSYN
IPC分类号： H03M13/05 , G06F12/02 , G06F11/10
CPC分类号： G11C16/26 , G06F11/1068 , G11C11/5642
摘要： To read a plurality of memory cells, each cell is assigned to a respective cell population. A respective value of an operational parameter of each cell is measured. Each cell is assigned an a-priori metric based at least in part on one or more CVD parameter values of the cell's population. The a-priori metrics are decoded. Based at least in part on the resulting a-posteriori metrics, the CVD parameter values are corrected, without repeating the measurements of the cell operational parameter values. The operational parameter values are indicative of bit patterns stored in the cells, and the correction of the CVD parameter values is constrained by requiring the bit patterns collectively to be a valid codeword.
摘要翻译：为了读取多个存储单元，将每个单元分配给相应的单元群。测量每个单元的操作参数的相应值。至少部分地基于单元格群体的一个或多个CVD参数值，为每个单元分配先验度量。先验先验度量被解码。至少部分地基于得到的后验度量，校正CVD参数值，而不重复单元操作参数值的测量。操作参数值表示存储在单元中的位模式，并且通过要求位图集合成为有效代码字来限制CVD参数值的校正。

3. 发明申请

US20090319858A1 REDUCED COMPLEXITY LDPC DECODER 有权
标题翻译：降低复杂LDPC解码器
公开(公告)号：US20090319858A1
公开(公告)日：2009-12-24
申请号：US12404308
申请日：2009-03-15
申请人： Eran SHARON , Simon Litsyn , Idan Alrod
发明人： Eran SHARON , Simon Litsyn , Idan Alrod
IPC分类号： H03M13/05 , G06F11/10
CPC分类号： H03M13/1131 , H03M13/1114 , H03M13/6505 , H03M13/6588
摘要： To decode a manifestation of a codeword in which K information bits are encoded as N>K codeword bits, messages are exchanged between N bit nodes and N−K check nodes. During computation, messages are expressed with a full message length greater than two bits. In each iteration, representations of at least some of the exchanged messages are stored. For at least one node, if representations of messages sent from that node are stored, then the representation of one or more of the messages is stored using at least two bits but using fewer bits than the full message length, and the representation of one other message is stored with full message length. Preferably, the messages that are stored using fewer bits than the full message length are messages sent from check nodes.
摘要翻译：为了解码其中K个信息比特被编码为N> K个码字比特的码字的表现，在N个比特节点和N-K个校验节点之间交换消息。在计算期间，消息以大于两位的完整消息长度表示。在每次迭代中，存储至少一些交换的消息的表示。对于至少一个节点，如果存储了从该节点发送的消息的表示，则使用至少两个比特来存储一个或多个消息的表示，但是使用比全消息长度少的比特，并且另一个的表示消息以完整的消息长度存储。优选地，使用比完整消息长度少的位来存储的消息是从校验节点发送的消息。

4. 发明申请

US20100169737A1 METHOD AND DEVICE FOR MULTI PHASE ERROR-CORRECTION 有权
标题翻译：用于多相位错误校正的方法和装置
公开(公告)号：US20100169737A1
公开(公告)日：2010-07-01
申请号：US12648313
申请日：2009-12-29
申请人： Simon LITSYN , Eran SHARON , Idan ALROD , Menahem LASSER
发明人： Simon LITSYN , Eran SHARON , Idan ALROD , Menahem LASSER
IPC分类号： H03M13/11 , G06F11/10
CPC分类号： H03M13/2927 , G06F11/1068 , H03M13/1111 , H03M13/152 , H03M13/1545 , H03M13/2903 , H03M13/2906 , H03M13/3715 , H03M13/6362
摘要： Data bits to be encoded are split into a plurality of subgroups. Each subgroup is encoded separately to generate a corresponding codeword. Selected subsets are removed from the corresponding codewords, leaving behind shortened codewords, and are many-to-one transformed to condensed bits. The final codeword is a combination of the shortened codewords and the condensed bits. A representation of the final codeword is decoded by being partitioned to a selected subset and a plurality of remaining subsets. Each remaining subset is decoded separately. If one of the decodings fails, the remaining subset whose decoding failed is decoded at least in part according to the selected subset. If the encoding and decoding are systematic then the selected subsets are of parity bits.
摘要翻译：要编码的数据位被分割成多个子组。每个子组被分别编码以产生相应的码字。所选择的子集从相应的码字中移除，留下缩短的码字，并且被多对一地转换成浓缩比特。最终码字是缩短的码字和浓缩比特的组合。通过划分为所选择的子集和多个剩余子集来对最终码字的表示进行解码。每个剩余子集被单独解码。如果解码之一失败，则解码失败的剩余子集至少部分地根据所选择的子集进行解码。如果编码和解码是系统的，则所选择的子集是奇偶校验位。

5. 发明申请

US20110276856A1 METHOD AND DEVICE FOR MULTI PHASE ERROR-CORRECTION 有权
标题翻译：用于多相位错误校正的方法和装置
公开(公告)号：US20110276856A1
公开(公告)日：2011-11-10
申请号：US13170193
申请日：2011-06-28
申请人： Simon LITSYN , Eran SHARON , Idan ALROD , Menahem LASSER
发明人： Simon LITSYN , Eran SHARON , Idan ALROD , Menahem LASSER
IPC分类号： H03M13/05 , G06F11/10
CPC分类号： H03M13/2927 , G06F11/1068 , H03M13/1111 , H03M13/152 , H03M13/1545 , H03M13/2903 , H03M13/2906 , H03M13/3715 , H03M13/6362
摘要： Data bits to be encoded are split into a plurality of subgroups. Each subgroup is encoded separately to generate a corresponding codeword. Selected subsets are removed from the corresponding codewords, leaving behind shortened codewords, and are many-to-one transformed to condensed bits. The final codeword is a combination of the shortened codewords and the condensed bits. A representation of the final codeword is decoded by being partitioned to a selected subset and a plurality of remaining subsets. Each remaining subset is decoded separately. If one of the decodings fails, the remaining subset whose decoding failed is decoded at least in part according to the selected subset. If the encoding and decoding are systematic then the selected subsets are of parity bits.
摘要翻译：要编码的数据位被分割成多个子组。每个子组被分别编码以产生相应的码字。所选择的子集从相应的码字中移除，留下缩短的码字，并且被多对一地转换成浓缩比特。最终码字是缩短的码字和浓缩比特的组合。最终码字的表示被分割成选定的子集和多个剩余子集。每个剩余子集被单独解码。如果解码失败之一，则解码失败的剩余子集至少部分地根据所选子集进行解码。如果编码和解码是系统的，则所选择的子集是奇偶校验位。

6. 发明申请

US20110276749A1 MULTI-BIT-PER-CELL FLASH MEMORY DEVICE WITH NON-BIJECTIVE MAPPING 有权
公开(公告)号：US20110276749A1
公开(公告)日：2011-11-10
申请号：US13175859
申请日：2011-07-03
申请人： Simon LITSYN , Eran SHARON , Idan ALROD
发明人： Simon LITSYN , Eran SHARON , Idan ALROD
IPC分类号： G06F12/02
CPC分类号： G11C16/10 , G06F11/1072 , G11C7/1006 , G11C11/56 , G11C11/5628 , G11C16/0483 , G11C16/34 , G11C29/42 , G11C2211/5641
摘要： To store a plurality of input bits, the bits are mapped to a corresponding programmed state of one or more memory cells and the cell(s) is/are programmed to that corresponding programmed state. The mapping may be many-to-one or may be an “into” generalized Gray mapping. The cell(s) is/are read to provide a read state value that is transformed into a plurality of output bits, for example by maximum likelihood decoding or by mapping the read state value into a plurality of soft bits and then decoding the soft bits.

7. 发明申请

US20100192042A1 READING A FLASH MEMORY BY CONSTRAINED DECODING 有权
标题翻译：通过约束解码读取闪存
公开(公告)号：US20100192042A1
公开(公告)日：2010-07-29
申请号：US12645499
申请日：2009-12-23
申请人： Eran SHARON , Idan ALROD , Simon LITSYN
发明人： Eran SHARON , Idan ALROD , Simon LITSYN
IPC分类号： H03M13/05 , G06F11/10
CPC分类号： G11C16/26 , G06F11/1068 , G11C11/5642 , G11C29/00
摘要： To read memory cells that have been programmed to store an ECC codeword, with each cell storing a respective plurality of bits of the codeword, a respective value of an operational parameter such as a threshold voltage of each cell is measured. Each bit is assigned a respective metric, such as a LLR estimate of the bit, based at least in part on the respective value of the operational parameter of the bit's cell. The metrics are decoded with reference both to the ECC and to mutual constraints of the metrics within each cell that are independent of the ECC.
摘要翻译：为了读取已编程为存储ECC码字的存储器单元，其中每个单元存储码字的相应多个位，测量诸如每个单元的阈值电压的操作参数的相应值。至少部分地基于比特的小区的操作参数的相应值，为比特分配各个度量，例如比特的LLR估计。参考ECC和与独立于ECC的每个单元内的度量的相互约束来对度量进行解码。

8. 发明申请

US20110258370A1 MULTIPLE PROGRAMMING OF FLASH MEMORY WITHOUT ERASE 有权
标题翻译：无擦除的闪存存储器的多个编程
公开(公告)号：US20110258370A1
公开(公告)日：2011-10-20
申请号：US13086408
申请日：2011-04-14
申请人： Eran SHARON , Idan Alrod , Simon Litsyn , Ishai Ilani
发明人： Eran SHARON , Idan Alrod , Simon Litsyn , Ishai Ilani
IPC分类号： G06F12/02
CPC分类号： G11C16/102 , G06F12/02 , G11C11/5628 , G11C16/349
摘要： To store, successively, in a plurality of memory cells, first and second pluralities of input bits that are equal in number, a first transformation transforms the first input bits into a first plurality of transformed bits. A first portion of the cells is programmed to store the first transformed bits according to a mapping of bit sequences to cell levels, but, if the first transformation has a variable output length, only if there are few enough first transformed bits to fit in the first cell portion. Then, without erasing a second cell portion that includes the first portion, if respective levels of the cells of the second portion, that represent a second plurality of transformed bits obtained by a second transformation of the second input bits, according to the mapping, are accessible from the current cell levels, the second portion is so programmed to store the second transformed bits.
摘要翻译：为了顺次地在多个存储单元中存储数量相等的第一和第二多个输入位，第一变换将第一输入位变换为第一多个变换位。单元的第一部分被编程为根据位序列到单元级别的映射来存储第一变换的位，但是如果第一变换具有可变的输出长度，则只有当足够少的第一变换位适合于第一细胞部分。然后，在不擦除包括第一部分的第二单元部分的情况下，如果根据映射通过第二输入位的第二变换获得的表示第二多个变换位的第二部分的单元的各个级别是从当前单元级可访问，第二部分被编程为存储第二转换位。

9. 发明申请

US20110022922A1 COMPACT DECODING OF PUNCTURED BLOCK CODES 有权
标题翻译：冲击块编码的紧凑解码
公开(公告)号：US20110022922A1
公开(公告)日：2011-01-27
申请号：US12506342
申请日：2009-07-21
申请人： Eran SHARON , Idan ALROD , Simon LITSYN
发明人： Eran SHARON , Idan ALROD , Simon LITSYN
IPC分类号： H03M13/05 , G06F11/10
CPC分类号： H03M13/6362 , G06F11/1068 , H03M13/1111 , H03M13/15 , H03M13/152
摘要： k input bits are encoded according to a code with which is associated a m×n=m+k parity check matrix H. The resulting codeword is punctured, with n′
摘要翻译： k个输入位根据与m×n = m + k个奇偶校验矩阵H相关联的代码进行编码。所得码字被打孔，n'

10. 发明申请

US20110022921A1 COMPACT DECODING OF PUNCTURED BLOCK CODES 有权
标题翻译：冲击块编码的紧凑解码
公开(公告)号：US20110022921A1
公开(公告)日：2011-01-27
申请号：US12506327
申请日：2009-07-21
申请人： Eran SHARON , Idan ALROD , Simon LITSYN
发明人： Eran SHARON , Idan ALROD , Simon LITSYN
IPC分类号： H03M13/05 , G06F11/10
CPC分类号： H03M13/6362 , G06F11/1068 , H03M13/1111 , H03M13/15
摘要： k input bits are encoded according to a code with which is associated a m×n=m+k parity check matrix H. The resulting codeword is punctured, with n′
摘要翻译： k个输入位根据与m×n = m + k个奇偶校验矩阵H相关联的代码进行编码。所得码字被打孔，n'

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