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1. 发明授权

US09032269B2 Systems and methods of storing data 有权
标题翻译：存储数据的系统和方法
公开(公告)号：US09032269B2
公开(公告)日：2015-05-12
申请号：US13329819
申请日：2011-12-19
申请人： Eran Sharon , Idan Alrod , Simon Litsyn
发明人： Eran Sharon , Idan Alrod , Simon Litsyn
IPC分类号： H03M13/00 , G11C7/10 , G06F11/10 , G11C11/56
CPC分类号： G11C7/1006 , G06F11/1044 , G06F11/1068 , G06F11/1072 , G11C11/5628 , G11C11/5642 , G11C16/0483 , G11C16/10 , G11C29/78 , G11C2211/5641
摘要： A method of writing data includes receiving data pages to be stored in a data storage device and generating codewords corresponding to the received data pages. The codewords are stored to physical pages of a first memory portion of the data storage device. A first portion of a particular codeword that corresponds to a particular data page is stored at a first physical page of the first memory portion. A second portion of the particular codeword is stored at a second physical page of the first memory portion. The codewords are copied from the physical pages of the first memory portion to a physical page of a second memory portion of the data storage device.
摘要翻译：一种写入数据的方法包括接收要存储在数据存储装置中的数据页，并产生与接收的数据页对应的码字。码字被存储到数据存储设备的第一存储器部分的物理页面。对应于特定数据页的特定码字的第一部分存储在第一存储器部分的第一物理页面。特定码字的第二部分被存储在第一存储器部分的第二物理页面上。将码字从第一存储器部分的物理页面复制到数据存储设备的第二存储器部分的物理页面。

2. 发明授权

US08832518B2 Method and device for multi phase error-correction 有权
标题翻译：多相纠错方法和装置
公开(公告)号：US08832518B2
公开(公告)日：2014-09-09
申请号：US12034718
申请日：2008-02-21
申请人： Simon Litsyn , Eran Sharon , Idan Alrod , Menahem Lasser
发明人： Simon Litsyn , Eran Sharon , Idan Alrod , Menahem Lasser
IPC分类号： H03M13/00
CPC分类号： H03M13/2927 , G06F11/1068 , H03M13/1111 , H03M13/152 , H03M13/1545 , H03M13/2903 , H03M13/2906 , H03M13/3707 , H03M13/6362
摘要： Data bits to be encoded are split into a plurality of subgroups. Each subgroup is encoded separately to generate a corresponding codeword. Selected subsets are removed from the corresponding codewords, leaving behind shortened codewords, and are many-to-one transformed to condensed bits. The final codeword is a combination of the shortened codewords and the condensed bits. A representation of the final codeword is decoded by being partitioned to a selected subset and a plurality of remaining subsets. Each remaining subset is decoded separately. A subset whose decoding is terminated is decoded again, at least in part according to the selected subset. If the encoding and decoding are systematic then the selected subsets are of parity bits.
摘要翻译：要编码的数据位被分割成多个子组。每个子组被分别编码以产生相应的码字。所选择的子集从相应的码字中移除，留下缩短的码字，并且被多对一地转换成浓缩比特。最终码字是缩短的码字和浓缩比特的组合。最终码字的表示被分割成选定的子集和多个剩余子集。每个剩余子集被单独解码。解码终止的子集至少部分地根据所选择的子集被再次解码。如果编码和解码是系统的，则所选择的子集是奇偶校验位。

3. 发明授权

US08650462B2 Probabilistic error correction in multi-bit-per-cell flash memory 失效
标题翻译：多比特单元闪存中的概率误差校正
公开(公告)号：US08650462B2
公开(公告)日：2014-02-11
申请号：US12401634
申请日：2009-03-11
申请人： Simon Litsyn , Idan Alrod , Eran Sharon , Mark Murin , Menahem Lasser
发明人： Simon Litsyn , Idan Alrod , Eran Sharon , Mark Murin , Menahem Lasser
IPC分类号： G11C29/00 , H03M13/00
CPC分类号： H03M13/458 , G06F11/1012 , G06F11/1024 , G06F11/1068 , G06F11/1072 , G11C11/5642 , G11C2029/0409 , H03M13/45
摘要： Data that are stored in cells of a multi-bit-per cell memory, according to a systematic or non-systematic ECC, are read and corrected (systematic ECC) or recovered (non-systematic ECC) in accordance with estimated probabilities that one or more of the read bits are erroneous. In one method of the present invention, the estimates are a priori. In another method of the present invention, the estimates are based only on aspects of the read bits that include significances or bit pages of the read bits. In a third method of the present invention, the estimates are based only on values of the read bits. Not all the estimates are equal.
摘要翻译：根据系统或非系统ECC存储在多比特单元存储器的单元中的数据根据估计的概率被读取和校正（系统ECC）或恢复（非系统ECC）更多的读取位是错误的。在本发明的一种方法中，估计是先验的。在本发明的另一种方法中，估计仅基于包括读位的重要性或位页的读位的方面。在本发明的第三种方法中，估计仅基于读位的值。并不是所有的估计是相等的。

4. 发明授权

US08645789B2 Multi-phase ECC encoding using algebraic codes 有权
标题翻译：使用代数代码的多阶段ECC编码
公开(公告)号：US08645789B2
公开(公告)日：2014-02-04
申请号：US13335534
申请日：2011-12-22
申请人： Eran Sharon , Idan Alrod , Simon Litsyn
发明人： Eran Sharon , Idan Alrod , Simon Litsyn
IPC分类号： H03M13/00
CPC分类号： G06F11/1012
摘要： A method includes a first encoding operation associated with a first algebraic error correcting code generating a first set of first parity bits corresponding to a first set of information bits and a second set of first parity bits corresponding to a second set of information bits. A second encoding operation associated with a second algebraic error correcting code generates a first set of second parity bits corresponding to the first set of information bits and a second set of second parity bits corresponding to the second set of information bits. A third encoding operation generates a set of joint parity bits. The first set of information bits, the second set of information bits, the first set of first parity bits, the second set of first parity bits, and the joint parity bits may be stored in a data storage device as a single codeword.
摘要翻译：一种方法包括与第一代数纠错码相关联的第一编码操作，所述第一代数纠错码产生对应于第一组信息比特的第一奇偶校验位的第一组，以及与第二组信息比特对应的第二奇偶校验位组。与第二代数纠错码相关联的第二编码操作产生对应于第一组信息比特的第一组第二奇偶校验位和对应于第二组信息比特的第二奇偶校验位组。第三编码操作产生一组联合奇偶校验位。第一组信息位，第二组信息位，第一组第一奇偶校验位，第二组第一奇偶校验位和联合奇偶校验位可以作为单个码字存储在数据存储设备中。

5. 发明授权

US08429512B2 Reduced complexity LDPC decoder 有权
标题翻译：降低复杂度的LDPC解码器
公开(公告)号：US08429512B2
公开(公告)日：2013-04-23
申请号：US12404308
申请日：2009-03-15
申请人： Eran Sharon , Simon Litsyn , Idan Alrod
发明人： Eran Sharon , Simon Litsyn , Idan Alrod
IPC分类号： G06F11/00
CPC分类号： H03M13/1131 , H03M13/1114 , H03M13/6505 , H03M13/6588
摘要： To decode a manifestation of a codeword in which K information bits are encoded as N>K codeword bits, messages are exchanged between N bit nodes and N−K check nodes. During computation, messages are expressed with a full message length greater than two bits. In each iteration, representations of at least some of the exchanged messages are stored. For at least one node, if representations of messages sent from that node are stored, then the representation of one or more of the messages is stored using at least two bits but using fewer bits than the full message length, and the representation of one other message is stored with full message length. Preferably, the messages that are stored using fewer bits than the full message length are messages sent from check nodes.
摘要翻译：为了解码其中K个信息比特被编码为N> K个码字比特的码字的表现，在N个比特节点和N-K个校验节点之间交换消息。在计算期间，消息以大于两位的完整消息长度表示。在每次迭代中，存储至少一些交换的消息的表示。对于至少一个节点，如果存储从该节点发送的消息的表示，则使用至少两个比特来存储一个或多个消息的表示，但是使用比全消息长度更少的比特，并且另一个的表示消息以完整的消息长度存储。优选地，使用比完整消息长度少的位来存储的消息是从校验节点发送的消息。

6. 发明授权

US08042029B2 Error correction decoding by trial and error 有权
标题翻译：纠错解码通过反复试验
公开(公告)号：US08042029B2
公开(公告)日：2011-10-18
申请号：US11528556
申请日：2006-09-28
申请人： Idan Alrod , Eran Sharon , Simon Litsyn
发明人： Idan Alrod , Eran Sharon , Simon Litsyn
IPC分类号： H03M13/03
CPC分类号： H03M13/3738 , H03M13/3707 , H03M13/6502 , H03M13/6511
摘要： A representation of a codeword is decoded by applying a first decoder of the codeword to the representation of the codeword. If applying the first decoder fails to decode the representation of the codeword then a second decoder of the codeword is applied to the representation of the codeword. Preferably, applying the first decoder consumes less power and is faster than applying the second decoder. Data are ported by encoding the data as a codeword, exporting the codeword to a corrupting medium, importing a representation of the codeword, and applying a first decoder to the representation of the codeword. If applying the first decoder fails to decode the representation of the codeword then a second decoder of the codeword is applied to the representation of the codeword.
摘要翻译：通过将码字的第一解码器应用于码字的表示来解码码字的表示。如果应用第一解码器不能解码码字的表示，则码字的第二解码器被应用于码字的表示。优选地，应用第一解码器消耗较少的功率并且比应用第二解码器更快。数据通过将数据编码为码字来移植，将码字导出到破坏性介质，导入码字的表示，以及将第一解码器应用于码字的表示。如果应用第一解码器不能解码码字的表示，则码字的第二解码器被应用于码字的表示。

7. 发明授权

US07903468B2 Adaptive dynamic reading of flash memories 有权
标题翻译：闪存的自适应动态读取
公开(公告)号：US07903468B2
公开(公告)日：2011-03-08
申请号：US11941945
申请日：2007-11-18
申请人： Simon Litsyn , Idan Alrod , Eran Sharon
发明人： Simon Litsyn , Idan Alrod , Eran Sharon
IPC分类号： G11C16/04
CPC分类号： G11C16/10 , G11C11/5628 , G11C11/5642 , G11C16/28 , G11C2211/5634
摘要： Each of a plurality of flash memory cells is programmed to a respective one of L≧2 threshold voltage states within a threshold voltage window. Values of parameters of threshold voltage functions are adjusted in accordance with comparisons of the threshold voltages of some or all of the cells to two or more of m≧2 threshold voltage intervals within the threshold voltage window. Reference voltages for reading the cells are selected based on the values. Alternatively, the m threshold voltage intervals span the threshold voltage window, and respective threshold voltage states are assigned to the cells based on numbers of cells whose threshold voltages are in the intervals, without re-reading the cells.
摘要翻译：多个闪存单元中的每一个被编程为阈值电压窗口内的L≥2个阈值电压状态中的相应一个。根据阈值电压窗口内的一些或所有单元的阈值电压与两个或多个m≥2个阈值电压间隔的比较，来调整阈值电压函数的参数值。基于这些值来选择用于读取单元的参考电压。或者，m阈值电压间隔跨越阈值电压窗口，并且基于阈值电压处于间隔中的单元的数量而将各个阈值电压状态分配给单元，而不重新读取单元。

8. 发明授权

US07814401B2 Soft decoding of hard and soft bits read from a flash memory 有权
标题翻译：从闪存中读取硬和软位的软解码
公开(公告)号：US07814401B2
公开(公告)日：2010-10-12
申请号：US11642708
申请日：2006-12-21
申请人： Idan Alrod , Eran Sharon , Simon Litsyn , Menahem Lasser
发明人： Idan Alrod , Eran Sharon , Simon Litsyn , Menahem Lasser
IPC分类号： H03M13/00
CPC分类号： G11C11/5642 , G06F11/1068 , G06F11/1072 , G11C16/26 , G11C2211/5634
摘要： To read one or more flash memory cells, the threshold voltage of each cell is compared to at least one integral reference voltage and to at least one fractional reference voltage. Based on the comparisons, a respective estimated probability measure of each bit of an original bit pattern of each cell is calculated. This provides a plurality of estimated probability measures. Based at least in part on at least two of the estimated probability measures, respective original bit patterns of the cells are estimated. Preferably, the estimated probability measures are initial probability measures that are transformed to final probability measures under the constraint that the bit pattern(s) (collectively) is/are a member of a candidate set, e.g. a set of codewords.
摘要翻译：为了读取一个或多个闪存单元，将每个单元的阈值电压与至少一个积分参考电压和至少一个分数参考电压进行比较。基于比较，计算每个单元的原始比特模式的每个比特的相应估计概率测量。这提供了多个估计的概率度量。至少部分地基于估计的概率测量中的至少两个，估计小区的各自的原始比特模式。优选地，估计的概率度量是在比特模式（统称为）是候选集合的成员的约束下被转换为最终概率测量的初始概率测量，例如。一组码字。

9. 发明授权

US07643342B2 Multi-bit-per-cell flash memory device with non-bijective mapping 失效
标题翻译：具有非双射映射的多比特单元闪存器件
公开(公告)号：US07643342B2
公开(公告)日：2010-01-05
申请号：US12045733
申请日：2008-03-11
申请人： Simon Litsyn , Eran Sharon , Idan Alrod
发明人： Simon Litsyn , Eran Sharon , Idan Alrod
IPC分类号： G11C11/34 , G11C16/06 , G06F12/00 , G06F13/00
CPC分类号： G11C16/10 , G06F11/1072 , G11C7/1006 , G11C11/56 , G11C11/5628 , G11C16/0483 , G11C16/34 , G11C29/42 , G11C2211/5641
摘要： To store a plurality of input bits, the bits are mapped to a corresponding programmed state of one or more memory cells and the cell(s) is/are programmed to that corresponding programmed state. The mapping may be many-to-one or may be an “into” generalized Gray mapping. The cell(s) is/are read to provide a read state value that is transformed into a plurality of output bits, for example by maximum likelihood decoding or by mapping the read state value into a plurality of soft bits and then decoding the soft bits.
摘要翻译：为了存储多个输入位，这些位被映射到一个或多个存储器单元的相应的编程状态，并且单元被编程为相应的编程状态。映射可以是多对一的或者可以是“到”广义灰色映射。读取单元以提供被转换成多个输出位的读取状态值，例如通过最大似然解码或通过将读取状态值映射到多个软比特中，然后解码软比特。

10. 发明申请

US20090319858A1 REDUCED COMPLEXITY LDPC DECODER 有权
标题翻译：降低复杂LDPC解码器
公开(公告)号：US20090319858A1
公开(公告)日：2009-12-24
申请号：US12404308
申请日：2009-03-15
申请人： Eran SHARON , Simon Litsyn , Idan Alrod
发明人： Eran SHARON , Simon Litsyn , Idan Alrod
IPC分类号： H03M13/05 , G06F11/10
CPC分类号： H03M13/1131 , H03M13/1114 , H03M13/6505 , H03M13/6588
摘要： To decode a manifestation of a codeword in which K information bits are encoded as N>K codeword bits, messages are exchanged between N bit nodes and N−K check nodes. During computation, messages are expressed with a full message length greater than two bits. In each iteration, representations of at least some of the exchanged messages are stored. For at least one node, if representations of messages sent from that node are stored, then the representation of one or more of the messages is stored using at least two bits but using fewer bits than the full message length, and the representation of one other message is stored with full message length. Preferably, the messages that are stored using fewer bits than the full message length are messages sent from check nodes.
摘要翻译：为了解码其中K个信息比特被编码为N> K个码字比特的码字的表现，在N个比特节点和N-K个校验节点之间交换消息。在计算期间，消息以大于两位的完整消息长度表示。在每次迭代中，存储至少一些交换的消息的表示。对于至少一个节点，如果存储了从该节点发送的消息的表示，则使用至少两个比特来存储一个或多个消息的表示，但是使用比全消息长度少的比特，并且另一个的表示消息以完整的消息长度存储。优选地，使用比完整消息长度少的位来存储的消息是从校验节点发送的消息。

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