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    • 8. 发明授权
    • Semiconductor integrated circuit device
    • 半导体集成电路器件
    • US08174901B2
    • 2012-05-08
    • US12721553
    • 2010-03-10
    • Ken MatsubaraHideo KasaiKenji KawadaMakoto Mizuno
    • Ken MatsubaraHideo KasaiKenji KawadaMakoto Mizuno
    • G11C11/34
    • G11C7/02G11C16/06G11C16/32G11C16/3418
    • This invention is to reduce the number of memory gate drivers, while lessening the number of times of disturb occurrence in a memory array configuration that implements writing in small byte units. A memory array comprises a plurality of sub-arrays, MG transfers, SL drivers, and CG drivers. Each sub-array includes a plurality of memory gate lines, control gate lines, source lines, and bit lines. Memory cells are arranged in positions of intersections of these lines. The control gate lines, CG drivers, source lines, and SL drivers are common to the sub-arrays, whereas the memory gate lines and MG buffer circuits are provided for each sub-array. Thereby, the units in which data is written are decreased and adverse effects of disturb are reduced without increasing the circuit size of the memory array.
    • 本发明是减少存储器栅极驱动器的数量,同时减少以小字节为单位实现写入的存储器阵列配置中的干扰发生次数。 存储器阵列包括多个子阵列,MG传输,SL驱动器和CG驱动器。 每个子阵列包括多个存储器栅极线,控制栅极线,源极线和位线。 存储单元布置在这些线的相交位置。 控制栅极线,CG驱动器,源极线和SL驱动器对于子阵列是共同的,而为每个子阵列提供存储器栅极线和MG缓冲电路。 因此,数据写入的单元减少,并且不增加存储器阵列的电路尺寸的同时降低了干扰的不利影响。
    • 9. 发明申请
    • SEMICONDUCTOR DEVICE
    • 半导体器件
    • US20110208904A1
    • 2011-08-25
    • US13099720
    • 2011-05-03
    • Masamichi FujitoMakoto MizunoTakahiro YokoyamaKenji KawadaTakashi IwaseYasunobu AokiTakashi KurafujiTomohiro UchiyamaShuichi SatoYuji Uji
    • Masamichi FujitoMakoto MizunoTakahiro YokoyamaKenji KawadaTakashi IwaseYasunobu AokiTakashi KurafujiTomohiro UchiyamaShuichi SatoYuji Uji
    • G06F12/00
    • G11C7/04G11C16/0441G11C16/10G11C16/28
    • The semiconductor device includes a nonvolatile memory, having a memory array containing 1-bit twin cells, each composed of electrically rewritable first and second storage devices, the first and second storage devices holding binary data according to difference of their threshold voltages, and having different retention characteristics depending on difference of the binary data thereof; a read circuit for differentially amplifying complementary data output from the first and second storage devices of the twin cell selected for read, and judging information stored in the twin cell; and a control circuit. Two memory cells constituting a twin cell are arranged to hold different data. Therefore, even when the retention performance of one memory cell deteriorates, the difference between data held by the two memory cells can be maintained. Hence, differential amplification of such difference enables acquisition of proper stored information. Thus, retention performance of an electrically rewritable nonvolatile memory cell is improved.
    • 半导体器件包括非易失性存储器,具有包含1比特双胞格的存储器阵列,每个存储器阵列由电可重写的第一和第二存储器件组成,第一和第二存储器件根据其阈值电压的差异保持二进制数据,并且具有不同的 保留特性取决于其二进制数据的差异; 用于差分放大从被选择读取的双胞胎的第一和第二存储装置输出的互补数据的读取电路,以及判断存储在双胞胎中的信息; 和控制电路。 布置构成双胞胎的两个存储单元以保存不同的数据。 因此,即使一个存储单元的保持性能劣化,也能够维持由两个存储单元保持的数据之间的差异。 因此,这种差异的差分放大使得能够获得正确的存储信息。 因此,提高了电可重写非易失性存储单元的保持性能。