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1. 发明授权

US10962933B1 Multibit per stage pipelined time-to-digital converter (TDC) 有权
公开(公告)号：US10962933B1
公开(公告)日：2021-03-30
申请号：US17125089
申请日：2020-12-17
申请人： IQ—Analog Corporation
发明人： Mikko Waltari
IPC分类号： G04F10/00 , H03M1/50 , H03M1/12
摘要： A multi-symbol per stage pipelined time-to-digital converter (TDC) is presented. The TDC includes a quantizer and a residue generator. The quantizer has an input to accept an analog input first time-differential signal comprising a binary level first edge separated from a binary level second edge by a first duration of time. The first time-differential signal is capable as being represented by m time intervals. The quantizer has an output to supply a first digital code representing Ceil(log2(m)) bit values responsive to (m−1) time interval measurements. The first digital code is a time-to-digital conversion. For example, if the first time-differential signal is capable of being represented as a p-bit binary coded digital word, the quantizer outputs a first digital code representing the Ceil(log2(m)) most significant bit (MSB) values of the p-bit digital word.

2. 发明授权

US09281834B1 N-path interleaving analog-to-digital converter (ADC) with offset gain and timing mismatch calibration 有权
标题翻译：具有偏移增益和定时不匹配校准的N路径交错模数转换器（ADC）
公开(公告)号：US09281834B1
公开(公告)日：2016-03-08
申请号：US14927077
申请日：2015-10-29
申请人： IQ-Analog Corporation
发明人： Mikko Waltari
IPC分类号： H03M1/10 , H03M1/12
CPC分类号： H03M1/1023 , H03M1/0626 , H03M1/0836 , H03M1/1052 , H03M1/121 , H03M1/1215 , H03M1/1245
摘要： A system and method are provided for calibrating timing mismatch in an n-path time interleaved analog-to-digital converter (ADC). The method digitizes an analog signal with an n-path interleaved ADC, creating an interleaved ADC signal. In a first process, the phase of the interleaved ADC signal is rotated by 90 degrees, creating a rotated signal. This rotation may be accomplished using a finite impulse response (FIR) filter with taps at {0.5, 0, −0.5}, enabled as a derivative filter, or as a Hilbert transformation. In a parallel second process, the interleaved ADC signal is delayed, creating a delayed signal. The rotated signal is multiplied by the delayed signal to create a timing error signal. Using the timing error signal, timing errors are accumulated for the ADC signal paths, and corrections are applied that minimize timing errors in each of the n ADC signal paths.
摘要翻译：提供了一种用于校准n路时间交错模数转换器（ADC）中的定时失配的系统和方法。该方法将模拟信号与n路交错ADC进行数字化，产生交错的ADC信号。在第一过程中，交错的ADC信号的相位旋转90度，产生旋转的信号。该旋转可以使用具有{0.5,0，-0.5}的抽头的有限脉冲响应（FIR）滤波器，作为导数滤波器使能，或作为希尔伯特变换来完成。在并行的第二过程中，交织的ADC信号被延迟，产生延迟的信号。旋转的信号乘以延迟信号以产生定时误差信号。使用定时误差信号，对ADC信号路径累积定时误差，并且施加使n个ADC信号路径中的每一个中的定时误差最小化的校正。

3. 发明申请

US20150212494A1 Traveling Pulse Wave Quantizer 有权
标题翻译：旅行脉冲波量化器
公开(公告)号：US20150212494A1
公开(公告)日：2015-07-30
申请号：US14681206
申请日：2015-04-08
申请人： IQ-Analog Corporation
发明人： Mikko Waltari
IPC分类号： G04F10/00 , H03M1/12
CPC分类号： G04F10/005 , H03M1/1295 , H03M1/50 , H03M1/502 , H03M1/60
摘要： A Traveling Pulse Wave Quantization method is provided for converting a time sensitive signal to a digital value. A first stop signal is delayed by a first time delay, a first plurality of times, to create a delayed first stop signal. A clock signal is delayed by a second time delay, a first plurality of times, to create a delayed clock signal first period. Each second time delay is associated with a corresponding first time delay, and the second time delay is greater than the first time delay. When the delayed first stop signal occurs before the delayed clock signal first period, a count of the delays is stopped and converted into a digital or thermometer value. An accurate resampled value is provided regardless of the duration in delay between the first stop signal and a second stop signal that is accepted after the first stop signal.
摘要翻译：提供了一种将时间敏感信号转换为数字值的行波脉冲波量化方法。第一停止信号被延迟第一时间延迟，第一次多次，以产生延迟的第一停止信号。时钟信号被延迟第二时间延迟，第一次多次，以产生延迟的时钟信号第一周期。每个第二时间延迟与对应的第一时间延迟相关联，并且第二时间延迟大于第一时间延迟。当延迟的第一停止信号在延迟时钟信号第一周期之前发生时，延迟的计数被停止并转换成数字或温度计值。无论第一停止信号和第一停止信号之后接受的第二停止信号的延迟持续时间如何，均提供精确的重采样值。

4. 发明授权

US08928513B1 Current steering digital-to-analog converter (DAC) switch driver 有权
标题翻译：电流转向数模转换器（DAC）开关驱动器
公开(公告)号：US08928513B1
公开(公告)日：2015-01-06
申请号：US14489582
申请日：2014-09-18
申请人： IQ-Analog Corporation
发明人： Mikko Waltari
IPC分类号： H03M1/66
CPC分类号： H03M1/66 , H03M1/0863 , H03M1/742
摘要： A current steering digital-to-analog converter (DAC) switch driver circuit is provided. The circuit is composed of a conditioning module having a signal input to accept a binary logic digital signal, and signal outputs to supply differential driver signals V+ and V− with a low voltage level (Vlow) greater than the binary logic digital signal low voltage level. Typically, Vlow has a greater potential than ground (0V). A DAC current steering cell has a signal input to accept the differential driver signals and an output to supply a differential analog current responsive to the differential driver signals. The DAC current steering cell may be an NMOS DAC current steering cell. The conditioning module may be a CMOS switch driver, or composed of a level shifter followed by a CMOS switch driver.
摘要翻译：提供了一种电流转向数模转换器（DAC）开关驱动电路。该电路由具有接收二进制逻辑数字信号的信号输入的信号输出和信号输出组成，该信号输出以比二进制逻辑数字信号低电压电平大的低电压电平（Vlow）提供差动驱动信号V +和V- 。通常，Vlow具有比接地（0V）更大的电位。 DAC电流导向单元具有接收差分驱动器信号的信号输入和响应于差分驱动器信号的差分模拟电流的输出。 DAC电流导向单元可以是NMOS DAC电流导向单元。调节模块可以是CMOS开关驱动器，或者由电平转换器和CMOS开关驱动器组成。

5. 发明授权

US09912344B1 Sort-and delay methods for time-to-digital conversion 有权
公开(公告)号：US09912344B1
公开(公告)日：2018-03-06
申请号：US15706732
申请日：2017-09-17
申请人： IQ-Analog Corporation
发明人： Mikko Waltari
IPC分类号： H03M1/12 , H03M1/44 , H03M1/06
CPC分类号： H03M1/0624 , H03M1/50
摘要： A sort-and-delay time-to-digital converter (TDC) is provided, made up of a plurality of serially connected sort-and-delay circuits. Each sort-and-delay circuit accepts a time-differential input signal with a first edge separated from a second edge by an input duration of time. The first and second edges are selectively routed as a time-differential output signal with a delayed edge separated from a trailing edge by an output duration of time representing a compression of the input duration of time. Each sort-and-delay circuit also supplies a TDC coded bit (e.g., Gray code) indicating the order in which the first and second edges are routed as leading and trailing edges. The TDC outputs a digital output signal representing the initial input duration of time associated with the initial time-differential input signal received by the initial sort-and-delay circuit. Associated TDC, sort-and-delay, and time amplification methods are also provided.

6. 发明授权

US09831888B1 Sort-and delay time-to-digital converter 有权
公开(公告)号：US09831888B1
公开(公告)日：2017-11-28
申请号：US15614705
申请日：2017-06-06
申请人： IQ-Analog Corporation
发明人： Mikko Waltari
IPC分类号： H03M1/12 , H03M1/44 , H03M1/06
CPC分类号： H03M1/0624 , H03M1/50
摘要： A sort-and-delay time-to-digital converter (TDC) is provided, made up of a plurality of serially connected sort-and-delay circuits. Each sort-and-delay circuit accepts a time-differential input signal with a first edge separated from a second edge by an input duration of time. The first and second edges are selectively routed as a time-differential output signal with a delayed edge separated from a trailing edge by an output duration of time representing a compression of the input duration of time. Each sort-and-delay circuit also supplies a TDC coded bit (e.g., Gray code) indicating the order in which the first and second edges are routed as leading and trailing edges. The TDC outputs a digital output signal representing the initial input duration of time associated with the initial time-differential input signal received by the initial sort-and-delay circuit. Associated TDC, sort-and-delay, and time amplification methods are also provided.

7. 发明申请

US20150145709A1 N-Path Interleaving Analog-to-Digital Converter (ADC) with Background Calibration 有权
标题翻译：具有背景校准的N路径交错模数转换器（ADC）
公开(公告)号：US20150145709A1
公开(公告)日：2015-05-28
申请号：US14531371
申请日：2014-11-03
申请人： IQ-Analog Corporation
发明人： Mikko Waltari
IPC分类号： H03M1/06 , H03M1/12
CPC分类号： H03M1/1245 , H03M1/0626 , H03M1/0836 , H03M1/1215
摘要： A system and method are provided of performing background corrections for an interleaving analog-to-digital converter (ADC). An analog input signal s1(t) is accepted having a first frequency f1 and a bandwidth (BW). A clock at frequency fs creates n sample clocks with evenly spaced phases, each having a sample clock frequency of fs/2. A first tone signal s2(t) is generated at second frequency f2, outside BW. The analog input signal and the first tone signal are combined, creating a combination signal, which is sampled using the sample clocks, creating n digital sample signals per clock period 1/fs. The n digital sample signals are interleaved, creating an interleaved signal. Corrections are applied that minimize errors in the interleaved signal, to obtain a corrected digital output. Errors are determined at an alias frequency f3, associated with the second frequency f2, to obtain correction information for a rotating pair of digital sample signals.
摘要翻译：提供了一种用于对交错模数转换器（ADC）执行背景校正的系统和方法。接受具有第一频率f1和带宽（BW）的模拟输入信号s1（t）。频率为fs的时钟产生具有均匀间隔相位的n个采样时钟，每个时钟采样时钟频率为fs / 2。第二音频信号s2（t）在BW外部的第二频率f2产生。组合模拟输入信号和第一音调信号，产生一个组合信号，采用采样时钟进行采样，每个时钟周期1 / fs创建n个数字采样信号。 n个数字采样信号被交织，产生交错信号。应用校正来最小化交错信号中的误差，以获得校正的数字输出。以与第二频率f2相关联的别名频率f3确定错误，以获得旋转数字采样信号对的校正信息。

8. 发明授权

US09035810B1 System and method for digital-to-analog converter calibration 有权
标题翻译：用于数模转换器校准的系统和方法
公开(公告)号：US09035810B1
公开(公告)日：2015-05-19
申请号：US14602095
申请日：2015-01-21
申请人： IQ-Analog Corporation
发明人： Mikko Waltari , Costantino Pala
IPC分类号： H03M1/10 , H03M1/68 , H03M1/66
CPC分类号： H03M1/1038 , H03M1/742
摘要： A system and method are provided for measuring current sources, such as might be useful in the calibration of a digital-to-analog converter (DAC). The method provides a first plurality of current sources. Each current source is engageable to supply a current representing a corresponding nominal value. The method selectively enables current source combinations of current. In response to measuring the current source combinations, current difference values are found, and the current source nominal values are adjusted using the current difference values. In one aspect, a reference current source is provided having a reference first value, and the current source nominal values are adjusted with respect to the reference first value. The current sources may have corresponding nominal digital values adjusted using measured digital difference values.
摘要翻译：提供了一种用于测量电流源的系统和方法，例如在数模转换器（DAC）的校准中可能是有用的。该方法提供第一多个电流源。每个电流源可接合以提供表示相应的标称值的电流。该方法选择性地实现电流的电流源组合。响应于测量电流源组合，找到电流差值，并使用电流差值调整电流源标称值。在一个方面，提供具有参考第一值的参考电流源，并且相对于参考第一值调整电流源标称值。电流源可以使用测量的数字差值调整相应的标称数字值。

9. 发明授权

US08917125B1 Interleaving analog-to-digital converter (ADC) with background calibration 有权
标题翻译：用背景校准交错模数转换器（ADC）
公开(公告)号：US08917125B1
公开(公告)日：2014-12-23
申请号：US14511206
申请日：2014-10-10
申请人： IQ-Analog Corporation
发明人： Mikko Waltari
IPC分类号： H03L7/06 , H03M1/06 , H03M1/12
CPC分类号： H03M1/0626 , H03M1/0836 , H03M1/1215 , H03M1/124 , H03M1/1245
摘要： A system and method are provided of performing background corrections for an interleaving analog-to-digital converter (ADC). An analog input signal s1(t) is accepted having a first frequency f1 and a bandwidth (BW). The method generates a clock at frequency fs, and creates 2 sample clocks with evenly spaced phases, each having a sample clock frequency of fs/2. The method also generates a first tone signal s2(t) having a predetermined second frequency f2 outside BW. The analog input signal and the first tone signal are combined, creating a combination signal, which is sampled using the sample clocks, creating 2 digital sample signals per clock period 1/fs. The 2 digital sample signals are interleaved, creating an interleaved signal. Corrections are applied that minimize errors in the interleaved signal, to obtain a corrected digital output. Errors are determined at an alias frequency f3, associated with the second frequency f2, to obtain correction information.
摘要翻译：提供了一种用于对交错模数转换器（ADC）执行背景校正的系统和方法。接受具有第一频率f1和带宽（BW）的模拟输入信号s1（t）。该方法以频率fs产生时钟，并产生具有均匀间隔相位的2个采样时钟，每个时钟采样时钟频率为fs / 2。该方法还产生具有BW以外的预定的第二频率f2的第一音调信号s2（t）。组合模拟输入信号和第一音调信号，产生一个组合信号，采用采样时钟进行采样，每个时钟周期1 / fs创建2个数字采样信号。 2个数字采样信号被交织，产生交错信号。应用校正来最小化交错信号中的误差，以获得校正的数字输出。以与第二频率f2相关联的别名频率f3确定错误，以获得校正信息。

10. 发明授权

US08917124B1 Frequency multiplier jitter correction 有权
标题翻译：倍频器抖动校正
公开(公告)号：US08917124B1
公开(公告)日：2014-12-23
申请号：US14503656
申请日：2014-10-01
申请人： IQ-Analog Corporation
发明人： Mikko Waltari , Michael Kappes , William Huff
IPC分类号： H03L7/06 , H03L7/091 , H03L7/093 , H03L7/097
CPC分类号： H03L7/091 , H03L7/093 , H03L7/097 , H03L7/18 , H03L7/1806 , H03L2207/10 , H03L2207/50 , H03M1/0626 , H03M1/0836 , H03M1/12 , H03M1/1215 , H03M1/1245
摘要： A system and method are provided for frequency multiplication jitter correction. The method accepts an analog reference signal having a first frequency, and using the analog reference signal, derives a system clock signal having a second frequency, greater than the first frequency. A PLL using a voltage controlled oscillator (VCO) is one example of a frequency multiplier. The method samples the amplitude of the analog reference signal using the system clock signal and converts the sampled analog reference signal into a digitized reference signal. In response to comparing the digitized reference signal to an ideal digitized reference signal, the phase error correction for the system clock signal is derived. The phase error correction at a first instance of time can be applied to the digitized data signal, previously converted from an analog data signal sampled at a first instance of time with the system clock signal.
摘要翻译：提供了一种用于倍频抖动校正的系统和方法。该方法接受具有第一频率的模拟参考信号，并且使用模拟参考信号导出具有大于第一频率的第二频率的系统时钟信号。使用压控振荡器（VCO）的PLL是倍频器的一个例子。该方法使用系统时钟信号对模拟参考信号的振幅进行采样，并将采样的模拟参考信号转换为数字化参考信号。响应于将数字化参考信号与理想数字化参考信号进行比较，导出系统时钟信号的相位误差校正。在第一时刻的相位误差校正可以应用于数字化数据信号，该数字化数据信号是先前从系统时钟信号在第一时刻采样的模拟数据信号转换的。

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