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1. 发明申请

US20180129578A1 VERIFYING A GRAPH-BASED COHERENCY VERIFICATION TOOL 审中-公开
公开(公告)号：US20180129578A1
公开(公告)日：2018-05-10
申请号：US15863186
申请日：2018-01-05
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Thomas P. GROSSER , Gerrit KOCH , Ralf WINKELMANN
IPC分类号： G06F11/26 , G06F11/36 , G06F17/50 , G06F11/263 , G06F12/0815 , G06F12/0811 , G06F12/084
CPC分类号： G06F11/261 , G06F11/263 , G06F11/3608 , G06F12/0811 , G06F12/0815 , G06F12/084 , G06F17/509
摘要： Verification is provided of a functional correctness of a graph-based coherency verification tool for logic designs of arrangements of processors and processor caches, the graph-based coherency verification tool using trace files as input for verifying memory ordering rules of a given processor architecture for accesses to the caches, wherein nodes in a graph represent memory accesses and edges represent dependencies between them. The verifying includes (i) providing a specification of a test case for a self-checking tool, the test case comprising a sequence of statements in a high-level description language format, representing memory access events and system events; and (ii) generating trace files with the self-checking tool for the graph-based coherency verification tool by producing permutations of trace events, which are defined by the sequence of statements of the test case.

2. 发明申请

US20160132417A1 VERIFYING A GRAPH-BASED COHERENCY VERIFICATION TOOL 审中-公开
标题翻译：验证基于图形的相似验证工具
公开(公告)号：US20160132417A1
公开(公告)日：2016-05-12
申请号：US14929741
申请日：2015-11-02
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Thomas P. GROSSER , Gerrit KOCH , Ralf WINKELMANN
IPC分类号： G06F11/32 , G06F11/26 , G06F11/22 , G06F12/08 , G06F11/07
CPC分类号： G06F11/261 , G06F11/263 , G06F11/3608 , G06F12/0811 , G06F12/0815 , G06F12/084 , G06F17/509
摘要： Verification is provided of a functional correctness of a graph-based coherency verification tool for logic designs of arrangements of processors and processor caches, the graph-based coherency verification tool using trace files as input for verifying memory ordering rules of a given processor architecture for accesses to the caches, wherein nodes in a graph represent memory accesses and edges represent dependencies between them. The verifying includes (i) providing a specification of a test case for a self-checking tool, the test case comprising a sequence of statements in a high-level description language format, representing memory access events and system events; and (ii) generating trace files with the self-checking tool for the graph-based coherency verification tool by producing permutations of trace events, which are defined by the sequence of statements of the test case.
摘要翻译：提供了基于图形的一致性验证工具的功能正确性，用于处理器和处理器高速缓存的布置的逻辑设计，基于图的一致性验证工具使用跟踪文件作为输入，用于验证给定处理器架构的存储器排序规则以进行访问到缓存，其中图中的节点表示存储器访问，边缘表示它们之间的依赖关系。验证包括（i）为自检工具提供测试用例的规范，测试用例包括高级描述语言格式的语句序列，表示存储器访问事件和系统事件; 并且（ii）通过产生由测试用例的语句序列定义的跟踪事件的排列，生成具有用于基于图表的一致性验证工具的自检工具的跟踪文件。

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