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1. 发明申请

US20220309000A1 POWER OPTIMIZED PREFETCHING IN SET-ASSOCIATIVE TRANSLATION LOOKASIDE BUFFER STRUCTURE 有权
公开(公告)号：US20220309000A1
公开(公告)日：2022-09-29
申请号：US17215287
申请日：2021-03-29
申请人： International Business Machines Corporation
发明人： David Campbell , George W. Rohrbaugh, III , Jake Truelove , Jon K. Kriegel , Charles D. Wait , Jody Joyner
IPC分类号： G06F12/0862 , G06F12/0864 , G06F12/1045 , G06F12/02
摘要： A computer system includes a processor and a prefetch engine. The processor is configured to generate a demand access stream. The prefetch engine is configured to initiate a first prefetch request based on the demand access stream and perform a first prefetch that includes performing a translation lookaside buffer (TLB) lookup on a TLB structure in response to the first prefetch request. The processor determines a TLB entry in response to performing the TLB lookup and performs at least one second prefetch based on the TLB entry without performing a subsequent TLB lookup on the TLB structure.

2. 发明授权

US11422947B2 Determining page size via page table cache 有权
公开(公告)号：US11422947B2
公开(公告)日：2022-08-23
申请号：US16991075
申请日：2020-08-12
申请人： International Business Machines Corporation
发明人： David Campbell , Jake Truelove , Charles D. Wait , Jon K. Kriegel
IPC分类号： G06F12/1045 , G06F12/1027 , G06F12/1009
摘要： A page directory entry cache (PDEC) can be checked to potentially rule out one or more possible page sizes for a translation lookaside buffer (TLB) lookup. Information gained from the PDEC lookup can reduce the number of TLB checks required to conclusively determine if the TLB lookup is a hit or a miss.

3. 发明授权

US08726295B2 Network on chip with an I/O accelerator 失效
标题翻译：使用I / O加速器的网络芯片
公开(公告)号：US08726295B2
公开(公告)日：2014-05-13
申请号：US13785288
申请日：2013-03-05
申请人： International Business Machines Corporation
发明人： Russell D. Hoover , Jon K. Kriegel , Eric O. Mejdrich
IPC分类号： G06F3/00 , G06F9/44 , G06F9/46 , G06F13/00 , G06F15/00
CPC分类号： G06F9/546 , G06F15/7825 , H04L45/00
摘要： Data processing on a network on chip (‘NOC’) that includes IP blocks, routers, memory communications controllers, and network interface controllers; each IP block adapted to a router through a memory communications controller and a network interface controller; each memory communications controller controlling communication between an IP block and memory; each network interface controller controlling inter-IP block communications through routers; each IP block adapted to the network by a low latency, high bandwidth application messaging interconnect comprising an inbox and an outbox; a computer software application segmented into stages, each stage comprising a flexibly configurable module of computer program instructions identified by a stage ID with each stage executing on a thread of execution on an IP block; and at least one of the IP blocks comprising an input/output (‘I/O’) accelerator that administers at least some data communications traffic to and from the at least one IP block.
摘要翻译：芯片上的数据处理（“NOC”）包括IP块，路由器，存储器通信控制器和网络接口控制器; 每个IP块通过存储器通信控制器和网络接口控制器适应于路由器; 每个存储器通信控制器控制IP块和存储器之间的通信; 每个网络接口控制器通过路由器控制IP间块通信; 每个IP块通过包括收件箱和发件箱的低延迟，高带宽应用消息互连来适应于网络; 每个阶段包括由阶段ID标识的计算机程序指令的灵活可配置模块，每个阶段在IP块上的执行线程上执行; 并且所述IP块中的至少一个包括向所述至少一个IP块执行至少一些数据通信业务的输入/输出（'I / O'）加速器。

4. 发明授权

US11636043B2 Sleeping and waking-up address translation that conflicts with translation level of active page table walks 有权
公开(公告)号：US11636043B2
公开(公告)日：2023-04-25
申请号：US17461919
申请日：2021-08-30
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Charles D. Wait , Jake Truelove , David Campbell , Jody Joyner , Jon K. Kriegel , Glenn O. Kincaid
IPC分类号： G06F12/1009
摘要： A memory address translation system includes a translation requestor module configured to provide translation requests from a virtual address to a real address of a physical memory. A translation cache module is configured to receive the translation request from the translation requestor module. A sleep and wake control module is configured to compare the received VA to VA's of all presently active table walks of the table walk machines. Upon determining that there is an address match in a given table walk machine, the translation request is sent with an identification number (ID) to the translation requestor module, to be put to sleep. Each table walk machine is configured to provide a wake-up signal having an ID to the translation requestor module upon completion of its translation level, thereby triggering a waking up and processing of a presently sleeping translation request, to provide parallel translation table walks.

5. 发明申请

US20230062909A1 SLEEP / WAKE-UP PERFORMANCE ENHANCING FOR SIMULTANEOUS ADDRESS TRANSLATION TABLE WALKS 有权
公开(公告)号：US20230062909A1
公开(公告)日：2023-03-02
申请号：US17461919
申请日：2021-08-30
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Charles D. Wait , Jake Truelove , David Campbell , Jody Joyner , Jon K. Kriegel , Glenn O. Kincaid
IPC分类号： G06F12/1009
摘要： A memory address translation system includes a translation requestor module configured to provide translation requests from a virtual address to a real address of a physical memory. A translation cache module is configured to receive the translation request from the translation requestor module. A sleep and wake control module is configured to compare the received VA to VA's of all presently active table walks of the table walk machines. Upon determining that there is an address match in a given table walk machine, the translation request is sent with an identification number (ID) to the translation requestor module, to be put to sleep. Each table walk machine is configured to provide a wake-up signal having an ID to the translation requestor module upon completion of its translation level, thereby triggering a waking up and processing of a presently sleeping translation request, to provide parallel translation table walks.

6. 发明申请

US20220292028A1 UNIFIED TRANSLATION MISS QUEUE FOR MULTIPLE ADDRESS TRANSLATION MODES 有权
公开(公告)号：US20220292028A1
公开(公告)日：2022-09-15
申请号：US17199315
申请日：2021-03-11
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Charles D. Wait , David Campbell , Jake Truelove , Jody Joyner , Jon K. Kriegel , Glenn O. Kincaid
IPC分类号： G06F12/1009 , G06F12/1045 , G06F12/0864 , G06F12/0882
摘要： A unified memory address translation system includes a translation queue module configured to receive different modes of translation requests for a real address (RA) of a physical memory. A translation cache (XLTC) interface is configured to receive successful translation results for previous requests for an RA and provide the previous successful translation result to the translation queue module. A plurality of page table entry group (PTEG) search modules are coupled to the translation queue module. A unified translation walk address generation (UTWAG) module is configured to provide a translation support for each mode of the different modes of translation request. A memory interface is coupled between the UTWAG and the physical memory.

7. 发明申请

US20130179902A1 Network On Chip With An I/O Accelerator 失效
标题翻译：使用I / O加速器的片上网络
公开(公告)号：US20130179902A1
公开(公告)日：2013-07-11
申请号：US13785288
申请日：2013-03-05
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Russell D. Hoover , Jon K. Kriegel , Eric O. Mejdrich
IPC分类号： G06F9/54
CPC分类号： G06F9/546 , G06F15/7825 , H04L45/00
摘要： Data processing on a network on chip (‘NOC’) that includes IP blocks, routers, memory communications controllers, and network interface controllers; each IP block adapted to a router through a memory communications controller and a network interface controller; each memory communications controller controlling communication between an IP block and memory; each network interface controller controlling inter-IP block communications through routers; each IP block adapted to the network by a low latency, high bandwidth application messaging interconnect comprising an inbox and an outbox; a computer software application segmented into stages, each stage comprising a flexibly configurable module of computer program instructions identified by a stage ID with each stage executing on a thread of execution on an IP block; and at least one of the IP blocks comprising an input/output (‘I/O’) accelerator that administers at least some data communications traffic to and from the at least one IP block.
摘要翻译：芯片上的数据处理（“NOC”）包括IP块，路由器，存储器通信控制器和网络接口控制器; 每个IP块通过存储器通信控制器和网络接口控制器适应于路由器; 每个存储器通信控制器控制IP块和存储器之间的通信; 每个网络接口控制器通过路由器控制IP间块通信; 每个IP块通过包括收件箱和发件箱的低延迟，高带宽应用消息互连来适应于网络; 每个阶段包括由阶段ID标识的计算机程序指令的灵活可配置模块，每个阶段在IP块上的执行线程上执行; 并且所述IP块中的至少一个包括对至少一个IP块执行至少一些数据通信业务的输入/输出（“I / O”）加速器。

8. 发明授权

US11556475B2 Power optimized prefetching in set-associative translation lookaside buffer structure 有权
公开(公告)号：US11556475B2
公开(公告)日：2023-01-17
申请号：US17215287
申请日：2021-03-29
申请人： International Business Machines Corporation
发明人： David Campbell , George W. Rohrbaugh, III , Jake Truelove , Jon K. Kriegel , Charles D. Wait , Jody Joyner
IPC分类号： G06F12/0862 , G06F12/02 , G06F12/1045 , G06F12/0864
摘要： A computer system includes a processor and a prefetch engine. The processor is configured to generate a demand access stream. The prefetch engine is configured to initiate a first prefetch request based on the demand access stream and perform a first prefetch that includes performing a translation lookaside buffer (TLB) lookup on a TLB structure in response to the first prefetch request. The processor determines a TLB entry in response to performing the TLB lookup and performs at least one second prefetch based on the TLB entry without performing a subsequent TLB lookup on the TLB structure.

9. 发明授权

US11221957B2 Promotion of ERAT cache entries 有权
公开(公告)号：US11221957B2
公开(公告)日：2022-01-11
申请号：US16119013
申请日：2018-08-31
申请人： International Business Machines Corporation
发明人： Bartholomew Blaner , Jay G. Heaslip , Benjamin Herrenschmidt , Robert D. Herzl , Jody Joyner , Jon K. Kriegel , Charles D. Wait
IPC分类号： G06F12/0897 , G06F12/02 , G06F12/1009
摘要： A method, computer program product, and a computer system are disclosed for processing information in a processor that in one or more embodiments includes receiving a request for an Effective Address to Real Address Translation (ERAT); determining whether there is a permissions miss; changing, in response to determining there is a permission miss, permissions of an ERAT cache entry; and providing a Real Address translation. The method, computer program product, and computer system may optionally include providing a promote checkout request to a memory management unit (MMU).

10. 发明申请

US20200073817A1 PROMOTION OF ERAT CACHE ENTRIES 审中-公开
公开(公告)号：US20200073817A1
公开(公告)日：2020-03-05
申请号：US16119013
申请日：2018-08-31
申请人： International Business Machines Corporation
发明人： Bartholomew Blaner , Jay G. Heaslip , Benjamin Herrenschmidt , Robert D. Herzl , Jody Joyner , Jon K. Kriegel , Charles D. Wait
IPC分类号： G06F12/0897 , G06F12/02 , G06F12/1009
摘要： A method, computer program product, and a computer system are disclosed for processing information in a processor that in one or more embodiments includes receiving a request for an Effective Address to Real Address Translation (ERAT); determining whether there is a permissions miss; changing, in response to determining there is a permission miss, permissions of an ERAT cache entry; and providing a Real Address translation. The method, computer program product, and computer system may optionally include providing a promote checkout request to a memory management unit (MMU).

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