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1. 发明授权

US10460937B2 Post growth heteroepitaxial layer separation for defect reduction in heteroepitaxial films 有权
公开(公告)号：US10460937B2
公开(公告)日：2019-10-29
申请号：US15805801
申请日：2017-11-07
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Stephen W. Bedell , Cheng-Wei Cheng , Kunal Mukherjee , John A. Ott , Devendra K. Sadana , Brent A. Wacaser
IPC分类号： H01L21/02 , H01L21/3065 , H01L21/306 , H01L29/04
摘要： A method for reducing crystalline defects in a semiconductor structure is presented. The method includes epitaxially growing a first crystalline material over a crystalline substrate, epitaxially growing a second crystalline material over the first crystalline material, and patterning and removing portions of the second crystalline material to form openings. The method further includes converting the first crystalline material into a non-crystalline material, depositing a thermally stable material in the openings, depositing a capping layer over the second crystalline material and the thermally stable material to form a substantially enclosed semiconductor structure, and annealing the substantially enclosed semiconductor structure.

2. 发明授权

US09859091B1 Automatic alignment for high throughput electron channeling contrast imaging 有权
公开(公告)号：US09859091B1
公开(公告)日：2018-01-02
申请号：US15187476
申请日：2016-06-20
申请人： International Business Machines Corporation
发明人： Stephen W. Bedell , Kunal Mukherjee , John A. Ott , Devendra K. Sadana , Brent A. Wacaser
IPC分类号： H01J37/28 , H01J37/147 , G01N23/207 , G01N23/203
CPC分类号： H01J37/1478 , G01N23/203 , G01N23/207 , G01N2223/321 , G01N2223/401 , G01N2223/418 , G01N2223/6116 , H01J2237/1506
摘要： An automatic method is provided to align a semiconductor crystalline substrate for electron channeling contrast imaging (ECCI) in regions where an electron channeling pattern cannot be reliably obtained but crystalline defects need to be imaged. The automatic semiconductor crystalline substrate alignment method is more reproducible and faster than the current operator intensive process for ECCI alignment routines. Also, the automatic semiconductor crystalline substrate alignment method increases the throughput of ECCI.

3. 发明申请

US20170365441A1 AUTOMATIC ALIGNMENT FOR HIGH THROUGHPUT ELECTRON CHANNELING CONTRAST IMAGING 有权
公开(公告)号：US20170365441A1
公开(公告)日：2017-12-21
申请号：US15187476
申请日：2016-06-20
申请人： International Business Machines Corporation
发明人： Stephen W. Bedell , Kunal Mukherjee , John A. Ott , Devendra K. Sadana , Brent A. Wacaser
IPC分类号： H01J37/147 , G01N23/207 , G01N23/203
CPC分类号： H01J37/1478 , G01N23/203 , G01N23/207 , G01N2223/321 , G01N2223/401 , G01N2223/418 , G01N2223/6116 , H01J2237/1506
摘要： An automatic method is provided to align a semiconductor crystalline substrate for electron channeling contrast imaging (ECCI) in regions where an electron channeling pattern cannot be reliably obtained but crystalline defects need to be imaged. The automatic semiconductor crystalline substrate alignment method is more reproducible and faster than the current operator intensive process for ECCI alignment routines. Also, the automatic semiconductor crystalline substrate alignment method increases the throughput of ECCI.

4. 发明申请

US20170117361A1 STACKED STRAINED AND STRAIN-RELAXED HEXAGONAL NANOWIRES 有权
公开(公告)号：US20170117361A1
公开(公告)日：2017-04-27
申请号：US15249560
申请日：2016-08-29
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Takashi Ando , Pouya Hashemi , John A. Ott , Alexander Reznicek
IPC分类号： H01L29/06 , H01L29/78 , H01L29/04 , H01L29/10 , H01L29/16
CPC分类号： H01L29/0673 , B82Y10/00 , H01L21/02164 , H01L21/02236 , H01L21/02532 , H01L21/02603 , H01L21/02609 , H01L21/30604 , H01L21/308 , H01L21/823431 , H01L21/823807 , H01L21/823821 , H01L21/8256 , H01L27/0886 , H01L27/092 , H01L27/0922 , H01L27/0924 , H01L29/045 , H01L29/0649 , H01L29/1054 , H01L29/16 , H01L29/42392 , H01L29/66439 , H01L29/775 , H01L29/7842 , H01L29/7843 , H01L29/785 , H01L29/78684 , H01L29/78696
摘要： A method for forming nanowires includes forming a plurality of epitaxial layers on a substrate, the layers including alternating material layers with high and low Ge concentration and patterning the plurality of layers to form fins. The fins are etched to form recesses in low Ge concentration layers to form pillars between high Ge concentration layers. The pillars are converted to dielectric pillars. A conformal material is formed in the recesses and on the dielectric pillars. The high Ge concentration layers are condensed to form hexagonal Ge wires with (111) facets. The (111) facets are exposed to form nanowires.

5. 发明授权

US09530643B2 Selective epitaxy using epitaxy-prevention layers 有权
标题翻译：选择性外延使用外延防止层
公开(公告)号：US09530643B2
公开(公告)日：2016-12-27
申请号：US14645894
申请日：2015-03-12
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Cheng-Wei Cheng , Jeehwan Kim , John A. Ott , Devendra K. Sadana
IPC分类号： H01L21/20 , H01L21/02 , H01L21/308
CPC分类号： H01L21/0274 , H01L21/02378 , H01L21/02444 , H01L21/02485 , H01L21/02527 , H01L21/0254 , H01L21/02612 , H01L21/02639 , H01L21/02642 , H01L21/308
摘要： A method for forming an epitaxial structure includes providing a two-dimensional material on a crystal semiconductor material and opening up portions of the two-dimensional material to expose the crystal semiconductor material. A structure is epitaxially grown in the portions opened up in the crystal semiconductor material such that the epitaxial growth is selective to the exposed crystal semiconductor material relative to the two-dimensional material.
摘要翻译：一种用于形成外延结构的方法包括在晶体半导体材料上提供二维材料并打开二维材料的部分以露出晶体半导体材料。在晶体半导体材料中开放的部分中外延生长结构，使得外延生长对于暴露的晶体半导体材料相对于二维材料是选择性的。

6. 发明申请

US20160276483A1 FORMATION OF FINFET JUNCTION 有权
标题翻译：形成FINFET结
公开(公告)号：US20160276483A1
公开(公告)日：2016-09-22
申请号：US15166665
申请日：2016-05-27
申请人： International Business Machines Corporation
发明人： Kevin K. Chan , Pouya Hashemi , Ali Khakifirooz , John A. Ott , Alexander Reznicek
IPC分类号： H01L29/78 , H01L29/66 , H01L29/167 , H01L29/165
CPC分类号： H01L29/7851 , H01L21/324 , H01L21/845 , H01L27/0924 , H01L29/1033 , H01L29/161 , H01L29/165 , H01L29/167 , H01L29/66545 , H01L29/66795 , H01L29/7848 , H01L29/785
摘要： A finFET structure, and method of forming such structure, in which a germanium enriched nanowire is located in the channel region of the FET, while simultaneously having silicon-germanium fin in the source/drain region of the finFET.
摘要翻译：一种finFET结构，以及形成这种结构的方法，其中富含锗的纳米线位于FET的沟道区域中，同时在finFET的源极/漏极区域同时具有硅 - 锗鳍。

7. 发明申请

US20160268128A1 SELECTIVE EPITAXY USING EPITAXY-PREVENTION LAYERS 有权
标题翻译：选择性外源使用外源性预防层
公开(公告)号：US20160268128A1
公开(公告)日：2016-09-15
申请号：US14645894
申请日：2015-03-12
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Cheng-Wei Cheng , Jeehwan Kim , John A. Ott , Devendra K. Sadana
IPC分类号： H01L21/02 , H01L21/308
CPC分类号： H01L21/0274 , H01L21/02378 , H01L21/02444 , H01L21/02485 , H01L21/02527 , H01L21/0254 , H01L21/02612 , H01L21/02639 , H01L21/02642 , H01L21/308
摘要： A method for forming an epitaxial structure includes providing a two-dimensional material on a crystal semiconductor material and opening up portions of the two-dimensional material to expose the crystal semiconductor material. A structure is epitaxially grown in the portions opened up in the crystal semiconductor material such that the epitaxial growth is selective to the exposed crystal semiconductor material relative to the two-dimensional material.
摘要翻译：一种用于形成外延结构的方法包括在晶体半导体材料上提供二维材料并打开二维材料的部分以露出晶体半导体材料。在晶体半导体材料中开放的部分中外延生长结构，使得外延生长对于暴露的晶体半导体材料相对于二维材料是选择性的。

8. 发明授权

US09406529B1 Formation of FinFET junction 有权
标题翻译： FinFET结的形成
公开(公告)号：US09406529B1
公开(公告)日：2016-08-02
申请号：US14639163
申请日：2015-03-05
申请人： International Business Machines Corporation
发明人： Kevin K. Chan , Pouya Hashemi , Ali Khakifirooz , John A. Ott , Alexander Reznicek
IPC分类号： H01L29/78 , H01L29/772 , H01L27/088 , H01L21/324 , H01L29/66 , H01L29/161 , H01L29/167 , H01L29/10 , H01L21/84 , H01L27/092
CPC分类号： H01L29/7851 , H01L21/324 , H01L21/845 , H01L27/0924 , H01L29/1033 , H01L29/161 , H01L29/165 , H01L29/167 , H01L29/66545 , H01L29/66795 , H01L29/7848 , H01L29/785
摘要： A finFET structure, and method of forming such structure, in which a germanium enriched nanowire is located in the channel region of the FET, while simultaneously having silicon-germanium fin in the source/drain region of the finFET.
摘要翻译：一种finFET结构，以及形成这种结构的方法，其中富含锗的纳米线位于FET的沟道区域中，同时在finFET的源极/漏极区域同时具有硅 - 锗鳍。

9. 发明授权

US09000594B2 Use of graphene to limit copper surface oxidation, diffusion and electromigration in interconnect structures 有权
标题翻译：使用石墨烯来限制互连结构中的铜表面氧化，扩散和电迁移
公开(公告)号：US09000594B2
公开(公告)日：2015-04-07
申请号：US14107100
申请日：2013-12-16
申请人： International Business Machines Corporation
发明人： John A. Ott , Ageeth A. Bol
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40 , H01L23/522 , H01L23/532
CPC分类号： H01L23/52 , H01L21/7682 , H01L21/76852 , H01L21/76885 , H01L23/5222 , H01L23/53238 , H01L23/53276 , H01L23/5329 , H01L23/53295 , H01L2924/0002 , H01L2924/0001 , H01L2924/00
摘要： A contiguous layer of graphene is formed on exposed sidewall surfaces and a topmost surface of a copper-containing structure that is present on a surface of a substrate. The presence of the contiguous layer of graphene on the copper-containing structure reduces copper oxidation and surface diffusion of copper ions and thus improves the electromigration resistance of the structure. These benefits can be obtained using graphene without increasing the resistance of copper-containing structure.
摘要翻译：邻近的石墨烯层形成在暴露的侧壁表面和存在于基底表面上的含铜结构的最上表面。在含铜结构上存在连续的石墨烯层可以减少铜离子的铜氧化和表面扩散，从而提高结构的电迁移能力。这些益处可以使用石墨烯获得，而不增加含铜结构的电阻。

10. 发明授权

US08809164B2 Method of large-area circuit layout recognition 有权
标题翻译：大面积电路布局识别方法
公开(公告)号：US08809164B2
公开(公告)日：2014-08-19
申请号：US14021527
申请日：2013-09-09
申请人： International Business Machines Corporation
发明人： Stephen W. Bedell , Bahman Hekmatshoartabari , Ali Khakifirooz , John A. Ott , Ghavam G. Shahidi , Davood Shahrjerdi
IPC分类号： H01L21/304
CPC分类号： H01L22/12 , H01L21/304 , H01L21/7806 , H01L21/7813
摘要： Methods for detecting the physical layout of an integrated circuit are provided. The methods of the present disclosure allow large area imaging of the circuit layout without requiring tedious sample preparation techniques. The imaging can be performed utilizing low-energy beam techniques such as scanning electron microscopy; however, more sophisticated imaging techniques can also be employed. In the methods of the present disclosure, spalling is used to remove a portion of a semiconductor layer including at least one semiconductor device formed thereon or therein from a base substrate. In some cases, a buried insulator layer that is located beneath a semiconductor layer including the at least one semiconductor device can be completely or partially removed. In some cases, the semiconductor layer including the at least one semiconductor device can be thinned. The methods improve the detection quality that the buried insulator layer and a thick semiconductor layer can reduce.
摘要翻译：提供了用于检测集成电路的物理布局的方法。本公开的方法允许电路布局的大面积成像，而不需要繁琐的样品制备技术。可以使用诸如扫描电子显微镜的低能束技术进行成像; 然而，也可以采用更复杂的成像技术。在本公开的方法中，剥离用于从基底衬底去除包括形成在其上或其中的至少一个半导体器件的半导体层的一部分。在一些情况下，可以完全或部分地去除位于包括至少一个半导体器件的半导体层下方的掩埋绝缘体层。在一些情况下，可以使包括至少一个半导体器件的半导体层变薄。该方法提高了掩埋绝缘体层和厚半导体层可以降低的检测质量。

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