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1. 发明申请

US20160147530A1 STRUCTURE FOR MICROPROCESSOR ARITHMETIC LOGIC UNITS 审中-公开
标题翻译：微处理器算术逻辑单元结构
公开(公告)号：US20160147530A1
公开(公告)日：2016-05-26
申请号：US14554194
申请日：2014-11-26
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Avraham Ayzenfeld , Lee E. Eisen , Brian W. Curran , Christian Jacobi
IPC分类号： G06F9/30
摘要： Examples of techniques for designing processors are described herein. In one example, a design structure can be tangibly embodied in a machine readable medium for designing, manufacturing, or testing an integrated circuit. The design structure can include a logic to determine whether a received instruction is an updating fixed point instruction or a non-updating fixed point instruction. The design structure can include a first arithmetic logic unit (ALU) to execute the received instruction if the received instruction is determined to be an updating fixed point instruction and store an update value in a general register. The design structure can include a second arithmetic logic unit (ALU) to execute the received instruction if the received instruction is determined to be a non-updating fixed point instruction.
摘要翻译：这里描述了用于设计处理器的技术的示例。在一个示例中，设计结构可以有形地体现在用于设计，制造或测试集成电路的机器可读介质中。设计结构可以包括确定接收到的指令是更新固定点指令还是非更新定点指令的逻辑。如果接收到的指令被确定为更新固定点指令并且将更新值存储在通用寄存器中，则设计结构可以包括用于执行接收到的指令的第一算术逻辑单元（ALU）。如果接收到的指令被确定为不更新定点指令，则设计结构可以包括第二算术逻辑单元（ALU），以执行接收到的指令。

2. 发明授权

US10678549B2 Executing processor instructions using minimal dependency queue 有权
公开(公告)号：US10678549B2
公开(公告)日：2020-06-09
申请号：US15823632
申请日：2017-11-28
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Avraham Ayzenfeld , Eyal Naor , Amir Turi
IPC分类号： G06F9/30 , G06F9/312 , G06F9/38
摘要： Examples of techniques for executing instructions out of order are described herein. An example computer-implemented method includes receiving, via a processor, a plurality of instructions to be executed. The method includes sending, via the processor, an instruction to a minimal dependency queue in response to detecting the instruction includes a minimally dependent instruction. The method also includes selecting, via the processor, an instruction from a set of instructions that are eligible to be executed based on a scheme. The method further includes executing, via the processor, the instruction.

3. 发明申请

US20140201419A1 EXECUTING VIRTUAL FUNCTIONS USING MEMORY-BASED DATA IN A PCI EXPRESS SR-IOV AND MR-IOV ENVIRONMENT 有权
标题翻译：在PCI EXPRESS SR-IOV和MR-IOV环境中使用基于存储器的数据执行虚拟功能
公开(公告)号：US20140201419A1
公开(公告)日：2014-07-17
申请号：US14212444
申请日：2014-03-14
申请人： International Business Machines Corporation
发明人： Avraham Ayzenfeld , Emmanuel Elder , Ilya Granovsky
IPC分类号： G06F13/20
CPC分类号： G06F13/20 , G06F9/48 , G06F12/08 , G06F13/105 , G06F13/14 , G06F13/16
摘要： A method, including receiving, by an extended virtual function shell positioned on a Peripheral Component Interconnect Express (PCIe) configuration space, a virtual function call comprising a request to perform a specific computation, and identifying a physical function associated with the called virtual function, the physical function one of multiple physical functions positioned on the PCIe configuration space. One or more first data values are then retrieved from a virtual function instance stored in the memory, one or more first data values, the virtual function instance associated with the called virtual function, and one or more second data values are retrieved from the identified physical function. The specific computation is then performed using the first data values and the second data values, thereby calculating a result.
摘要翻译：一种方法，包括通过位于外围组件互连Express（PCIe）配置空间上的扩展虚拟功能外壳来接收包括执行特定计算的请求以及识别与被叫虚拟功能相关联的物理功能的虚拟功能调用，物理功能位于PCIe配置空间的多个物理功能之一。然后从存储在存储器中的虚拟功能实例中检索一个或多个第一数据值，一个或多个第一数据值，与被叫虚拟功能关联的虚拟功能实例以及一个或多个第二数据值从所识别的物理功能。然后使用第一数据值和第二数据值执行特定的计算，由此计算结果。

4. 发明授权

US11379228B2 Microprocessor including an efficiency logic unit 有权
公开(公告)号：US11379228B2
公开(公告)日：2022-07-05
申请号：US16654857
申请日：2019-10-16
申请人： International Business Machines Corporation
发明人： Avraham Ayzenfeld , Lee E. Eisen , Brian W. Curran , Christian Jacobi
IPC分类号： G06F9/30 , G06F9/38 , G06F30/30 , G06F115/10
摘要： An example design structure tangibly embodied in a machine readable medium includes a first arithmetic logic unit (ALU) to perform fixed point instructions using at least two general registers to read data from a first and second general register of a plurality of general registers and write a result in at least a third general register of the plurality of general registers. The design structure includes a second ALU to perform non-updating fixed point instructions using at least two general registers to only read data from the general registers. The design structure includes an efficiency logic unit coupled to the first ALU and the second ALU. The efficiency logic unit is to receive an instruction and determine whether the received instruction is an updating fixed point instruction or a non-updating fixed point instruction based on a number of general registers to be used to execute the received instruction.

5. 发明授权

US11144367B2 Write power optimization for hardware employing pipe-based duplicate register files 有权
公开(公告)号：US11144367B2
公开(公告)日：2021-10-12
申请号：US16270632
申请日：2019-02-08
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Richard Joseph Branciforte , Gregory William Alexander , Avraham Ayzenfeld , Edward Thomas Malley , Jonathan Ting Hsieh , Gregory Miaskovsky
IPC分类号： G06F9/00 , G06F9/52 , G06F9/38 , G06F9/30
摘要： Methods and systems for controlling writing to register files in a processing system having at least two execution pipelines are provided. Aspects include obtaining a micro operation for execution by an execution unit of a first pipeline in the processing system, wherein the micro operation includes writing data to a register file. Aspects also include determining whether the data will be accessed by an execution unit of a second pipeline in the processing system. Based on a determination that the data will only be accessed by the execution unit of the first pipeline, aspects include blocking writing of the data to a register file of the second pipeline.

6. 发明授权

US10503503B2 Generating design structure for microprocessor with arithmetic logic units and an efficiency logic unit 有权
公开(公告)号：US10503503B2
公开(公告)日：2019-12-10
申请号：US14865555
申请日：2015-09-25
申请人： International Business Machines Corporation
发明人： Avraham Ayzenfeld , Lee E. Eisen , Brian W. Curran , Christian Jacobi
IPC分类号： G06F9/30 , G06F9/38 , G06F17/50
CPC分类号： G06F9/3001 , G06F9/30141 , G06F9/3824 , G06F9/3836 , G06F17/5045 , G06F2217/68
摘要： A method in a computer-aided design system for generating a functional design model of a processor, is described herein. The method comprises generating a functional representation of logic to determine whether an instruction is an updating instruction or a non-updating instruction. The method further comprises generating a functional representation of a first arithmetic logic unit (ALU) coupled to a general register in the processor, the first ALU to execute the instruction if the instruction is an updating instruction and store an update value in the general register, and generating a functional representation of a second ALU in the processor to execute the instruction if the instruction is a non-updating instruction.

7. 发明授权

US11916802B2 Data transmission flow control regime 有权
公开(公告)号：US11916802B2
公开(公告)日：2024-02-27
申请号：US17709512
申请日：2022-03-31
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Giora Biran , Amit Shay , Avraham Ayzenfeld
IPC分类号： H04L47/10
CPC分类号： H04L47/39
摘要： A credit-based flow control system can utilize speculative credit. If an agent has not received a credit return from a downstream agent for a given period of time, the agent can return speculative credit to an upstream agent. This way, even if the agent is not currently capable of performing operations represented by the speculative credit, the upstream agent can be enabled to proceed with operations.

8. 发明公开

US20230273824A1 ESTABLISHING COHERENT MESSAGE ANALYSIS ACROSS DISTRIBUTED LOCATIONS 审中-公开
公开(公告)号：US20230273824A1
公开(公告)日：2023-08-31
申请号：US17682996
申请日：2022-02-28
申请人： International Business Machines Corporation
发明人： Giora Biran , Amit Shay , Avraham Ayzenfeld
IPC分类号： G06F9/50
CPC分类号： G06F9/5022 , G06F2209/5011 , G06F2209/503
摘要： A computer-implemented method, according to one approach, is for establishing coherent analysis across distributed locations. The computer-implemented method includes: processing messages at an initiator location. In response to detecting a query indicator set on one of the messages: an inspection resource is allocated from a pool of available inspection resources to collect initial information associated with the processing of the message having the set query indicator. Moreover, the message is sent to a receiver location with the set query indicator for processing and collecting supplemental information associated with the processing of the message at the receiver location. The initial and supplemental information is eventually collected, and the collected information is processed for determining performance characteristics of the processing of the message at the initiator and receiver locations.

9. 发明授权

US11474821B1 Processor dependency-aware instruction execution 有权
公开(公告)号：US11474821B1
公开(公告)日：2022-10-18
申请号：US17318252
申请日：2021-05-12
申请人： International Business Machines Corporation
发明人： Amir Turi , Avraham Ayzenfeld , Gilad Shimon Merran , Yanai Danan , Amit Shay , Yossi Shapira , Yair Fried , Oren Ben Gigi , Omri Rafaeli
IPC分类号： G06F9/38
摘要： In an approach to processor dependency-aware instruction execution, responsive to a new instruction being issued to an instruction issue queue in a processor, a future dependency count is incremented for each instruction of a plurality of instructions in the instruction issue queue that has a dependency on the new instruction. The plurality of instructions in the instruction issue queue are prioritized based on the future dependency count. The highest priority instruction of the plurality of instructions in the instruction issue queue is issued.

10. 发明申请

US20190310856A1 EXECUTING INSTRUCTIONS BASED ON A SHARED PHYSICAL REGISTER 审中-公开
公开(公告)号：US20190310856A1
公开(公告)日：2019-10-10
申请号：US15948220
申请日：2018-04-09
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Avraham Ayzenfeld , AMIR TURI , EYAL NAOR , Ido Rozenberg
IPC分类号： G06F9/38 , G06F9/30
摘要： Embodiments of the present invention disclose a method, a computer program product, and a computer system for system for executing instructions, comprising a processor to detect a pair of destructive instructions within a predetermined number of instructions, wherein each instruction from the pair of destructive instructions assigns a value to be stored in a shared target logical register. In addition, the processor can also execute the pair of destructive instructions in an order received, wherein a result of each instruction of the pair of destructive instructions is mapped to a shared physical register. Furthermore, the processor can execute additional instructions based on the result of the pair of destructive instructions stored in the shared physical register.

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