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1. 发明授权

US11557789B2 Solid electrolyte, electrode, power storage device, and method for producing solid electrolytes 有权
公开(公告)号：US11557789B2
公开(公告)日：2023-01-17
申请号：US16481782
申请日：2018-10-31
申请人： IMEC VZW , KATHOLIEKE UNIVERSITEIT LEUVEN , PANASONIC CORPORATION
发明人： Xubin Chen , Philippe Vereecken , Maarten Mees , Knut Bjarne Gandrud , Mitsuhiro Murata , Akihiko Sagara , Yukihiro Kaneko , Morio Tomiyama , Mikinari Shimada
IPC分类号： H01M10/0562 , H01M10/0525 , H01M4/62
摘要： A solid electrolyte (10) of the present disclosure includes porous silica (11) having a plurality of pores (12) interconnected mutually and an electrolyte (13) coating inner surfaces of the plurality of pores (12). The electrolyte (13) includes 1-ethyl-3-methylimidazolium bis(fluorosulfonyl)imide represented by EMI-FSI and a lithium salt dissolved in the EMI-FSI. A molar ratio of the EMI-FSI to the porous silica (11) is larger than 1.0 and less than 3.5.

2. 发明授权

US11710850B2 Solid electrolyte, electrode, power storage device, and method for producing solid electrolytes 有权
公开(公告)号：US11710850B2
公开(公告)日：2023-07-25
申请号：US16481814
申请日：2018-10-31
申请人： IMEC VZW , PANASONIC CORPORATION
发明人： Philippe Vereecken , Maarten Mees , Knut Bjarne Gandrud , Akihiko Sagara , Mitsuhiro Murata , Yukihiro Kaneko , Morio Tomiyama , Mikinari Shimada
IPC分类号： H01M10/0562 , H01M4/13 , H01M4/62 , H01M10/052 , H01M10/056 , H01B1/12
CPC分类号： H01M10/0562 , H01B1/12 , H01M4/13 , H01M4/62 , H01M10/052 , H01M10/056 , H01M2300/0068
摘要： A solid electrolyte (10) of the present disclosure includes porous silica (11) having a plurality of pores (12) interconnected mutually and an electrolyte (13) coating inner surfaces of the plurality of pores (12). The electrolyte (13) includes 1-ethyl-3-methylimidazolium bis(trifluoromethanesulfonyl)imide represented by EMI-TFSI and a lithium salt dissolved in the EMI-TFSI. A molar ratio of the EMI-TFSI to the porous silica (11) is larger than 1.5 and less than 2.0.

3. 发明授权

US08775346B2 Learning method of neural network circuit 有权
标题翻译：神经网络电路学习方法
公开(公告)号：US08775346B2
公开(公告)日：2014-07-08
申请号：US13951443
申请日：2013-07-25
申请人： Panasonic Corporation
发明人： Yu Nishitani , Yukihiro Kaneko , Michihito Ueda
IPC分类号： G06N3/063
CPC分类号： G06N3/063 , G06N3/04 , G06N3/049
摘要： A neuron circuit in a neural network circuit element includes a waveform generating circuit for generating a bipolar sawtooth pulse voltage, and a first input signal has a bipolar sawtooth pulse waveform. For a period during which the first input signal is permitted to be input to a first electrode of a variable resistance element, the bipolar sawtooth pulse voltage generated within the neural network circuit element including the variable resistance element which is applied with the first input signal from another neural network circuit element is input to a control electrode of the variable resistance element. The resistance value of the variable resistance element changes due to an electric potential difference between the first electrode and the control electrode, the electric potential difference being generated depending on an input timing difference between a voltage applied to the first electrode and the voltage applied to the control electrode.
摘要翻译：神经网络电路元件中的神经元电路包括用于产生双极锯齿波脉冲电压的波形发生电路，第一输入信号具有双极锯齿波脉冲波形。在第一输入信号被允许输入到可变电阻元件的第一电极的期间，在包括可变电阻元件的神经网络电路元件内产生的双极锯齿波脉冲电压被施加来自另一个神经网络电路元件被输入到可变电阻元件的控制电极。可变电阻元件的电阻值由于第一电极和控制电极之间的电位差而变化，电位差根据施加到第一电极的电压与施加到第一电极的电压之间的输入定时差而产生控制电极。

4. 发明授权

US08724368B2 Method for driving semiconductor memory device 有权
标题翻译：驱动半导体存储器件的方法
公开(公告)号：US08724368B2
公开(公告)日：2014-05-13
申请号：US13692587
申请日：2012-12-03
申请人： Panasonic Corporation
发明人： Yukihiro Kaneko
IPC分类号： G11C11/22
CPC分类号： G11C11/223 , G11C11/221 , H01L27/1159 , H01L27/11597 , H01L29/6684 , H01L29/78391 , H01L29/78648
摘要： A semiconductor device includes first to fourth memory cells and each memory cell includes a first gate electrode, a ferroelectric film, a semiconductor film, a source electrode, a drain electrode, a paraelectric film and a second gate electrode. The ferroelectric film is interposed between the first gate electrode and the semiconductor film, the source electrode and the drain electrode are interposed between the semiconductor film and the paraelectric film. The first gate electrode, the ferroelectric film, the source electrode, and the drain electrode constitute a first semiconductor transistor. The second gate electrode, the paraelectric film, the source electrode, and the drain electrode constitute a second semiconductor transistor.
摘要翻译：半导体器件包括第一至第四存储单元，并且每个存储单元包括第一栅电极，铁电体膜，半导体膜，源电极，漏极，顺电膜和第二栅电极。铁电体膜介于第一栅电极和半导体膜之间，源电极和漏电极介于半导体膜和副电介质膜之间。第一栅电极，铁电体膜，源极电极和漏电极构成第一半导体晶体管。第二栅电极，顺电膜，源电极和漏电极构成第二半导体晶体管。

5. 发明授权

US09036394B2 Method of driving nonvolatile semiconductor device 有权
标题翻译：驱动非易失性半导体器件的方法
公开(公告)号：US09036394B2
公开(公告)日：2015-05-19
申请号：US14143544
申请日：2013-12-30
申请人： Panasonic Corporation
发明人： Yukihiro Kaneko
IPC分类号： G11C13/00 , H03K19/21 , H01L21/28 , H01L29/66 , H01L27/115 , G11C11/22 , H01L29/78
CPC分类号： G11C13/0069 , G11C5/025 , G11C11/2259 , G11C11/2275 , H01L21/28291 , H01L27/1159 , H01L29/6684 , H01L29/78391 , H03K19/21
摘要： Pulse voltages V1 and V2 are applied to a first upper gate electrode and a second upper gate electrode, respectively, for a period T1 which is shorter than a period necessary to invert all the polarizations included in a ferroelectric film, while voltages Vs, Vd, and V3 are applied to a source electrode, a drain electrode, and a lower gate electrode film, respectively, so as to increase the values of the widths WRL1 and WRL2 and so as to decrease the value of the width WRH. The absolute values of the pulse voltages V1 and V2 are smaller than that of a voltage necessary to invert all the polarizations included in the ferroelectric film. The voltage Vs, the voltage Vd, the voltage V3, the pulse voltage V1, and the pulse voltage V2 satisfy the following relationship: Vs, Vd, V3>V1, V2.
摘要翻译：脉冲电压V1和V2分别施加到第一上栅极电极和第二上栅极电极，周期T1短于反转铁电体中包含的所有极化所需的周期，同时电压Vs，Vd，和V3分别施加到源电极，漏电极和下栅电极膜，以便增加宽度WRL1和WRL2的值，并且减小宽度WRH的值。脉冲电压V1和V2的绝对值小于反转包含在铁电体膜中的所有极化所需的电压的绝对值。电压Vs，电压Vd，电压V3，脉冲电压V1，脉冲电压V2满足Vs，Vd，V3> V1，V2的关系。

6. 发明授权

US08965821B2 Learning method of neural network circuit 有权
标题翻译：神经网络电路学习方法
公开(公告)号：US08965821B2
公开(公告)日：2015-02-24
申请号：US13951448
申请日：2013-07-25
申请人： Panasonic Corporation
发明人： Yu Nishitani , Yukihiro Kaneko , Michihito Ueda
IPC分类号： G06N3/08 , G06N3/04 , G06N3/063
CPC分类号： G06N3/08 , G06N3/049 , G06N3/0635
摘要： A neuron circuit in a neural network circuit element includes a waveform generating circuit for generating a predetermined pulse voltage, and a first input signal has a waveform of the predetermined pulse voltage. For a period having a predetermined duration of the predetermined pulse voltage generated within the neural network circuit element including the variable resistance element which is applied with the first input signal from another neural network circuit element, the first input signal is permitted to be input to the control electrode of the variable resistance element, to change the resistance value of the variable resistance element due to an electric potential difference generated between the first electrode and the control electrode which occurs depending on an input timing of the first input signal with respect to the period during which the first input signal is permitted to be input to the control electrode.
摘要翻译：神经网络电路元件中的神经元电路包括用于产生预定脉冲电压的波形发生电路，并且第一输入信号具有预定脉冲电压的波形。在包含施加了来自另一神经网络电路元件的第一输入信号的可变电阻元件的神经网络电路元件内产生的预定脉冲电压的预定持续时间的期间，允许第一输入信号输入到可变电阻元件的控制电极，用于根据第一输入信号的输入定时相对于周期来改变由于在第一电极和控制电极之间产生的电位差产生的电位差的可变电阻元件的电阻值第一输入信号被允许输入到控制电极。

7. 发明授权

US08830723B2 Method of driving nonvolatile semiconductor device 有权
标题翻译：驱动非易失性半导体器件的方法
公开(公告)号：US08830723B2
公开(公告)日：2014-09-09
申请号：US14030619
申请日：2013-09-18
申请人： Panasonic Corporation
发明人： Yukihiro Kaneko
IPC分类号： G11C11/22 , G11C11/56 , H01L29/78 , H01L29/51 , H01L21/28 , G11C13/00 , G11C5/02
CPC分类号： G11C11/2275 , G11C5/025 , G11C11/22 , G11C11/5657 , G11C2013/0092 , H01L21/28291 , H01L29/516 , H01L29/78391 , H04L29/12
摘要： Pulse voltages V1 and V2 are applied to the first upper gate electrode and the second upper gate electrode, respectively, for a period T1 which is shorter than a period necessary to invert all the polarizations included in the ferroelectric film, while voltages Vs, Vd, and V3 are applied to the source electrode, the drain electrode, and the lower gate electrode film, respectively, so as to increase the values of the widths WRH1 and WRH2 and so as to decrease the value of the width WRL. The pulse voltages V1 and V2 have a smaller voltage than a voltage necessary to invert all the polarizations included in the ferroelectric film. The voltage Vs, the voltage Vd, the voltage V3, the pulse voltage V1, and the pulse voltage V2 satisfy the following relationship: Vs, Vd, V3
摘要翻译：脉冲电压V1和V2分别施加到第一上栅极电极和第二上栅电极，周期T1短于反转铁电体中包含的所有极化所需的周期，同时电压Vs，Vd，并且V3分别施加到源电极，漏电极和下栅极电极膜，以便增加宽度WRH1和WRH2的值，并且减小宽度WRL的值。脉冲电压V1和V2具有比包含在铁电体膜中的所有极化反转所必需的电压更小的电压。电压Vs，电压Vd，电压V3，脉冲电压V1，脉冲电压V2满足Vs，Vd，V3

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