专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US08957794B2 A/D converter and method for calibrating the same 有权
标题翻译： A / D转换器及其校准方法
公开(公告)号：US08957794B2
公开(公告)日：2015-02-17
申请号：US13767233
申请日：2013-02-14
申请人： IMEC , Renesas Electronics Corporation
发明人： Bob Verbruggen , Masao Iriguchi , Jan Craninckx
IPC分类号： H03M1/06 , H03M1/10 , H03M1/14 , H03M1/46
CPC分类号： H03M1/06 , H03M1/1023 , H03M1/145 , H03M1/466
摘要： An ADC includes sampling means for sampling an input voltage signal, comparator(s) for receiving the sampled signal, and a DAC including circuitry for generating a search signal approximating the input signal and a calibration signal. The search signal and the calibration signal are to be applied to a comparator. The ADC also includes a search logic block for receiving a comparator output signal, for providing input to the DAC for generating the search signal, and for producing a digital output signal. Further, the ADC includes a calibration logic block for producing a control signal to control the circuitry of the DAC and including processing means for observing the output signal, for comparing the output signal with a desired output, and for compensating analog non-idealities of the ADC. The DAC circuitry is adapted for generating the calibration signal in accordance with the control signal and with the sampled input signal.
摘要翻译： ADC包括用于对输入电压信号进行采样的采样装置，用于接收采样信号的比较器，以及包括用于产生近似输入信号的搜索信号和校准信号的电路的DAC。搜索信号和校准信号应用于比较器。 ADC还包括用于接收比较器输出信号的搜索逻辑块，用于向DAC提供用于产生搜索信号的输入，以及用于产生数字输出信号。此外，ADC包括用于产生控制信号以控制DAC的电路的校准逻辑块，并且包括用于观察输出信号的处理装置，用于将输出信号与期望的输出进行比较，并且用于补偿模拟非理想 ADC。 DAC电路适于根据控制信号和采样的输入信号产生校准信号。

2. 发明申请

US20130214947A1 Device, System and Method for Analogue-to-Digital Conversion Using a Current Integrating Circuit 有权
标题翻译：使用电流积分电路进行模数转换的器件，系统和方法
公开(公告)号：US20130214947A1
公开(公告)日：2013-08-22
申请号：US13768811
申请日：2013-02-15
申请人： IMEC , RENESAS ELECTRONICS CORPORATION
发明人： Takaya Yamamoto , Jan Craninckx
IPC分类号： H03M1/38
CPC分类号： H03M1/38 , G11C27/024 , H03M1/0854 , H03M1/129 , H03M1/46
摘要： A device including a sample and hold circuit for providing a signal related to an input analogue current signal, by sampling the input analogue current signal and integrating it on capacitive means, thereby charging the capacitive means to a charge value. The capacitive means being configurable to dynamically change its effective capacitance value in order to shape a voltage signal present on the capacitive means such that the charge value remains unchanged. The device also including an analogue-to digital conversion (ADC) and control circuit arranged for performing an ADC of the at least one related signal at the output of the sample and hold circuit into an output digital signal, the ADC and control circuit including successive approximation ADC means for considering the value of the voltage signal on the capacitive means and converting the charge value present in the capacitive means into the digital output signal.
摘要翻译：一种包括用于提供与输入模拟电流信号相关的信号的采样和保持电路的装置，通过对输入的模拟电流信号进行采样并将其积分在电容性装置上，从而将电容装置充电到电荷值。电容性装置被配置为动态地改变其有效电容值，以形成存在于电容装置上的电压信号，使得电荷值保持不变。该装置还包括模数转换（ADC）和控制电路，其被布置为在采样和保持电路的输出处执行至少一个相关信号的ADC作为输出数字信号，该ADC和控制电路包括连续的近似ADC用于考虑电容装置上的电压信号的值并将存在于电容装置中的电荷值转换为数字输出信号。

3. 发明申请

US20130214946A1 A/D Converter and Method for Calibrating the Same 有权
标题翻译： A / D转换器及其校准方法
公开(公告)号：US20130214946A1
公开(公告)日：2013-08-22
申请号：US13767233
申请日：2013-02-14
申请人： IMEC , Renesas Electronics Corporation
发明人： Bob Verbruggen , Masao Iriguchi , Jan Craninckx
IPC分类号： H03M1/06
CPC分类号： H03M1/06 , H03M1/1023 , H03M1/145 , H03M1/466
摘要： An ADC includes sampling means for sampling an input voltage signal, comparator(s) for receiving the sampled signal, and a DAC including circuitry for generating a search signal approximating the input signal and a calibration signal. The search signal and the calibration signal are to be applied to a comparator. The ADC also includes a search logic block for receiving a comparator output signal, for providing input to the DAC for generating the search signal, and for producing a digital output signal. Further, the ADC includes a calibration logic block for producing a control signal to control the circuitry of the DAC and including processing means for observing the output signal, for comparing the output signal with a desired output, and for compensating analogue non-idealities of the ADC. The DAC circuitry is adapted for generating the calibration signal in accordance with the control signal and with the sampled input signal.
摘要翻译： ADC包括用于对输入电压信号进行采样的采样装置，用于接收采样信号的比较器，以及包括用于产生近似输入信号的搜索信号和校准信号的电路的DAC。搜索信号和校准信号应用于比较器。 ADC还包括用于接收比较器输出信号的搜索逻辑块，用于向DAC提供用于产生搜索信号的输入，以及用于产生数字输出信号。此外，ADC包括用于产生控制信号以控制DAC的电路的校准逻辑块，并且包括用于观察输出信号的处理装置，用于将输出信号与期望的输出进行比较，并且用于补偿模拟非理想 ADC。 DAC电路适于根据控制信号和采样的输入信号产生校准信号。

4. 发明授权

US08890733B2 Device, system and method for analogue-to-digital conversion using a current integrating circuit 有权
标题翻译：使用电流积分电路进行模数转换的装置，系统和方法
公开(公告)号：US08890733B2
公开(公告)日：2014-11-18
申请号：US13768811
申请日：2013-02-15
申请人： IMEC , Renesas Electronics Corporation
发明人： Takaya Yamamoto , Jan Craninckx
IPC分类号： H03M1/12 , G11C27/02 , H03M1/38 , H03M1/08 , H03M1/46
CPC分类号： H03M1/38 , G11C27/024 , H03M1/0854 , H03M1/129 , H03M1/46
摘要： A device including a sample and hold circuit for providing a signal related to an input analogue current signal, by sampling the input analogue current signal and integrating it on capacitive means, thereby charging the capacitive means to a charge value. The capacitive means being configurable to dynamically change its effective capacitance value in order to shape a voltage signal present on the capacitive means such that the charge value remains unchanged. The device also including an analogue-to digital conversion (ADC) and control circuit arranged for performing an ADC of the at least one related signal at the output of the sample and hold circuit into an output digital signal, the ADC and control circuit including successive approximation ADC means for considering the value of the voltage signal on the capacitive means and converting the charge value present in the capacitive means into the digital output signal.
摘要翻译：一种包括用于提供与输入模拟电流信号相关的信号的采样和保持电路的装置，通过对输入的模拟电流信号进行采样并将其积分在电容性装置上，从而将电容装置充电到电荷值。电容性装置被配置为动态地改变其有效电容值，以形成存在于电容装置上的电压信号，使得电荷值保持不变。该装置还包括模数转换（ADC）和控制电路，其被布置为在采样和保持电路的输出处执行至少一个相关信号的ADC作为输出数字信号，该ADC和控制电路包括连续的近似ADC用于考虑电容装置上的电压信号的值并将存在于电容装置中的电荷值转换为数字输出信号。

5. 发明授权

US10200047B2 DTC-based PLL and method for operating the DTC-based PLL 有权
公开(公告)号：US10200047B2
公开(公告)日：2019-02-05
申请号：US15605261
申请日：2017-05-25
申请人： IMEC VZW , Stichting IMEC Nederland , Vrije Universiteit Brussel
发明人： Nereo Markulic , Yao-Hong Liu , Jan Craninckx
IPC分类号： H03L7/06 , H03L7/085 , H03K5/159 , H03L7/099 , H03L7/081 , H03L7/197 , H03K5/00
摘要： The disclosure provides a phase locked loop, PLL, for phase locking an output signal to a reference signal. The PLL comprises a reference path providing the reference signal to a first input of a phase detector, a feedback loop providing the output signal of the PLL as a feedback signal to a second input of the phase detector, a controllable oscillator generating the output signal based on at least a phase difference between reference and feedback signal, a digital-to-time converter, DTC, delaying a signal that is provided at one of the first and second input, a delay calculation path for calculating a DTC delay value. The PLL further comprises a randomization unit for generating and adding a random offset, i.e. a pseudo-random integer, to the delay value. The offset is such that a target output of the phase detector remains substantially unchanged.

6. 发明申请

US20170346493A1 DTC-Based PLL and Method for Operating the DTC-Based PLL 审中-公开
公开(公告)号：US20170346493A1
公开(公告)日：2017-11-30
申请号：US15605261
申请日：2017-05-25
申请人： IMEC VZW , Stichting IMEC Nederland , Vrije Universiteit Brussel
发明人： Nereo Markulic , Yao-Hong Liu , Jan Craninckx
IPC分类号： H03L7/085 , H03K5/159 , H03L7/099 , H03K5/00
CPC分类号： H03L7/085 , H03K5/159 , H03K2005/00013 , H03L7/081 , H03L7/0991 , H03L7/197 , H03L7/1976 , H03L2207/50
摘要： The disclosure provides a phase locked loop, PLL, for phase locking an output signal to a reference signal. The PLL comprises a reference path providing the reference signal to a first input of a phase detector, a feedback loop providing the output signal of the PLL as a feedback signal to a second input of the phase detector, a controllable oscillator generating the output signal based on at least a phase difference between reference and feedback signal, a digital-to-time converter, DTC, delaying a signal that is provided at one of the first and second input, a delay calculation path for calculating a DTC delay value. The PLL further comprises a randomization unit for generating and adding a random offset, i.e. a pseudo-random integer, to the delay value. The offset is such that a target output of the phase detector remains substantially unchanged.

7. 发明申请

US20210344349A1 Advanced Successive Approximation Register Analog-To-Digital Converter and Corresponding Method 有权
公开(公告)号：US20210344349A1
公开(公告)日：2021-11-04
申请号：US17221166
申请日：2021-04-02
申请人： Imec vzw
发明人： Ewout Martens , Davide Dermit , Jan Craninckx
IPC分类号： H03M1/06
摘要： An successive approximation register analog-to-digital converter is provided. The successive approximation register analog-to-digital converter includes a digital-to-analog converter, a successive approximation register, a comparator, and a threshold voltage determining unit. In this context, the threshold voltage determining unit is configured to dynamically determine the threshold voltage of the comparator on the basis of the input signal of the digital-to-analog converter or the output signal of the comparator.

8. 发明授权

US11128326B2 Digital radio frequency circuitry 有权
公开(公告)号：US11128326B2
公开(公告)日：2021-09-21
申请号：US17098178
申请日：2020-11-13
申请人： IMEC vzw , Vrije Universiteit Brussel
发明人： Johan Nguyen , Khaled Khalaf , Pierre Wambacq , Jan Craninckx
IPC分类号： H04B1/04 , H03F3/193 , H03F3/72 , H03G3/00 , H03G1/00
摘要： A digital radio-frequency (RF) circuitry is disclosed. In one aspect, the circuitry includes a digitally controlled amplifier configured to receive an RF input signal and a digital control signal, and to output an amplitude controlled output signal. The digitally controlled amplifier includes one or more common-source amplifying unit cells. A respective common-source amplifying unit cell includes a sources node connected to a switching circuitry controllable by the digital control signal so as to activate or deactivate the common-source amplifying unit cell. The switching circuitry comprises a first switch configured to connect the source node with a first power supply node and a second switch configured to connect the source node with a second power supply node when activating and deactivating, respectively, the common-source amplifying unit cell.

9. 发明授权

US10230347B2 Telecommunications device comprising an EBD circuit, a tunable impedance network and a method for tuning a tunable impedance network 有权
公开(公告)号：US10230347B2
公开(公告)日：2019-03-12
申请号：US15217927
申请日：2016-07-22
申请人： IMEC VZW , VRIJE UNIVERSITEIT BRUSSEL
发明人： Benjamin Hershberg , Barend Wilhelmus Marinus Van Liempd , Jan Craninckx
IPC分类号： H03H7/38 , H03H7/46 , H04B1/18 , H04B1/52
摘要： A system having a tunable impedance network and a method of tuning a tunable impedance network are disclosed. In one aspect, a telecommunications device comprises an electrical-balance duplexer (EBD) circuit coupled to at least one output node of a transmit path (TXin), an antenna, and at least one input node of a receive path (RXout), wherein the EBD circuit is configured to isolate the transmit path from the receive path by signal cancellation, and a balancing network (Zbal) as part of the EBD circuit. In one embodiment, the balancing network is an integrated tunable impedance network configured to provide an impedance that matches a target impedance (Zant) associated with the antenna at a first frequency and simultaneously at a second, different frequency. The network comprises a first portion and a second portion, the first portion reducing the influence of the tuning of the second portion at the first frequency. In some embodiments, the network preferably comprises no explicit resistors.

10. 发明申请

US20170179976A1 CIRCUIT AND METHOD FOR CONVERTING ANALOG SIGNAL TO DIGITAL VALUE REPRESENTATION 有权
公开(公告)号：US20170179976A1
公开(公告)日：2017-06-22
申请号：US15369777
申请日：2016-12-05
申请人： IMEC VZW
发明人： Jan Craninckx , Jonathan Borremans , Maarten De Bock
IPC分类号： H03M3/00
CPC分类号： H03M3/458 , H03M1/00 , H03M1/12 , H03M1/365 , H03M3/30 , H03M3/322 , H03M3/39 , H03M3/496
摘要： A circuit and a method for converting an analog signal to a digital value representation is disclosed. In one aspect, the circuit includes an incremental sigma-delta analog-to-digital converter (ADC). The circuit further includes a first input line for providing a primary analog signal representing a sensor measurement to the incremental sigma-delta ADC. The circuit further includes a second input line for providing a secondary analog signal to the incremental sigma-delta ADC. The incremental sigma-delta ADC receives the primary and secondary analog signals during a first period (TADC1) and a second period (TADC2), respectively. The circuit further includes a filter configured to weight the digital values in a sequence of digital values output by the incremental sigma-delta ADC, and to output a single digital value representing the sensor measurement.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式