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1. 发明申请

US20070239970A1 Apparatus For Cooperative Sharing Of Operand Access Port Of A Banked Register File 审中-公开
标题翻译：用于共享存储文件的操作数接入端口的装置
公开(公告)号：US20070239970A1
公开(公告)日：2007-10-11
申请号：US11278824
申请日：2006-04-06
申请人： I-Tao Liao , Chuan-Cheng Peng , Po-Han Huang , Chuan-Hua Chang
发明人： I-Tao Liao , Chuan-Cheng Peng , Po-Han Huang , Chuan-Hua Chang
IPC分类号： G06F9/44
CPC分类号： G06F9/3012 , G06F9/30141 , G06F9/3836 , G06F9/3885 , G06F9/3891
摘要： An apparatus for cooperative sharing of operand access port of a banked register file comprises a partitioned register file, a first group of functional unit, a second group of function units and an access control circuit. The access control circuit includes three control bits to control the accesses to the register file by the functional units for operands. The invention is to relax the constraint encountered by the compiler and a smart assembler using a conventional Ping-Pong file register. The relaxed constraint allows the two banks of the partitioned register file accessed by two instructions simultaneously as long as each corresponding operand of the two instructions are in different register banks. By the relaxed constraint, a compiler and a smart assembler have more choices to schedule instructions in a program, potentially increasing program performance.
摘要翻译：一种用于协同共享存储寄存器文件的操作数访问端口的装置，包括分区寄存器文件，第一组功能单元，第二组功能单元和访问控制电路。访问控制电路包括三个控制位，用于控制功能单元对操作数对寄存器文件的访问。本发明是为了放松使用传统乒乓文件寄存器的编译器和智能汇编器遇到的约束。宽松的约束允许两个指令同时访问的分区寄存器文件的两个库，只要两个指令的每个相应的操作数都在不同的寄存器组中。通过轻松的约束，编译器和智能汇编器有更多的选择来调度程序中的指令，从而潜在地增加程序性能。

2. 发明申请

US20100124308A1 Method of Handling Successive Bitstream Extraction and Packing and Related Device 有权
标题翻译：处理逐行提取和包装及相关设备的方法
公开(公告)号：US20100124308A1
公开(公告)日：2010-05-20
申请号：US12271924
申请日：2008-11-16
申请人： Chuan-Hua Chang , Hong-Men Su
发明人： Chuan-Hua Chang , Hong-Men Su
IPC分类号： H03K21/00
CPC分类号： H03K21/38 , G06F9/30018
摘要： To handle boundary conditions efficiently during bitstream extraction, a predetermined number of bits are extracted from the bitstream register starting from a most significant bit of the bitstream register when an underflow flag is set. The predetermined number equals a predetermined extraction width minus a previous starting position. The bits are stored in a lowest part of a destination register, and the underflow flag is cleared.
摘要翻译：为了在比特流提取期间有效地处理边界条件，当设置下溢标志时，从比特流寄存器的最高有效位开始从比特流寄存器提取预定数量的比特。预定数量等于预定的提取宽度减去先前的开始位置。这些位被存储在目标寄存器的最低部分，并且下溢标志被清除。

3. 发明授权

US07003648B2 Flexible demand-based resource allocation for multiple requestors in a simultaneous multi-threaded CPU 失效
公开(公告)号：US07003648B2
公开(公告)日：2006-02-21
申请号：US10109255
申请日：2002-03-28
申请人： George Z. Chrysos , Chuan-Hua Chang , Joel S. Emer , John H. Mylius , Peter Soderquist
发明人： George Z. Chrysos , Chuan-Hua Chang , Joel S. Emer , John H. Mylius , Peter Soderquist
IPC分类号： G06F15/82 , G06F15/163
CPC分类号： G06F9/3855 , G06F9/3824 , G06F9/3836 , G06F9/3851 , G06F9/3857
摘要： A multi-threaded processor provides for efficient flow-control from a pool of un-executed stores in an instruction queue to a store queue. The processor also includes similar capabilities with respect to load instructions. The processor includes logic organized into a plurality of thread processing units (“TPUs”) and allocation logic that monitors each TPUs demand for entries in the store queue. Demand is determined by subtracting an adjustable threshold value from the most recently assigned store identifier value. If the difference between the most recently assigned instruction identifier for a TPU and the TPU's threshold is non-zero, then it is determined that the TPU has demand for at least one entry in the store queue. The allocation logic includes arbitration logic that determines which one of a plurality of TPUs with store queue demand should be allocated a free entry in the store queue.

4. 发明授权

US08171188B2 Method of handling successive bitstream extraction and packing and related device 有权
标题翻译：处理连续比特流提取和打包及相关设备的方法
公开(公告)号：US08171188B2
公开(公告)日：2012-05-01
申请号：US12271924
申请日：2008-11-16
申请人： Chuan-Hua Chang , Hong-Men Su
发明人： Chuan-Hua Chang , Hong-Men Su
IPC分类号： G06F5/14 , G06F7/24
CPC分类号： H03K21/38 , G06F9/30018
摘要： To handle boundary conditions efficiently during bitstream extraction, a predetermined number of bits are extracted from the bitstream register starting from a most significant bit of the bitstream register when an underflow flag is set. The predetermined number equals a predetermined extraction width minus a previous starting position. The bits are stored in a lowest part of a destination register, and the underflow flag is cleared.
摘要翻译：为了在比特流提取期间有效地处理边界条件，当设置下溢标志时，从比特流寄存器的最高有效位开始从比特流寄存器提取预定数量的比特。预定数量等于预定的提取宽度减去先前的开始位置。这些位被存储在目标寄存器的最低部分，并且下溢标志被清除。

5. 发明申请

US20080140986A1 METHOD FOR ACCESSING TARGET REGISTER OF REGISTERS AND APPARATUS THEREOF 审中-公开
标题翻译：用于访问寄存器目标寄存器的方法及其装置
公开(公告)号：US20080140986A1
公开(公告)日：2008-06-12
申请号：US11608247
申请日：2006-12-08
申请人： Chuan-Hua Chang , Hong-Men Su , Jen-Chih Tseng
发明人： Chuan-Hua Chang , Hong-Men Su , Jen-Chih Tseng
IPC分类号： G06F12/06
CPC分类号： G06F9/30145 , G06F9/30134 , G06F9/384
摘要： A method is disclosed for accessing a target register of a plurality of registers. The method includes: receiving an instruction containing a register index field; and mapping the register index field to the target register access index for accessing the target register. A data accessing apparatus corresponding to this method is also disclosed.
摘要翻译：公开了一种用于访问多个寄存器的目标寄存器的方法。该方法包括：接收包含寄存器索引字段的指令; 并将寄存器索引字段映射到用于访问目标寄存器的目标寄存器访问索引。还公开了与该方法对应的数据访问装置。

6. 发明申请

US20130138921A1 DE-COUPLED CO-PROCESSOR INTERFACE 审中-公开
标题翻译：脱耦合处理器接口
公开(公告)号：US20130138921A1
公开(公告)日：2013-05-30
申请号：US13304705
申请日：2011-11-28
申请人： Yuan-Yuan Shih , Chuan-Hua Chang , Chi-Chang Lai
发明人： Yuan-Yuan Shih , Chuan-Hua Chang , Chi-Chang Lai
IPC分类号： G06F15/76 , G06F9/02
CPC分类号： G06F9/3881
摘要： A de-coupled co-processor interface (CPIF) is provided. The de-coupled CPIF transfers endian information along with the dispatching of co-processor (COP) instructions. The de-coupled CPIF divides the status report provided by a COP into an early status report and a late status report. The de-coupled CPIF may disable the late status report in order to improve the performance. The de-coupled CPIF further provides multiple early flush interfaces (EFIs) to transfer early flush events from a main processor (MP) to a corresponding COP. As a result, the de-coupled CPIF can improve the performance of the processing of data endian, status reports and early flush events between an MP and a COP.
摘要翻译：提供去耦合协处理器接口（CPIF）。去耦合的CPIF传送尾随信息以及协处理器（COP）指令的调度。解散的CPIF将COP提供的状态报告分为早期状态报告和后期状态报告。去耦合CPIF可能会禁用后期状态报告，以提高性能。解耦CPIF还提供多个早期冲洗接口（EFI），以将早期冲洗事件从主处理器（MP）传送到相应的COP。因此，解耦CPIF可以提高MP和COP之间数据端，状态报告和早期冲突事件的处理性能。

7. 发明授权

US07822999B2 Computer system and method for controlling a processor thereof 有权
标题翻译：用于控制其处理器的计算机系统和方法
公开(公告)号：US07822999B2
公开(公告)日：2010-10-26
申请号：US11757411
申请日：2007-06-04
申请人： Li-Hung Chang , Hong-Men Su , Chuan-Hua Chang
发明人： Li-Hung Chang , Hong-Men Su , Chuan-Hua Chang
IPC分类号： G06F1/00 , G06F1/26 , G11C5/14 , H04B1/38
CPC分类号： G06F1/3203 , G06F1/324 , G06F1/3296 , Y02D10/126 , Y02D10/172
摘要： A computer system and a method for controlling a processor thereof are provided. A processor management unit (PMU) is programmed by the processor itself or by another processor according to a change of the operating condition of the processor. Then, a notification signal is sent to the PMU by the processor when the processor is entering a standby mode. Upon receiving the notification signal, the PMU adjusts the operating condition of the processor according to the change. Finally, a completion signal is sent by the PMU to the processor after the change of the operating condition of the processor is stabilized. Therefore, the unpredictable behavior caused by premature awakening of the processor during the adjustment of the operating condition can be avoided.
摘要翻译：提供了一种用于控制其处理器的计算机系统和方法。处理器管理单元（PMU）由处理器本身或由另一处理器根据处理器的工作状态的变化来编程。然后，当处理器进入待机模式时，处理器将通知信号发送到PMU。 PMU接收到通知信号后，根据变更调整处理器的运行状况。最后，在处理器的工作状态改变稳定之后，PMU向处理器发送一个完成信号。因此，可以避免在调整操作条件期间由处理器过早唤醒引起的不可预知的行为。

8. 发明授权

US06925552B2 Method and system with multiple exception handlers in a processor 失效
标题翻译：处理器中有多个异常处理程序的方法和系统
公开(公告)号：US06925552B2
公开(公告)日：2005-08-02
申请号：US09884675
申请日：2001-06-19
申请人： Matthew H. Reilly , Matthew C. Mattina , Shane L. Bell , Chuan-Hua Chang
发明人： Matthew H. Reilly , Matthew C. Mattina , Shane L. Bell , Chuan-Hua Chang
IPC分类号： G06F9/38 , G06F9/00
CPC分类号： G06F9/3861 , G06F9/3842
摘要： An exception handler for a processor is split into two functional units to permit exceptions to be classified into two categories. The first category of exceptions includes performance critical excepted instructions, while the second category includes non-performance critical excepted instructions. The performance critical exceptions are routed to a speculative exception handler, which resolves the exceptions speculatively, even though the excepted instruction may lie in a speculative path of the program flow. The non-performance critical exceptions are routed to a non-speculative exception handler that only resolves exceptions when the excepted instruction is certain to execute in an actual path of the program flow.
摘要翻译：处理器的异常处理程序分为两个功能单元，以允许将异常分为两类。第一类异常包括性能关键的除外指令，而第二类包括非性能关键的除外指令。性能关键异常被路由到推测性的异常处理程序，即异常指令可能位于程序流的推测路径中，该异常处理程序可以推测性地解析异常。非性能关键异常被路由到非推测性异常处理程序，该异常处理程序仅在排除的指令确定在程序流的实际路径中执行时才解析异常。

9. 发明授权

US07934073B2 Method for performing jump and translation state change at the same time 有权
标题翻译：同时执行跳转和翻译状态改变的方法
公开(公告)号：US07934073B2
公开(公告)日：2011-04-26
申请号：US11685773
申请日：2007-03-14
申请人： Chuan-Hua Chang , Hong-Men Su
发明人： Chuan-Hua Chang , Hong-Men Su
IPC分类号： G06F12/00
CPC分类号： G06F9/322 , G06F9/30181 , G06F9/4812 , G06F12/10
摘要： A method for performing a jump and translation state change procedure at the same time is disclosed. The method includes: carrying out a series of instruction processing in a first function in a first translation state; and executing a jump instruction which jumps to a target address in a second function and initiates and completes a translation state change to a second translation state at the same time; wherein an address of a next instruction after the jump instruction is stored as a return address in a first register.
摘要翻译：公开了一种用于同时执行跳转和转换状态改变过程的方法。该方法包括：以第一翻译状态在第一功能中执行一系列指令处理; 并执行在第二功能中跳转到目标地址的跳转指令，并同时启动并完成翻译状态改变为第二翻译状态; 其中在所述跳转指令之后的下一条指令的地址作为返回地址被存储在第一寄存器中。

10. 发明申请

US20080229054A1 METHOD FOR PERFORMING JUMP AND TRANSLATION STATE CHANGE AT THE SAME TIME 有权
标题翻译：同时执行跳转和翻译状态更改的方法
公开(公告)号：US20080229054A1
公开(公告)日：2008-09-18
申请号：US11685773
申请日：2007-03-14
申请人： Chuan-Hua Chang , Hong-Men Su
发明人： Chuan-Hua Chang , Hong-Men Su
IPC分类号： G06F9/34
CPC分类号： G06F9/322 , G06F9/30181 , G06F9/4812 , G06F12/10
摘要： A method for performing a jump and translation state change procedure at the same time is disclosed. The method includes: carrying out a series of instruction processing in a first function in a first translation state; and executing a jump instruction which jumps to a target address in a second function and initiates and completes a translation state change to a second translation state at the same time; wherein an address of a next instruction after the jump instruction is stored as a return address in a first register.
摘要翻译：公开了一种用于同时执行跳转和转换状态改变过程的方法。该方法包括：以第一翻译状态在第一功能中执行一系列指令处理; 并执行在第二功能中跳转到目标地址的跳转指令，并同时启动并完成翻译状态改变为第二翻译状态; 其中在所述跳转指令之后的下一条指令的地址作为返回地址被存储在第一寄存器中。

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