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1. 发明申请

US20080140986A1 METHOD FOR ACCESSING TARGET REGISTER OF REGISTERS AND APPARATUS THEREOF 审中-公开
标题翻译：用于访问寄存器目标寄存器的方法及其装置
公开(公告)号：US20080140986A1
公开(公告)日：2008-06-12
申请号：US11608247
申请日：2006-12-08
申请人： Chuan-Hua Chang , Hong-Men Su , Jen-Chih Tseng
发明人： Chuan-Hua Chang , Hong-Men Su , Jen-Chih Tseng
IPC分类号： G06F12/06
CPC分类号： G06F9/30145 , G06F9/30134 , G06F9/384
摘要： A method is disclosed for accessing a target register of a plurality of registers. The method includes: receiving an instruction containing a register index field; and mapping the register index field to the target register access index for accessing the target register. A data accessing apparatus corresponding to this method is also disclosed.
摘要翻译：公开了一种用于访问多个寄存器的目标寄存器的方法。该方法包括：接收包含寄存器索引字段的指令; 并将寄存器索引字段映射到用于访问目标寄存器的目标寄存器访问索引。还公开了与该方法对应的数据访问装置。

2. 发明授权

US07627743B2 Method and circuit implementation for multiple-word transfer into/from memory subsystems 有权
标题翻译：从存储器子系统进入/从多个字传输的方法和电路实现
公开(公告)号：US07627743B2
公开(公告)日：2009-12-01
申请号：US11622471
申请日：2007-01-12
申请人： Hong-Men Su , Chuan-Hua Chang , Jen-Chih Tseng
发明人： Hong-Men Su , Chuan-Hua Chang , Jen-Chih Tseng
IPC分类号： G06F9/312 , G06F9/345
CPC分类号： G06F9/30043
摘要： A multi-word transfer instruction, a memory transfer method using the multi-word transfer instruction and a circuit implementation for transferring multiple words between a memory subsystem and a processor register file are provided. The multi-word transfer instruction specifies an access type (load or store), a consecutive register group, a selection mask and a base register for the starting address of the corresponding memory locations. Therefore, the total number of words accessed by this instruction is equal to the number of registers specified in the consecutive register group along with the number of the registers specified by the selection mask. Besides, additional information, such as an address update mode, an order mode and a modification mode, may be further specified in the multi-word transfer instruction.
摘要翻译：提供多字传输指令，使用多字传输指令的存储器传送方法和用于在存储器子系统和处理器寄存器文件之间传送多个字的电路实现。多字传输指令指定相应存储器位置的起始地址的访问类型（加载或存储），连续寄存器组，选择掩码和基址寄存器。因此，该指令访问的字总数等于连续寄存器组中指定的寄存器数以及选择掩码指定的寄存器数。此外，可以在多字传输指令中进一步指定附加信息，诸如地址更新模式，订单模式和修改模式。

3. 发明申请

US20080172550A1 METHOD AND CIRCUIT IMPLEMENTATION FOR MULTIPLE-WORD TRANSFER INTO/FROM MEMORY SUBSYSTEMS 有权
标题翻译：用于多字节传输到记忆体子系统的方法和电路实现
公开(公告)号：US20080172550A1
公开(公告)日：2008-07-17
申请号：US11622471
申请日：2007-01-12
申请人： Hong-Men Su , Chuan-Hua Chang , Jen-Chih Tseng
发明人： Hong-Men Su , Chuan-Hua Chang , Jen-Chih Tseng
IPC分类号： G06F9/312
CPC分类号： G06F9/30043
摘要： A multi-word transfer instruction, a memory transfer method using the multi-word transfer instruction and a circuit implementation for transferring multiple words between a memory subsystem and a processor register file are provided. The multi-word transfer instruction specifies an access type (load or store), a consecutive register group, a selection mask and a base register for the starting address of the corresponding memory locations. Therefore, the total number of words accessed by this instruction is equal to the number of registers specified in the consecutive register group along with the number of the registers specified by the selection mask. Besides, additional information, such as an address update mode, an order mode and a modification mode, may be further specified in the multi-word transfer instruction.
摘要翻译：提供多字传输指令，使用多字传输指令的存储器传送方法和用于在存储器子系统和处理器寄存器文件之间传送多个字的电路实现。多字传输指令指定相应存储器位置的起始地址的访问类型（加载或存储），连续寄存器组，选择掩码和基址寄存器。因此，该指令访问的字总数等于连续寄存器组中指定的寄存器数以及选择掩码指定的寄存器数。此外，可以在多字传输指令中进一步指定附加信息，诸如地址更新模式，订单模式和修改模式。

4. 发明申请

US20100124308A1 Method of Handling Successive Bitstream Extraction and Packing and Related Device 有权
标题翻译：处理逐行提取和包装及相关设备的方法
公开(公告)号：US20100124308A1
公开(公告)日：2010-05-20
申请号：US12271924
申请日：2008-11-16
申请人： Chuan-Hua Chang , Hong-Men Su
发明人： Chuan-Hua Chang , Hong-Men Su
IPC分类号： H03K21/00
CPC分类号： H03K21/38 , G06F9/30018
摘要： To handle boundary conditions efficiently during bitstream extraction, a predetermined number of bits are extracted from the bitstream register starting from a most significant bit of the bitstream register when an underflow flag is set. The predetermined number equals a predetermined extraction width minus a previous starting position. The bits are stored in a lowest part of a destination register, and the underflow flag is cleared.
摘要翻译：为了在比特流提取期间有效地处理边界条件，当设置下溢标志时，从比特流寄存器的最高有效位开始从比特流寄存器提取预定数量的比特。预定数量等于预定的提取宽度减去先前的开始位置。这些位被存储在目标寄存器的最低部分，并且下溢标志被清除。

5. 发明授权

US07822999B2 Computer system and method for controlling a processor thereof 有权
标题翻译：用于控制其处理器的计算机系统和方法
公开(公告)号：US07822999B2
公开(公告)日：2010-10-26
申请号：US11757411
申请日：2007-06-04
申请人： Li-Hung Chang , Hong-Men Su , Chuan-Hua Chang
发明人： Li-Hung Chang , Hong-Men Su , Chuan-Hua Chang
IPC分类号： G06F1/00 , G06F1/26 , G11C5/14 , H04B1/38
CPC分类号： G06F1/3203 , G06F1/324 , G06F1/3296 , Y02D10/126 , Y02D10/172
摘要： A computer system and a method for controlling a processor thereof are provided. A processor management unit (PMU) is programmed by the processor itself or by another processor according to a change of the operating condition of the processor. Then, a notification signal is sent to the PMU by the processor when the processor is entering a standby mode. Upon receiving the notification signal, the PMU adjusts the operating condition of the processor according to the change. Finally, a completion signal is sent by the PMU to the processor after the change of the operating condition of the processor is stabilized. Therefore, the unpredictable behavior caused by premature awakening of the processor during the adjustment of the operating condition can be avoided.
摘要翻译：提供了一种用于控制其处理器的计算机系统和方法。处理器管理单元（PMU）由处理器本身或由另一处理器根据处理器的工作状态的变化来编程。然后，当处理器进入待机模式时，处理器将通知信号发送到PMU。 PMU接收到通知信号后，根据变更调整处理器的运行状况。最后，在处理器的工作状态改变稳定之后，PMU向处理器发送一个完成信号。因此，可以避免在调整操作条件期间由处理器过早唤醒引起的不可预知的行为。

6. 发明授权

US08171188B2 Method of handling successive bitstream extraction and packing and related device 有权
标题翻译：处理连续比特流提取和打包及相关设备的方法
公开(公告)号：US08171188B2
公开(公告)日：2012-05-01
申请号：US12271924
申请日：2008-11-16
申请人： Chuan-Hua Chang , Hong-Men Su
发明人： Chuan-Hua Chang , Hong-Men Su
IPC分类号： G06F5/14 , G06F7/24
CPC分类号： H03K21/38 , G06F9/30018
摘要： To handle boundary conditions efficiently during bitstream extraction, a predetermined number of bits are extracted from the bitstream register starting from a most significant bit of the bitstream register when an underflow flag is set. The predetermined number equals a predetermined extraction width minus a previous starting position. The bits are stored in a lowest part of a destination register, and the underflow flag is cleared.
摘要翻译：为了在比特流提取期间有效地处理边界条件，当设置下溢标志时，从比特流寄存器的最高有效位开始从比特流寄存器提取预定数量的比特。预定数量等于预定的提取宽度减去先前的开始位置。这些位被存储在目标寄存器的最低部分，并且下溢标志被清除。

7. 发明授权

US07934073B2 Method for performing jump and translation state change at the same time 有权
标题翻译：同时执行跳转和翻译状态改变的方法
公开(公告)号：US07934073B2
公开(公告)日：2011-04-26
申请号：US11685773
申请日：2007-03-14
申请人： Chuan-Hua Chang , Hong-Men Su
发明人： Chuan-Hua Chang , Hong-Men Su
IPC分类号： G06F12/00
CPC分类号： G06F9/322 , G06F9/30181 , G06F9/4812 , G06F12/10
摘要： A method for performing a jump and translation state change procedure at the same time is disclosed. The method includes: carrying out a series of instruction processing in a first function in a first translation state; and executing a jump instruction which jumps to a target address in a second function and initiates and completes a translation state change to a second translation state at the same time; wherein an address of a next instruction after the jump instruction is stored as a return address in a first register.
摘要翻译：公开了一种用于同时执行跳转和转换状态改变过程的方法。该方法包括：以第一翻译状态在第一功能中执行一系列指令处理; 并执行在第二功能中跳转到目标地址的跳转指令，并同时启动并完成翻译状态改变为第二翻译状态; 其中在所述跳转指令之后的下一条指令的地址作为返回地址被存储在第一寄存器中。

8. 发明申请

US20080229054A1 METHOD FOR PERFORMING JUMP AND TRANSLATION STATE CHANGE AT THE SAME TIME 有权
标题翻译：同时执行跳转和翻译状态更改的方法
公开(公告)号：US20080229054A1
公开(公告)日：2008-09-18
申请号：US11685773
申请日：2007-03-14
申请人： Chuan-Hua Chang , Hong-Men Su
发明人： Chuan-Hua Chang , Hong-Men Su
IPC分类号： G06F9/34
CPC分类号： G06F9/322 , G06F9/30181 , G06F9/4812 , G06F12/10
摘要： A method for performing a jump and translation state change procedure at the same time is disclosed. The method includes: carrying out a series of instruction processing in a first function in a first translation state; and executing a jump instruction which jumps to a target address in a second function and initiates and completes a translation state change to a second translation state at the same time; wherein an address of a next instruction after the jump instruction is stored as a return address in a first register.
摘要翻译：公开了一种用于同时执行跳转和转换状态改变过程的方法。该方法包括：以第一翻译状态在第一功能中执行一系列指令处理; 并执行在第二功能中跳转到目标地址的跳转指令，并同时启动并完成翻译状态改变为第二翻译状态; 其中在所述跳转指令之后的下一条指令的地址作为返回地址被存储在第一寄存器中。

9. 发明申请

US20100211591A1 APPARATUS FOR PROCESSING STRINGS SIMULTANEOUSLY 审中-公开
标题翻译：同时处理行的装置
公开(公告)号：US20100211591A1
公开(公告)日：2010-08-19
申请号：US12371908
申请日：2009-02-16
申请人： Chuan-Hua Chang , Chi-Chang Lai , Hong-Men Su
发明人： Chuan-Hua Chang , Chi-Chang Lai , Hong-Men Su
IPC分类号： G06F17/30
CPC分类号： G06F16/90344
摘要： An exemplary string processing method for specific byte string processing with word-related instructions includes: loading a plurality of first predetermined strings; comparing a specific string with the loaded first predetermined strings simultaneously, thereby generating a plurality of comparison results corresponding to the specific string; and generating a string processing result according to the comparison results. A string processing apparatus uses the string processing method.
摘要翻译：用于与字相关指令的特定字节串处理的示例性字符串处理方法包括：加载多个第一预定字符串; 同时将特定字符串与加载的第一预定字符串进行比较，从而生成对应于特定字符串的多个比较结果; 并根据比较结果生成字符串处理结果。字符串处理装置使用字符串处理方法。

10. 发明申请

US20080301480A1 COMPUTER SYSTEM AND METHOD FOR CONTROLLING A PROCESSOR THEREOF 有权
标题翻译：用于控制处理器的计算机系统和方法
公开(公告)号：US20080301480A1
公开(公告)日：2008-12-04
申请号：US11757411
申请日：2007-06-04
申请人： Li-Hung Chang , Hong-Men Su , Chuan-Hua Chang
发明人： Li-Hung Chang , Hong-Men Su , Chuan-Hua Chang
IPC分类号： G06F1/28 , G06F9/46
CPC分类号： G06F1/3203 , G06F1/324 , G06F1/3296 , Y02D10/126 , Y02D10/172
摘要： A computer system and a method for controlling a processor thereof are provided. A processor management unit (PMU) is programmed by the processor itself or by another processor according to a change of the operating condition of the processor. Then, a notification signal is sent to the PMU by the processor when the processor is entering a standby mode. Upon receiving the notification signal, the PMU adjusts the operating condition of the processor according to the change. Finally, a completion signal is sent by the PMU to the processor after the change of the operating condition of the processor is stabilized. Therefore, the unpredictable behavior caused by premature awakening of the processor during the adjustment of the operating condition can be avoided.
摘要翻译：提供了一种用于控制其处理器的计算机系统和方法。处理器管理单元（PMU）由处理器本身或由另一处理器根据处理器的工作状态的变化来编程。然后，当处理器进入待机模式时，处理器将通知信号发送到PMU。 PMU接收到通知信号后，根据变更调整处理器的运行状况。最后，在处理器的工作状态改变稳定之后，PMU向处理器发送一个完成信号。因此，可以避免在调整操作条件期间由处理器过早唤醒引起的不可预知的行为。

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