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1. 发明授权

US08705715B2 Home appliance, home appliance system, and diagnosis method of a home appliance 有权
标题翻译：家电，家电系统和家电的诊断方法
公开(公告)号：US08705715B2
公开(公告)日：2014-04-22
申请号：US12432111
申请日：2009-04-29
申请人： Hyung Jun Park , Hae Yong Kang , Young Soo Kim , Si Moon Jeon , Koon Seok Lee , Yong Tae Kim , Hyun Sang Kim , Eui Hyeok Kwon
发明人： Hyung Jun Park , Hae Yong Kang , Young Soo Kim , Si Moon Jeon , Koon Seok Lee , Yong Tae Kim , Hyun Sang Kim , Eui Hyeok Kwon
IPC分类号： H04M11/00
CPC分类号： H04L12/2825 , H04B11/00 , H04L2012/285
摘要： A home appliance system and an operation method thereof are disclosed. The home appliance outputs product information as a predetermined sound and transmits the sound through a connected communication network, thereby making it easier for a service center at a remote place to check a status of the home appliance. Further, the home appliance system and operation method thereof prevents noise or signal error generated in the procedure of converting product information into a signal of a predetermined frequency band in order to output the product information as a sound, thus enabling stable signal conversion and improving the accuracy of information transmission using the output of sound.
摘要翻译：公开了家电系统及其操作方法。家用电器将产品信息作为预定声音输出，并通过连接的通信网络发送声音，从而使远程位置的服务中心更容易地检查家用电器的状态。此外，家用电器系统及其操作方法防止将产品信息转换为预定频带的信号的过程中产生的噪声或信号错误，以便将产品信息输出为声音，从而实现稳定的信号转换和改善使用声音输出的信息传输精度。

2. 发明授权

US08532273B2 Home appliance and home appliance system 有权
标题翻译：家电和家电系统
公开(公告)号：US08532273B2
公开(公告)日：2013-09-10
申请号：US12431910
申请日：2009-04-29
申请人： Hyung Jun Park , Hae Yong Kang , Young Soo Kim , Si Moon Jeon , Koon Seok Lee , Yong Tae Kim
发明人： Hyung Jun Park , Hae Yong Kang , Young Soo Kim , Si Moon Jeon , Koon Seok Lee , Yong Tae Kim
IPC分类号： H04M11/00
CPC分类号： D06F33/02 , A47L15/0049 , A47L15/0063 , A47L2501/26 , D06F39/005 , D06F2210/00
摘要： A home appliance and a home appliance system are provided. The home appliance may convert product information into an acoustic signal and externally output the same as a sound. The home appliance system may receive the sound, convert the same into the acoustic signal, and then inversely convert the acoustic signal into the product information and read the same. Accordingly, the home appliance may externally output the acoustic signal as the sound so that the user may be easily notified of transmission. Also, the home appliance system may easily transmit the sound to a management device to read the product information because the sound may be transmitted via a communications network.
摘要翻译：提供家用电器和家用电器系统。家用电器可以将产品信息转换为声信号，并将外部输出与声音相同。家用电器系统可以接收声音，将其转换成声信号，然后将声信号反向转换成产品信息并读取它们。因此，家用电器可以外部输出声音信号作为声音，使得用户可以容易地通知传输。此外，家用电器系统可以容易地将声音发送到管理设备以读取产品信息，因为声音可以经由通信网络传输。

3. 发明授权

US07056459B2 Ethylene vinyl acetate based film for crosslinked blown eva foam, shoe components using the same, and method for manufacturing thereof 失效
标题翻译：用于交联吹塑泡沫的乙烯 - 乙酸乙烯酯基膜，使用它的鞋组分及其制备方法
公开(公告)号：US07056459B2
公开(公告)日：2006-06-06
申请号：US10602893
申请日：2003-06-25
申请人： Hyung Jun Park
发明人： Hyung Jun Park
IPC分类号： B29C44/02
CPC分类号： C08J5/18 , B29D35/0054 , B29D35/12 , B29D35/122 , B29D35/142 , C08J2331/04
摘要： A method for manufacturing shoe components using EVA copolymer of film shape having a thickness of 0.01 to 2 mm, preferably 0.1 to 1.0 mm and a surface roughness variations which cannot be easily discriminated through touch or sight, and a shoe component manufactured by the method are provided. The method overcomes the drawbacks caused during the process of manufacturing a shoe component with different mechanical physical properties or colors. The method allows for ease of manufacture of a shoe component with two or more types of colors or physical properties, through a single foam molding process using a film with less variation and ease of processing, to thereby simplify manufacturing procedures and reduce manufacturing costs. In addition, a high quality shoe component with no additional seam-line is obtained.
摘要翻译：使用厚度为0.01〜2mm，优选为0.1〜1.0mm的膜状的EVA共聚物和通过触摸或视觉不能容易地判别的表面粗糙度变化以及通过该方法制造的鞋部件来制造鞋部件的方法是：提供。该方法克服了在制造具有不同机械物理性质或颜色的鞋部件的过程中引起的缺点。该方法允许通过使用具有较小变化和易于加工的膜的单一泡沫模制方法容易地制造具有两种或更多种颜色或物理性质的鞋部件，从而简化制造程序并降低制造成本。另外，获得了没有附加缝线的高质量的鞋部件。

4. 发明授权

US06773961B1 Singulation method used in leadless packaging process 有权
标题翻译：无引线封装工艺中使用的切割方法
公开(公告)号：US06773961B1
公开(公告)日：2004-08-10
申请号：US10641094
申请日：2003-08-15
申请人： Jun Hong Lee , Hyung Jun Park , Hyeong No Kim , Kun A Kang
发明人： Jun Hong Lee , Hyung Jun Park , Hyeong No Kim , Kun A Kang
IPC分类号： H01L2144
CPC分类号： H01L21/561 , H01L21/4828 , H01L21/566 , H01L21/568 , H01L23/3107 , H01L24/48 , H01L24/73 , H01L24/97 , H01L2224/05599 , H01L2224/32245 , H01L2224/45099 , H01L2224/48091 , H01L2224/48247 , H01L2224/73265 , H01L2224/85399 , H01L2224/97 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/01076 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/10253 , H01L2924/14 , H01L2924/181 , H01L2924/3011 , H01L2224/85 , H01L2924/00012 , H01L2924/00 , H01L2224/45015 , H01L2924/207
摘要： A singulation method used in leadless packaging process is disclosed. An array of molded products on an upper surface of a lead frame is utilized in the singulation method. The lead frame has a plurality of dambars between the molded products. The lower surface of the lead frame is attached with a tape. Each of the molded products includes a semiconductor chip encapsulated in a package body and electrically coupled to the upper surface of the lead frame. The singulation method is accomplished by etching the upper surface of the lead frame with the package bodies as mask until each dambar is etched away.
摘要翻译：公开了一种在无引线封装工艺中使用的切割方法。在切割方法中使用在引线框架的上表面上的成型产品的阵列。引线框架在模制产品之间具有多个堤坝。引线框架的下表面附有带子。每个模制产品包括封装在封装主体中并电耦合到引线框架的上表面的半导体芯片。通过用封装体作为掩模蚀刻引线框架的上表面，直到每个阻挡层被蚀刻掉为止，完成了分割方法。

5. 发明授权

US06489218B1 Singulation method used in leadless packaging process 有权
标题翻译：无引线封装工艺中使用的切割方法
公开(公告)号：US06489218B1
公开(公告)日：2002-12-03
申请号：US09928729
申请日：2001-08-14
申请人： Hyeongno Kim , Hyung Jun Park , Sangbae Park , Junhong Lee , Kun-A Kang , Bae Doo Kim
发明人： Hyeongno Kim , Hyung Jun Park , Sangbae Park , Junhong Lee , Kun-A Kang , Bae Doo Kim
IPC分类号： H01L2146
CPC分类号： H01L21/4828 , H01L23/3107 , H01L24/45 , H01L24/48 , H01L2224/05599 , H01L2224/45139 , H01L2224/48247 , H01L2224/85399 , H01L2924/10253 , H01L2924/12042 , H01L2924/14 , H01L2924/181 , H01L2924/00 , H01L2924/00014 , H01L2924/00012
摘要： A singulation method comprising: (a) providing a molded product including semiconductor chips attached and electrically coupled to an upper surface of a lead frame wherein a lower surface of the lead frame is exposed from the bottom of the molded product, the lead frame including a plurality of units in an array arrangement and cutting streets between the units, each unit having a die pad and leads arranged at the periphery of the die pad, a first metal layer formed on the entire lower surface of the lead frame except the cutting streets; (b) etching the lower surface of the lead frame with the first metal layer as mask such that the cutting streets are etched away to form a plurality of grooves; and (c) cutting the etched molded product along the grooves to obtain the leadless semiconductor packages.
摘要翻译：一种分割方法，包括：（a）提供包括附接并电耦合到引线框架的上表面的半导体芯片的模制产品，其中引线框架的下表面从模制产品的底部露出，引线框架包括阵列布置中的多个单元和单元之间的切割街道，每个单元具有芯片焊盘和布置在管芯焊盘周边的引线，形成在除了切割街道之外的引线框架的整个下表面上的第一金属层; （b）用第一金属层作为掩模蚀刻引线框架的下表面，使得切割街道被蚀刻掉以形成多个凹槽; 和（c）沿着凹槽切割蚀刻的模制产品以获得无引线半导体封装。

6. 发明授权

US06342730B1 Low-pin-count chip package and manufacturing method thereof 有权
标题翻译：低引脚数芯片封装及其制造方法
公开(公告)号：US06342730B1
公开(公告)日：2002-01-29
申请号：US09492820
申请日：2000-01-28
申请人： Kyujin Jung , Kun-A Kang , Hyung Jun Park
发明人： Kyujin Jung , Kun-A Kang , Hyung Jun Park
IPC分类号： H01L2348
CPC分类号： H01L21/4832 , H01L23/3107 , H01L23/49582 , H01L24/48 , H01L2224/05599 , H01L2224/32245 , H01L2224/48091 , H01L2224/48247 , H01L2224/484 , H01L2224/73265 , H01L2224/85444 , H01L2224/85464 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01019 , H01L2924/01028 , H01L2924/01029 , H01L2924/01046 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/181 , H01L2924/18165 , H01L2224/45099 , H01L2924/00012
摘要： A low-pin-count chip package including a die pad for receiving a semiconductor chip and a plurality of connection pads electrically coupled to the semiconductor chip. The semiconductor chip, the die pad, and the connection pads are encapsulated in a package body such that the lower surfaces of the die pad and the connection pads are exposed through the package body. The present invention is characterized in that the die pad and the connection pads have a substantially concave profile thereby prolonging the time for moisture diffusion into the package as well as enhancing the “locking” of the die pad and the connection pads in the package body. The present invention further provides a method of producing the low-pin-count chip package described above.
摘要翻译：一种低引脚数的芯片封装，包括用于接收半导体芯片的管芯焊盘和与半导体芯片电连接的多个连接焊盘。半导体芯片，管芯焊盘和连接焊盘被封装在封装主体中，使得管芯焊盘和连接焊盘的下表面通过封装主体露出。本发明的特征在于，芯片焊盘和连接焊盘具有基本上凹形的轮廓，从而延长了水分扩散到封装中的时间，并且增强了封装体中芯片焊盘和连接焊盘的“锁定”。本发明还提供了一种制造上述低引脚数芯片封装的方法。

7. 发明授权

US09057921B2 Thin film transistor array panel and liquid crystal display device including the same 有权
标题翻译：薄膜晶体管阵列面板和包括其的液晶显示装置
公开(公告)号：US09057921B2
公开(公告)日：2015-06-16
申请号：US13546654
申请日：2012-07-11
申请人： Hyung Jun Park , Kyung-Ho Park , Woo-Jung Shin , Si Hyun Ahn , Dong-Hyun Yoo
发明人： Hyung Jun Park , Kyung-Ho Park , Woo-Jung Shin , Si Hyun Ahn , Dong-Hyun Yoo
IPC分类号： G02F1/136 , H01L27/12 , H01L29/417 , G02F1/1362 , G02F1/1343
CPC分类号： H01L27/124 , G02F1/136213 , G02F1/13624 , G02F2001/134345 , G02F2001/136245 , H01L29/41733 , H01L29/41758
摘要： A thin film transistor array panel includes a first substrate; a gate line and a data line on the first substrate; a storage electrode line on the first substrate where a constant voltage is applied thereto; a first thin film transistor and a second thin film transistor which are connected to the gate line and the data line; a third thin film transistor which is connected to the gate line, the second thin film transistor and the storage electrode line; a first subpixel electrode which is connected to the first thin film transistor; and a second subpixel electrode which is connected to the second thin film transistor.
摘要翻译：薄膜晶体管阵列面板包括第一基板; 第一基板上的栅极线和数据线; 在第一基板上施加恒定电压的存储电极线; 连接到栅极线和数据线的第一薄膜晶体管和第二薄膜晶体管; 连接到栅极线的第三薄膜晶体管，第二薄膜晶体管和存储电极线; 连接到第一薄膜晶体管的第一子像素电极; 以及与第二薄膜晶体管连接的第二子像素电极。

8. 发明授权

US07205658B2 Singulation method used in leadless packaging process 有权
标题翻译：无引线封装工艺中使用的切割方法
公开(公告)号：US07205658B2
公开(公告)日：2007-04-17
申请号：US10878521
申请日：2004-06-29
申请人： Jun Hong Lee , Hyung Jun Park , Hyeong No Kim , Kun A Kang
发明人： Jun Hong Lee , Hyung Jun Park , Hyeong No Kim , Kun A Kang
IPC分类号： H01L23/04
CPC分类号： H01L21/561 , H01L21/4828 , H01L21/566 , H01L21/568 , H01L23/3107 , H01L24/48 , H01L24/73 , H01L24/97 , H01L2224/05599 , H01L2224/32245 , H01L2224/45099 , H01L2224/48091 , H01L2224/48247 , H01L2224/73265 , H01L2224/85399 , H01L2224/97 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/01076 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/10253 , H01L2924/14 , H01L2924/181 , H01L2924/3011 , H01L2224/85 , H01L2924/00012 , H01L2924/00 , H01L2224/45015 , H01L2924/207
摘要： A singulation method used in leadless packaging process is disclosed. An array of molded products on an upper surface of a lead frame is utilized in the singulation method. The lead frame has a plurality of dambars between the molded products. The lower surface of the lead frame is attached with a tape. Each of the molded products includes a semiconductor chip encapsulated in a package body and electrically coupled to the upper surface of the lead frame. The singulation method is accomplished by etching the upper surface of the lead frame with the package bodies as mask until each dambar is etched away.
摘要翻译：公开了一种在无引线封装工艺中使用的切割方法。在切割方法中使用在引线框架的上表面上的成型产品的阵列。引线框架在模制产品之间具有多个堤坝。引线框架的下表面附有带子。每个模制产品包括封装在封装主体中并电耦合到引线框架的上表面的半导体芯片。通过用封装体作为掩模蚀刻引线框架的上表面，直到每个阻挡层被蚀刻掉为止，完成了分割方法。

9. 发明授权

US06861295B2 Low-pin-count chip package and manufacturing method thereof 有权
标题翻译：低引脚数芯片封装及其制造方法
公开(公告)号：US06861295B2
公开(公告)日：2005-03-01
申请号：US10020964
申请日：2001-12-19
申请人： Kyujin Jung , Kun-A Kang , Hyung Jun Park
发明人： Kyujin Jung , Kun-A Kang , Hyung Jun Park
IPC分类号： H01L21/48 , H01L23/31 , H01L23/495 , H01L21/44 , H01L21/50
CPC分类号： H01L21/4832 , H01L23/3107 , H01L23/49582 , H01L24/48 , H01L2224/05599 , H01L2224/32245 , H01L2224/48091 , H01L2224/48247 , H01L2224/484 , H01L2224/73265 , H01L2224/85444 , H01L2224/85464 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01019 , H01L2924/01028 , H01L2924/01029 , H01L2924/01046 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/181 , H01L2924/18165 , H01L2224/45099 , H01L2924/00012
摘要： A low-pin-count chip package including a die pad for receiving a semiconductor chip and a plurality of connection pads electrically coupled to the semiconductor chip. The semiconductor chip, the die pad, and the connection pads are encapsulated in a package body such that the lower surfaces of the die pad and the connection pads are exposed through the package body. The present invention is characterized in that the die pad and the connection pads have a substantially concave profile thereby prolonging the time for moisture diffusion into the package as well as enhancing the “locking” of the die pad and the connection pads in the package body. The present invention further provides a method of producing the low-pin-count chip package described above.
摘要翻译：一种低引脚数的芯片封装，包括用于接收半导体芯片的管芯焊盘和与半导体芯片电连接的多个连接焊盘。半导体芯片，管芯焊盘和连接焊盘被封装在封装主体中，使得管芯焊盘和连接焊盘的下表面通过封装主体露出。本发明的特征在于，芯片焊盘和连接焊盘具有基本上凹形的轮廓，从而延长了水分扩散到封装中的时间，并且增强了封装体中芯片焊盘和连接焊盘的“锁定”。本发明还提供了一种制造上述低引脚数芯片封装的方法。

10. 发明授权

US06242284B1 Method for packaging a semiconductor chip 有权
标题翻译：包装半导体芯片的方法
公开(公告)号：US06242284B1
公开(公告)日：2001-06-05
申请号：US09565452
申请日：2000-05-05
申请人： Kun-A Kang , Kyujin Jung , Hyung Jun Park , Jun Hong Lee
发明人： Kun-A Kang , Kyujin Jung , Hyung Jun Park , Jun Hong Lee
IPC分类号： H01L2144
CPC分类号： H01L21/6835 , H01L21/486 , H01L23/3107 , H01L23/3128 , H01L23/49827 , H01L24/48 , H01L2221/68377 , H01L2224/05599 , H01L2224/48091 , H01L2224/73265 , H01L2224/85399 , H01L2924/00014 , H01L2924/10253 , H01L2924/181 , H01L2924/18165 , H01L2924/00 , H01L2224/45015 , H01L2924/207 , H01L2224/45099 , H01L2924/00012
摘要： A method for packaging a semiconductor chip, generally comprising the following steps of: (a) forming a plurality of openings on the top surface of the conducting substrate, wherein the upper portions of the openings are formed larger than the lower portions of the openings; (b) forming insulating sections in the conducting substrate by filling an insulating material in the openings; (c) forming a plurality of leads insulated by the insulating sections by planarizing the bottom surface of the conducting substrate to expose and form planarized bottom surfaces of the insulating sections; (d) mounting a semiconductor chip on the bottom surface of the conducting substrate; (e) providing a plurality of conducting wires to electrically connect the semiconductor chip to the leads; and (f) encapsulating the semiconductor chip and the conducting wires. The package according to the present invention is characterized by upper portions of the leads that are purposedly formed larger than lower portions of the leads which prevents the leads from being easily detachable and the package from being destructed by water, the reliability of the package is thus increased.
摘要翻译：一种用于封装半导体芯片的方法，通常包括以下步骤：（a）在导电基板的顶表面上形成多个开口，其中开口的上部形成为大于开口的下部; （b）通过在开口中填充绝缘材料在导电衬底中形成绝缘部分; （c）通过平面化导电基板的底面形成绝缘部分绝缘的多个引线，露出和形成绝缘部分的平坦化底面; （d）将半导体芯片安装在导电基板的底表面上; （e）提供多个导线以将半导体芯片电连接到引线; 和（f）封装半导体芯片和导线。根据本发明的封装的特征在于，引线的上部设计成大于引线的下部，防止引线容易拆卸，并且封装不被水破坏，因此封装的可靠性因此增加。

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