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1. 发明授权

US07855109B2 Method for manufacturing a semiconductor device capable of preventing the generation of a bridge between a recess gate and a PLC plug 失效
标题翻译：一种用于制造能够防止在凹槽门和PLC插头之间产生桥接的半导体器件的方法
公开(公告)号：US07855109B2
公开(公告)日：2010-12-21
申请号：US12345755
申请日：2008-12-30
申请人： Hyung Hwan Kim , Kwang Kee Chae , Jong Goo Jung , Ok Min Moon , Young Bang Lee , Sung Eun Park
发明人： Hyung Hwan Kim , Kwang Kee Chae , Jong Goo Jung , Ok Min Moon , Young Bang Lee , Sung Eun Park
IPC分类号： H01L21/337
CPC分类号： H01L21/76232
摘要： A method for manufacturing a semiconductor device according to the present invention, comprising the steps of: forming a screen oxide layer over the surface of an active region of a semiconductor substrate in which an isolation structure defining the active region is formed; forming a first recess pattern in the active region and a second recess pattern in the isolation structure by etching a gate forming area in the active region and the isolation structure part extended thereto; removing the screen oxide film and simultaneously expanding the width of the second recess pattern; forming a first insulation dielectric layer over the resultant of the substrate having the second recess pattern with the expanded width so that the first insulation dielectric layer is blocked at the upper end thereof in the first recess pattern and it is deposited along the profile in the second recess pattern; forming a second insulation dielectric layer over the first insulation dielectric layer so that the second recess patter is not filled; forming a third insulation dielectric layer over the second insulation dielectric layer so that the second recess pattern is filled; and removing the third, second, and first insulation dielectric layers formed over the active region including the first recess pattern and the isolation structure between the second recess patterns.
摘要翻译：一种根据本发明的半导体器件的制造方法，包括以下步骤：在其中形成限定有源区的隔离结构的半导体衬底的有源区的表面上形成屏蔽氧化物层; 通过蚀刻有源区域中的栅极形成区域和延伸到其中的隔离结构部分，在有源区域中形成第一凹槽图案和隔离结构中的第二凹陷图案; 去除屏幕氧化膜并同时扩大第二凹槽图案的宽度; 在具有第二凹槽图案的基底的结果上形成第一绝缘电介质层，其具有扩展的宽度，使得第一绝缘电介质层在其第一凹槽图案的上端处被阻挡，并且沿着第二凹部图案休闲模式; 在所述第一绝缘电介质层上形成第二绝缘电介质层，使得所述第二凹槽图案不被填充; 在所述第二绝缘电介质层上形成第三绝缘电介质层，使得所述第二凹槽图案被填充; 以及去除在包括第一凹槽图案的有源区域和在第二凹槽图案之间的隔离结构之间形成的第三绝缘介电层和第二绝缘介电层。

2. 发明授权

US08841198B2 Isolation layer having a bilayer structure for a semiconductor device and method for forming the same 有权
标题翻译：具有半导体器件的双层结构的隔离层及其形成方法
公开(公告)号：US08841198B2
公开(公告)日：2014-09-23
申请号：US12167322
申请日：2008-07-03
申请人： Hyung Hwan Kim , Kwang Kee Chae , Jong Goo Jung , Ok Min Moon , Young Bang Lee , Sung Eun Park
发明人： Hyung Hwan Kim , Kwang Kee Chae , Jong Goo Jung , Ok Min Moon , Young Bang Lee , Sung Eun Park
IPC分类号： H01L21/76 , H01L21/762
CPC分类号： H01L21/76232
摘要： An isolation layer of a semiconductor device and a process for forming the same is described herein. The isolation layer includes a trench that is defined and formed in a semiconductor substrate. A first liner nitride layer is formed on the surface of the trench and a flowable insulation layer is formed in the trench including the first liner nitride layer. The flowable insulation layer is formed such to define a recess in the trench. A second liner nitride layer is formed on the recess including the flowable insulation layer and the first liner nitride layer. Finally, an insulation layer is formed in the recess on the second liner nitride layer to completely fill the trench.
摘要翻译：本文描述了半导体器件的隔离层及其形成工艺。隔离层包括限定并形成在半导体衬底中的沟槽。第一衬里氮化物层形成在沟槽的表面上，并且在包括第一衬里氮化物层的沟槽中形成可流动的绝缘层。可流动绝缘层形成为在沟槽中限定凹部。在包括可流动绝缘层和第一衬里氮化物层的凹部上形成第二衬里氮化物层。最后，在第二衬里氮化物层上的凹槽中形成绝缘层以完全填充沟槽。

3. 发明授权

US08007594B2 Method for manufacturing semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US08007594B2
公开(公告)日：2011-08-30
申请号：US12834121
申请日：2010-07-12
申请人： Young Bang Lee , Kwang Kee Chae , Ok Min Moon
发明人： Young Bang Lee , Kwang Kee Chae , Ok Min Moon
IPC分类号： C23G1/02
CPC分类号： C23G1/103 , H01L21/02068 , H01L21/0209 , Y10S134/902 , Y10S438/906
摘要： A method for manufacturing a semiconductor device includes the step of conducting a cleaning process for a wafer formed with copper wiring lines to remove contaminations produced on a back surface of the wafer. The cleaning process is conducted by injecting onto the back surface of the wafer an etchant for removing contaminations and simultaneously injecting onto a front surface of the wafer a reductant containing hydrogen.
摘要翻译：一种制造半导体器件的方法包括对由铜布线形成的晶片进行清洁处理以除去晶片背面产生的污染物的步骤。通过在晶片的背面注入用于去除污染物的蚀刻剂并同时向晶片的前表面注入含有氢的还原剂来进行清洁过程。

4. 发明授权

US08187942B2 Method for manufacturing semiconductor device having a dual gate insulation layer 失效
标题翻译：具有双栅极绝缘层的半导体器件的制造方法
公开(公告)号：US08187942B2
公开(公告)日：2012-05-29
申请号：US12634889
申请日：2009-12-10
申请人： Young Bang Lee
发明人： Young Bang Lee
IPC分类号： H01L21/8234
CPC分类号： H01L21/31111 , H01L21/823462 , Y10S438/981
摘要： A method for manufacturing a semiconductor device having a dual gate insulation layer is presented. The method includes a step of forming a first insulation layer on a semiconductor substrate which has a first region and a second region. The method includes a step of selectively removing a portion of the first insulation layer formed the second region of the semiconductor substrate. The removal of the portion of the first insulation layer is conducted using an etching solution comprising propylene glycol, HF and amine. The method also includes a step of forming a second insulation layer on the first insulation layer in the first region and on the semiconductor substrate in the second region.
摘要翻译：本发明提供一种具有双栅极绝缘层的半导体器件的制造方法。该方法包括在具有第一区域和第二区域的半导体衬底上形成第一绝缘层的步骤。该方法包括选择性地去除形成半导体衬底的第二区域的第一绝缘层的一部分的步骤。使用包含丙二醇，HF和胺的蚀刻溶液进行第一绝缘层的部分的去除。该方法还包括在第一区域中的第一绝缘层和第二区域中的半导体衬底上形成第二绝缘层的步骤。

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