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1. 发明授权

US07807337B2 Inductor for a system-on-a-chip and a method for manufacturing the same 有权
标题翻译：一种片上系统的电感器及其制造方法
公开(公告)号：US07807337B2
公开(公告)日：2010-10-05
申请号：US11968787
申请日：2008-01-03
申请人： Hyo-Jong Lee , Hong-Seong Son , Ui-Hyoung Lee , Sang-Rok Hah , In-Ryong Kim , Yi-Gwon Kim
发明人： Hyo-Jong Lee , Hong-Seong Son , Ui-Hyoung Lee , Sang-Rok Hah , In-Ryong Kim , Yi-Gwon Kim
IPC分类号： G03F7/26
CPC分类号： H01L28/10 , H01F41/041 , H01F2017/0046 , H01L23/5227 , H01L27/08 , H01L2924/0002 , H01L2924/00
摘要： An inductor for a system-on-a-chip and a method for manufacturing the inductor are disclosed. The inductor comprises a conductive line formed by connecting a plurality of conductive patterns grown from a seed layer formed on a lower wiring. The method comprises using an electrolytic plating process or an electroless plating process to grow the plurality of adjacent conductive patterns from the seed layer until they become connected. The method also enables adjusting the height and width of the conductive line to desired levels.
摘要翻译：公开了一种用于片上系统的电感器和用于制造电感器的方法。电感器包括通过连接从形成在下布线上的晶种层生长的多个导电图案而形成的导电线。该方法包括使用电解电镀工艺或无电镀处理，以从种子层生长多个相邻的导电图案直到它们连接。该方法还能够将导线的高度和宽度调整到所希望的水平。

2. 发明申请

US20050116317A1 Inductor for a system-on-a-chip and method for manufacturing the same 审中-公开
标题翻译：用于片上系统的电感器及其制造方法
公开(公告)号：US20050116317A1
公开(公告)日：2005-06-02
申请号：US10982782
申请日：2004-11-08
申请人： Hyo-Jong Lee , Hong-Seong Son , Ui-Hyoung Lee , Sang-Rok Hah , Il-Ryong Kim , Yi-Gwon Kim
发明人： Hyo-Jong Lee , Hong-Seong Son , Ui-Hyoung Lee , Sang-Rok Hah , Il-Ryong Kim , Yi-Gwon Kim
IPC分类号： H01L27/04 , H01F17/00 , H01F41/04 , H01L21/02 , H01L23/522 , H01L27/08 , H01L21/00 , H01L21/4763 , H01L21/8238 , H01L29/00
CPC分类号： H01L28/10 , H01F41/041 , H01F2017/0046 , H01L23/5227 , H01L27/08 , H01L2924/0002 , H01L2924/00
摘要： An inductor for a system-on-a-chip and a method for manufacturing the inductor are disclosed. The inductor comprises a conductive line formed by connecting a plurality of conductive patterns grown from a seed layer formed on a lower wiring. The method comprises using an electrolytic plating process or an electroless plating process to grow the plurality of adjacent conductive patterns from the seed layer until they become connected. The method also enables adjusting the height and width of the conductive line to desired levels.
摘要翻译：公开了一种用于片上系统的电感器和用于制造电感器的方法。电感器包括通过连接从形成在下布线上的晶种层生长的多个导电图案而形成的导电线。该方法包括使用电解电镀工艺或无电镀处理，以从种子层生长多个相邻的导电图案直到它们连接。该方法还能够将导线的高度和宽度调整到所希望的水平。

3. 发明申请

US20050070090A1 Method of forming metal pattern using selective electroplating process 审中-公开
标题翻译：使用选择性电镀工艺形成金属图案的方法
公开(公告)号：US20050070090A1
公开(公告)日：2005-03-31
申请号：US10875434
申请日：2004-06-24
申请人： Hyo-Jong Lee , Jong-Won Lee , Duk-Ho Hong , Sang-Rok Hah , Hong-Seong Son , Jin-Sung Chung , Jae-Soo Ahn
发明人： Hyo-Jong Lee , Jong-Won Lee , Duk-Ho Hong , Sang-Rok Hah , Hong-Seong Son , Jin-Sung Chung , Jae-Soo Ahn
IPC分类号： H01L21/28 , H01L21/768 , H01L23/532 , H01L21/48 , H01L21/44 , H01L21/4763 , H01L21/50
CPC分类号： H01L21/76846 , H01L21/7684 , H01L21/76849 , H01L21/76864 , H01L21/76873 , H01L21/76879 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： A method of forming a metal pattern using a selective electroplating process is provided. First, a dielectric layer is formed on an underlying layer. Then, a trench defining blanket region is formed by patterning the dielectric layer. A diffusion barrier layer is conformally formed in the trench and on the blanket region. A polishing/plating stop layer and an upper seed layer are conformally formed on the diffusion barrier layer in a successive manner. The polishing/plating layer in the blanket region is exposed by selectively removing the upper seed layer in the blanket region, and, at the same time, a seed layer pattern remaining in the trenches is formed. An upper conductive layer is formed to fill the trench surrounded by the seed layer pattern using an electroplating process. Then, the dielectric layer in the blanket region is exposed by planarizing the upper conductive layer, the polishing/plating stop layer, the seed layer pattern, and the diffusion barrier layer.
摘要翻译：提供了使用选择性电镀工艺形成金属图案的方法。首先，在下层形成介电层。然后，通过图案化介电层形成限定覆盖区域的沟槽。扩散阻挡层在沟槽和覆盖区域中共形地形成。抛光/电镀停止层和上部种子层以连续的方式共形地形成在扩散阻挡层上。通过选择性地去除覆盖区域中的上部种子层，暴露覆盖区域中的抛光/镀覆层，并且同时形成留在沟槽中的晶种层图案。形成上导电层以使用电镀工艺填充由种子层图案包围的沟槽。然后，通过平坦化上导电层，抛光/电镀停止层，种子层图案和扩散阻挡层来曝光覆盖区域中的电介质层。

4. 发明申请

US20060270228A1 Method of forming metal pattern using selective electroplating process 审中-公开
标题翻译：使用选择性电镀工艺形成金属图案的方法
公开(公告)号：US20060270228A1
公开(公告)日：2006-11-30
申请号：US11501791
申请日：2006-08-09
申请人： Hyo-Jong Lee , Jong-Won Lee , Duk-Ho Hong , Sang-Rok Hah , Hong-Seong Son , Jin-Sung Chung , Jae-Soo Ahn
发明人： Hyo-Jong Lee , Jong-Won Lee , Duk-Ho Hong , Sang-Rok Hah , Hong-Seong Son , Jin-Sung Chung , Jae-Soo Ahn
IPC分类号： H01L21/44
CPC分类号： H01L21/76846 , H01L21/7684 , H01L21/76849 , H01L21/76864 , H01L21/76873 , H01L21/76879 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： A method of forming a metal pattern using a selective electroplating process is provided. First, a dielectric layer is formed on an underlying layer. Then, a trench defining blanket region is formed by patterning the dielectric layer. A diffusion barrier layer is conformally formed in the trench and on the blanket region. A polishing/plating stop layer and an upper seed layer are conformally formed on the diffusion barrier layer in a successive manner. The polishing/plating layer in the blanket region is exposed by selectively removing the upper seed layer in the blanket region, and, at the same time, a seed layer pattern remaining in the trenches is formed. An upper conductive layer is formed to fill the trench surrounded by the seed layer pattern using an electroplating process. Then, the dielectric layer in the blanket region is exposed by planarizing the upper conductive layer, the polishing/plating stop layer, the seed layer pattern, and the diffusion barrier layer.
摘要翻译：提供了使用选择性电镀工艺形成金属图案的方法。首先，在下层形成介电层。然后，通过图案化介电层形成限定覆盖区域的沟槽。扩散阻挡层在沟槽和覆盖区域中共形地形成。抛光/电镀停止层和上部种子层以连续的方式共形地形成在扩散阻挡层上。通过选择性地去除覆盖区域中的上部种子层，暴露覆盖区域中的抛光/镀覆层，并且同时形成留在沟槽中的晶种层图案。形成上导电层以使用电镀工艺填充由种子层图案包围的沟槽。然后，通过平坦化上导电层，抛光/电镀停止层，种子层图案和扩散阻挡层来曝光覆盖区域中的电介质层。

5. 发明申请

US20050048875A1 Chemical mechanical polishing apparatus 失效
公开(公告)号：US20050048875A1
公开(公告)日：2005-03-03
申请号：US10850688
申请日：2004-05-21
申请人： Ja-Eung Koo , Jong-Won Lee , Sung-Bae Lee , Duk-Ho Hong , Sang-Rok Hah , Hong-Seong Son
发明人： Ja-Eung Koo , Jong-Won Lee , Sung-Bae Lee , Duk-Ho Hong , Sang-Rok Hah , Hong-Seong Son
IPC分类号： B24B37/02 , B24B37/04 , B24B49/10 , B24B49/14 , B24B49/00 , B24B1/00
CPC分类号： B24B37/013 , B24B49/10 , B24B49/14
摘要： There is provided a chemical mechanical polishing apparatus, which may include a polishing table rotated by a polishing table motor and having a pad thereon, a carrier head located above the polishing table to be rotatable by the driving of a carrier head motor and having a wafer located under the bottom thereof, a slurry supplier for supplying a slurry to the upper portion of the polishing table, a first polishing end point detector for detecting a polishing end point through the temperature change of the temperature sensor, at least one temperature sensor for detecting the temperature of a polishing region (the wafer, the pad, and the slurry), and a second polishing end point detector for detecting a polishing end point from the changes of load current, voltage, and resistance of the carrier head motor. Further, instead of the second polishing end point detector, an optical signal polishing end point detector may be employed, for detecting the polishing end point by the light illuminated on the wafer and reflected from the wafer.

6. 发明授权

US07488235B2 Polishing apparatus and related polishing methods 失效
标题翻译：抛光装置及相关抛光方法
公开(公告)号：US07488235B2
公开(公告)日：2009-02-10
申请号：US11381415
申请日：2006-05-03
申请人： Moo-Yong Park , Sang-Rok Hah , Jong-Gyoon Kim , Hong-Seong Son , Ja-Hyung Han
发明人： Moo-Yong Park , Sang-Rok Hah , Jong-Gyoon Kim , Hong-Seong Son , Ja-Hyung Han
IPC分类号： B24B49/00
CPC分类号： B24B37/30 , B24B1/005 , B24B49/16
摘要： Polishing apparatus and related methods employ aligned first and second magnetic field sources to adjust the compressive force and/or pressure applied by a carrier head against a target workpiece (such as a wafer) by selectively and controllably generating a repellant or attractive force between the two magnetic field sources.
摘要翻译：抛光装置和相关方法使用对准的第一和第二磁场源来通过选择性地和可控地产生驱避剂或两者之间的吸引力来调节由载体头部抵靠目标工件（例如晶片）施加的压缩力和/或压力磁场源

7. 发明申请

US20070117378A1 Method of forming a trench for use in manufacturing a semiconductor device 审中-公开
标题翻译：形成用于制造半导体器件的沟槽的方法
公开(公告)号：US20070117378A1
公开(公告)日：2007-05-24
申请号：US11655159
申请日：2007-01-19
申请人： Sung-Bae Lee , Sang-Rok Hah , Hong-Seong Son
发明人： Sung-Bae Lee , Sang-Rok Hah , Hong-Seong Son
IPC分类号： H01L21/4763 , H01L21/44 , H01L21/302
CPC分类号： H01L27/10885 , H01L21/76229 , H01L21/76232 , H01L29/66181
摘要： A method for use in manufacturing a semiconductor device includes forming a photoresist pattern on a substrate, performing first etching process in which an initial trench is formed using the photoresist pattern as a mask, and performing second distinct etching process to enlarge the initial trench. Thus, the initial trench can be formed using the photoresist pattern having a stable structure. Thereafter, the trench is enlarged using an etching solution having a composition based on the material in which the initial trench is formed, e.g., silicon substrate or an insulation film. Therefore, a metal wiring, an isolation film or a contact can be formed in the enlarged trench to desired dimensions.
摘要翻译：一种用于制造半导体器件的方法包括在衬底上形成光致抗蚀剂图案，执行第一蚀刻工艺，其中使用光致抗蚀剂图案作为掩模形成初始沟槽，并且执行第二不同的蚀刻工艺以扩大初始沟槽。因此，可以使用具有稳定结构的光致抗蚀剂图案来形成初始沟槽。此后，使用具有基于其中形成初始沟槽的材料的组成的蚀刻溶液（例如硅衬底或绝缘膜）来扩大沟槽。因此，可以在扩大的沟槽中形成金属布线，隔离膜或接触件到期望的尺寸。

8. 发明申请

US20080166851A1 METAL-INSULATOR-METAL (MIM) CAPACITOR AND METHOD FOR FABRICATING THE SAME 审中-公开
标题翻译：金属绝缘子金属（MIM）电容器及其制造方法
公开(公告)号：US20080166851A1
公开(公告)日：2008-07-10
申请号：US12030476
申请日：2008-02-13
申请人： Uk-Sun HONG , Sang-Rok Hah , Hong-Seong Son
发明人： Uk-Sun HONG , Sang-Rok Hah , Hong-Seong Son
IPC分类号： H01L21/02
CPC分类号： H01G4/33 , H01L21/31144 , H01L23/5223 , H01L28/40 , H01L2924/0002 , H01L2924/00
摘要： The present invention discloses a metal-insulator-metal (MIM) capacitor and a method for fabricating the MIM capacitor, comprising forming a bottom insulation layer, a capacitor electrode material layer, and a hard mask material layer on a semiconductor substrate having a metal wire thereon; forming a hard mask by etching the hard mask material layer using a photosensitive mask; forming a capacitor electrode by etching the capacitor electrode material layer using the hard mask as an etching mask; and forming a top insulation layer on an entire surface of the semiconductor.
摘要翻译：本发明公开了一种金属绝缘体金属（MIM）电容器及其制造方法，包括在具有金属线的半导体基板上形成底部绝缘层，电容器电极材料层和硬掩模材料层上; 通过使用感光掩模蚀刻硬掩模材料层来形成硬掩模; 通过使用硬掩模作为蚀刻掩模来蚀刻电容器电极材料层来形成电容器电极; 以及在半导体的整个表面上形成顶部绝缘层。

9. 发明授权

US07183226B2 Method of forming a trench for use in manufacturing a semiconductor device 有权
标题翻译：形成用于制造半导体器件的沟槽的方法
公开(公告)号：US07183226B2
公开(公告)日：2007-02-27
申请号：US10673873
申请日：2003-09-30
申请人： Sung-Bae Lee , Sang-Rok Hah , Hong-Seong Son
发明人： Sung-Bae Lee , Sang-Rok Hah , Hong-Seong Son
IPC分类号： H01L21/302 , H01L21/461
CPC分类号： H01L27/10885 , H01L21/76229 , H01L21/76232 , H01L29/66181
摘要： A method for use in manufacturing a semiconductor device includes forming a photoresist pattern on a substrate, performing first etching process in which an initial trench is formed using the photoresist pattern as a mask, and performing second distinct etching process to enlarge the initial trench. Thus, the initial trench can be formed using the photoresist pattern having a stable structure. Thereafter, the trench is enlarged using an etching solution having a composition based on the material in which the initial trench is formed, e.g., a silicon substrate or an insulation film. Therefore, a metal wiring, an isolation film or a contact can be formed in the enlarged trench to desired dimensions.
摘要翻译：一种用于制造半导体器件的方法包括在衬底上形成光致抗蚀剂图案，执行第一蚀刻工艺，其中使用光致抗蚀剂图案作为掩模形成初始沟槽，并且执行第二不同的蚀刻工艺以扩大初始沟槽。因此，可以使用具有稳定结构的光致抗蚀剂图案来形成初始沟槽。此后，使用具有基于其中形成初始沟槽的材料的组成的蚀刻溶液（例如硅衬底或绝缘膜）来扩大沟槽。因此，可以在扩大的沟槽中形成金属布线，隔离膜或接触件到期望的尺寸。

10. 发明授权

US07026242B2 Method for filling a hole with a metal 有权
标题翻译：用金属填充孔的方法
公开(公告)号：US07026242B2
公开(公告)日：2006-04-11
申请号：US10802411
申请日：2004-03-16
申请人： Hong-Seong Son , Sang-Rok Hah , Il-Goo Kim , Jun-Hwan Oh
发明人： Hong-Seong Son , Sang-Rok Hah , Il-Goo Kim , Jun-Hwan Oh
IPC分类号： H01L21/4763
CPC分类号： H01L21/2885 , H01L21/76877
摘要： In a method for filling a hole with a metal, an insulating layer, a first mask layer and a second mask layer are successively formed on a semiconductor substrate. The first and second mask layers are etched using a photoresist pattern to form first and second masks. The first mask layer pattern is selectively etched using an etchant, the first mask layer pattern having a higher etching selectivity than the second layer pattern with respect to the etchant, to form a third mask layer pattern having a broadened opening. The insulating layer is etched using the second mask to form a hole in the insulating layer. A metal layer is formed in the hole and the third opening. The metal layer is planarized to form a metal plug buried in the hole without recesses or voids.
摘要翻译：在用金属填充孔的方法中，在半导体衬底上依次形成绝缘层，第一掩模层和第二掩模层。使用光致抗蚀剂图案蚀刻第一和第二掩模层以形成第一和第二掩模。使用蚀刻剂选择性地蚀刻第一掩模层图案，第一掩模层图案相对于蚀刻剂具有比第二层图案更高的蚀刻选择性，以形成具有加宽开口的第三掩模层图案。使用第二掩模蚀刻绝缘层，以在绝缘层中形成孔。在孔和第三开口中形成金属层。金属层被平坦化以形成埋在孔中的金属塞，而没有凹陷或空隙。

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