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1. 发明申请

US20070096782A1 Method and apparatus for fail-safe and restartable system clock generation 失效
标题翻译：用于故障安全和可重启系统时钟生成的方法和装置
公开(公告)号：US20070096782A1
公开(公告)日：2007-05-03
申请号：US11260563
申请日：2005-10-27
申请人： Hung Ngo , Gary Carpenter , Fadi Gebara , Jente Kuang
发明人： Hung Ngo , Gary Carpenter , Fadi Gebara , Jente Kuang
IPC分类号： H03L7/06
CPC分类号： H03L7/18 , G06F1/04
摘要： A method and apparatus for fail-safe and restartable system clock generation provides recovery from failures due to incorrect clock generator settings or from marginal clock distribution components. Clock failure is detected at a point along the clock distribution path between the output of the clock generator and the downstream circuits. If a clock failure is detected, a second clock, which may be the clock generator reference clock, is used to operate the downstream circuits. The clock generator, which may be a phase-lock loop, is then restarted, either with a predetermined loop filter voltage at which downstream circuits are guaranteed to operate, or with a divider setting on the output of the clock generator that reduces the frequency so that downstream circuits are guaranteed to operate. Parameters of the clock generator can thereby be reset and operating conditions determined before restoring the output of the clock generator to the downstream circuits.
摘要翻译：用于故障安全和可重新启动的系统时钟生成的方法和装置提供了由于错误的时钟发生器设置或边缘时钟分配组件导致的故障的恢复。在时钟发生器的输出与下游电路之间的时钟分配路径的某一点检测到时钟故障。如果检测到时钟故障，则可以使用可能是时钟发生器参考时钟的第二时钟来操作下游电路。时钟发生器可以是锁相环，然后重新启动下游电路被保证工作的预定环路滤波器电压，或者在时钟发生器的输出端上分频器设置，从而降低频率确保下游电路工作。因此，时钟发生器的参数可以在将时钟发生器的输出恢复到下行电路之前被确定并且确定操作条件。

2. 发明申请

US20070096770A1 Cascaded pass-gate test circuit with interposed split-output drive devices 失效
标题翻译：带有插入式分离输出驱动装置的级联传输门测试电路
公开(公告)号：US20070096770A1
公开(公告)日：2007-05-03
申请号：US11260571
申请日：2005-10-27
申请人： Ching-Te Chuang , Jente Kuang , Hung Ngo
发明人： Ching-Te Chuang , Jente Kuang , Hung Ngo
IPC分类号： H03K19/00
CPC分类号： G01R31/31725
摘要： A cascaded pass-gate test circuit including interposed split-output drive devices provides accurate measurement of critical timing parameters of pass gates. The rise time and fall time of signals passed through the pass gate can be separately measured in a ring oscillator or one-shot delay line configuration. Inverters or other buffer circuits are provided as drive devices to couple the pass gates in cascade. The final complementary tree in each drive device is split so that the only one of the output pull-down transistor or pull-up transistor is connected to the next pass gate input, while the other transistor is connected to the output of the pass gate. The result is that the state transition associated with the device connected to the pass gate input is dominant in the delay, while the other state transition is propagated directly to the output of the pass gate, bypassing the pass gate.
摘要翻译：包括插入式分离输出驱动装置的级联通过栅极测试电路提供对通孔的临界定时参数的精确测量。通过通过门的信号的上升时间和下降时间可以在环形振荡器或单稳态延迟线配置中单独测量。逆变器或其它缓冲电路被提供作为驱动装置来串联耦合通过门。每个驱动装置中的最终互补树被分开，使得输出下拉晶体管或上拉晶体管中的唯一一个连接到下一个通过栅极输入，而另一个晶体管连接到通过栅极的输出端。结果是，与连接到通过栅极输入的器件相关联的状态转变在延迟中是主要的，而另一个状态转变直接传播到通过栅极的输出，绕过通过栅极。

3. 发明申请

US20060103431A1 Dynamic logic circuit incorporating reduced leakage state-retaining devices 失效
标题翻译：动态逻辑电路结合了减少的泄漏状态保持装置
公开(公告)号：US20060103431A1
公开(公告)日：2006-05-18
申请号：US10992486
申请日：2004-11-18
申请人： Hung Ngo , Jente Kuang , Harmander Deogun , AJ Kleinosowski
发明人： Hung Ngo , Jente Kuang , Harmander Deogun , AJ Kleinosowski
IPC分类号： H03K19/096
CPC分类号： H03K19/0963 , H03K19/0016
摘要： A dynamic logic circuit incorporating reduced leakage state-retaining devices reduces power consumption of processors and other systems incorporating dynamic circuits. A keeper circuit provides a low leakage retention of the state of the output stage of the dynamic circuit so that an output circuit foot device can be disabled except when required for a transition in the output of the dynamic circuit. The keeper circuit includes a transistor having a smaller area than a corresponding transistor in the output circuit, thus reducing leakage through the gate of the output circuit when the keeper circuit is holding the output and the output circuit foot device is disabled. A self-clocked control of the output circuit foot device can be provided via a delayed version of the dynamic logic gate output, or may be provided by an external control circuit that generates a delayed version of the precharge clock or a multi-cycle signal.
摘要翻译：结合减少泄漏状态保持装置的动态逻辑电路降低了处理器和其他结合动态电路的系统的功耗。保持器电路提供动态电路的输出级的状态的低泄漏保持，使得输出电路脚装置可以被禁用，除非在动态电路的输出中需要转换。保持器电路包括具有比输出电路中的对应晶体管更小的面积的晶体管，从而当保持器电路保持输出并且输出电路脚器件被禁用时减小通过输出电路的栅极的泄漏。可以通过延迟版本的动态逻辑门输出来提供输出电路脚装置的自定时控制，或者可以由产生预充电时钟的延迟版本或多周期信号的外部控制电路提供。

4. 发明申请

US20070046323A1 Control circuitry for power gating virtual power supply rails at differing voltage potentials 失效
公开(公告)号：US20070046323A1
公开(公告)日：2007-03-01
申请号：US11211954
申请日：2005-08-25
申请人： Jente Kuang , Hung Ngo , Kevin Nowka
发明人： Jente Kuang , Hung Ngo , Kevin Nowka
IPC分类号： H03K17/16
CPC分类号： H03K19/0016
摘要： A single-stage level shifting circuit is used to interface control signals across the boundary between voltage domains with differing positive or ground voltage potentials Asserted states are determined by the difference between the positive voltages potentials and the ground potentials. A lower positive power supply potential is not used to turn OFF PFET coupled to a higher positive power supply potential. Likewise a higher ground power supply potential is not used to turn OF NFETs coupled to a power domain where is significant ground shift. The single stage level shifting circuit has keeper devices that hold asserted states using voltages within the power gated domain.

5. 发明申请

US20070040584A1 Dual-gate dynamic logic circuit with pre-charge keeper 有权
公开(公告)号：US20070040584A1
公开(公告)日：2007-02-22
申请号：US11204401
申请日：2005-08-16
申请人： Hung Ngo , Ching-Te Chuang , Keunwoo Kim , Jente Kuang , Kevin Nowka
发明人： Hung Ngo , Ching-Te Chuang , Keunwoo Kim , Jente Kuang , Kevin Nowka
IPC分类号： H03K19/096
CPC分类号： H03K19/0963
摘要： A dynamic logic gate has an asymmetrical dual-gate PFET device for charging a dynamic node during a pre-charge phase of a clock. A logic tree evaluates the dynamic node during an evaluate phase of the clock. The front gate of the asymmetrical dual-gate PFET device is coupled to the clock signal and the back gate is coupled to the ground potential of the power supply. When the clock is a logic zero both the front gate and the back gate are biased ON and the dynamic node charges with maximum current. The clock signal transitions to a logic one during the evaluation phase of the clock turning OFF the front gate. The back gate remains ON and the asymmetrical dual-gate PFET device operates as a keeper device with a current level sufficient to counter leakage on the dynamic node.

6. 发明申请

US20060082389A1 Dynamic logic circuit apparatus and method for reducing leakage power consumption via separate clock and output stage control 失效
标题翻译：用于通过单独的时钟和输出级控制来减少泄漏功耗的动态逻辑电路装置和方法
公开(公告)号：US20060082389A1
公开(公告)日：2006-04-20
申请号：US10992488
申请日：2004-11-18
申请人： Hung Ngo , Jente Kuang , Harmander Deogun , AJ Kleinosowski
发明人： Hung Ngo , Jente Kuang , Harmander Deogun , AJ Kleinosowski
IPC分类号： H03K19/096
CPC分类号： H03K19/0016 , H03K19/0966
摘要： A dynamic logic circuit apparatus and method for reducing leakage power consumption via separate clock and output stage control reduces power consumption of processors and other systems incorporating dynamic circuits. The power control signal may be a delayed version of the logic clock and turns on the output inverter foot device after the dynamic node has had sufficient time to evaluate, providing a fast evaluate time and reducing leakage through the inverter input when the foot device is off. Alternatively, a coarsely timed static power control signal may be used to control the inverter foot devices. The drains of the inverter foot devices can be commonly connected across multiple circuits, reducing the foot device total area.
摘要翻译：用于通过单独的时钟和输出级控制减少泄漏功率消耗的动态逻辑电路装置和方法降低了处理器和结合动态电路的其他系统的功耗。功率控制信号可以是逻辑时钟的延迟版本，并且在动态节点有足够的时间评估之后接通输出的反相器脚装置，当脚装置关闭时提供快速的评估时间并减少逆变器输入的泄漏。或者，可以使用粗定时静态功率控制信号来控制逆变器脚装置。逆变器脚踏装置的排水管可以通过多个回路共同连接，减少了脚踏装置总面积。

7. 发明申请

US20070189097A1 Methods and arrangements for enhancing power management systems in integrated circuits 有权
标题翻译：集成电路中增强电源管理系统的方法和安排
公开(公告)号：US20070189097A1
公开(公告)日：2007-08-16
申请号：US11352699
申请日：2006-02-13
申请人： Jente Kuang , Hung Ngo
发明人： Jente Kuang , Hung Ngo
IPC分类号： G11C5/14
CPC分类号： G11C11/417 , G11C5/14
摘要： Methods and arrangements to configure power management systems for integrated circuits are provided herein. A group of IC components that are functionally distinct or have mutually exclusive and/or quasi-mutually exclusive, (ME/QME) operating patterns (i.e. alternate or partially overlapping duty cycles) can be powered with a single power cell. An integrated circuit design tool can identified components in an integrated circuit design that have the ME/QME operating patterns. These cells can be collocated in close proximity to each other and power management system components can be placed in this area such that a multiple signal processing cells can share a single power line and a single power cell. Such a configuration can greatly reduce the size of a power management system for an integrated circuit.
摘要翻译：本文提供了为集成电路配置电源管理系统的方法和布置。功能上不同或具有互斥和/或准互斥（ME / QME）操作模式（即交替或部分重叠占空比）的一组IC组件可以由单个功率单元供电。集成电路设计工具可以识别具有ME / QME操作模式的集成电路设计中的组件。这些电池可以彼此靠近并置，并且功率管理系统组件可以放置在该区域中，使得多个信号处理单元可以共享单个电源线和单个功率单元。这种配置可以大大减小用于集成电路的电力管理系统的尺寸。

8. 发明申请

US20060055391A1 Power-gating cell for virtual power rail control 有权
标题翻译：用于虚拟电源轨控制的电源门控单元
公开(公告)号：US20060055391A1
公开(公告)日：2006-03-16
申请号：US10926597
申请日：2004-08-26
申请人： Jente Kuang , Jethro Law , Hung Ngo , Kevin Nowka
发明人： Jente Kuang , Jethro Law , Hung Ngo , Kevin Nowka
IPC分类号： F02P3/02
CPC分类号： H03K19/0016
摘要： Virtual power-gated cells (VPC) are configured with control circuitry for buffering control signals and a power-gated block (PGB) comprising two or more NFETs for virtual ground rail nodes and PFETs for virtual positive rail nodes. Each VPC has a control voltage input, a control voltage output, a node coupled to a power supply voltage potential, and a virtual power-gated node that is coupled and decoupled from the power supply potential in response to logic states on the control input. The control signals are buffered by non-power-gated inverters before being applied to the input of a PGB. VPCs may propagate a control signal that is in phase with or inverted from a corresponding control signal at the control input. VPCs may be cascaded to create virtual power rails in chains and power grids. The control signals are latched at the cell boundaries or latched in response to a clock signal.
摘要翻译：虚拟功率门控单元（VPC）配置有用于缓冲控制信号的控制电路和包括用于虚拟接地轨道节点的两个或更多个NFET的功率门控块（PGB），以及用于虚拟正轨节点的PFET。每个VPC具有控制电压输入，控制电压输出，耦合到电源电压电位的节点以及响应于控制输入上的逻辑状态与电源电位耦合和去耦合的虚拟电源门控节点。在施加到PGB的输入之前，控制信号由非电源门控的逆变器进行缓冲。 VPC可以传播与控制输入处的相应控制信号同相或反相的控制信号。 VPC可以级联以在链和电网中创建虚拟电源轨。控制信号在单元边界被锁存或响应于时钟信号锁存。

9. 发明申请

US20050127949A1 LOW SWITCHING POWER LIMITED SWITCH DYNAMIC LOGIC 失效
标题翻译：低开关电源有限公司开关动态逻辑
公开(公告)号：US20050127949A1
公开(公告)日：2005-06-16
申请号：US10733936
申请日：2003-12-11
申请人： Hung Ngo , Jente Kuang
发明人： Hung Ngo , Jente Kuang
IPC分类号： H03K3/356 , H03K19/096
CPC分类号： H03K19/0963 , H03K3/356121
摘要： An LSDL circuit is improved by having the data input function to control the pre-charging of the dynamic node. The clock signal no longer is coupled to the P channel FET used to pre-charge the dynamic node. Additionally an N channel FET (NFET) is added in parallel with the NFET coupled to the clock for evaluating the dynamic node. This NFET assures the dynamic node does not float when the data input is a logic one and the clock is a logic zero.
摘要翻译：通过具有数据输入功能来控制动态节点的预充电来改进LSDL电路。时钟信号不再耦合到用于对动态节点预充电的P沟道FET。此外，N沟道FET（NFET）与耦合到时钟的NFET并联并用于评估动态节点。该NFET保证当数据输入为逻辑1且时钟为逻辑0时，动态节点不浮动。

10. 发明申请

US20050102346A1 Computing carry-in bit to most significant bit carry save adder in current stage 失效
标题翻译：计算进位位到当前阶段的最高有效位进位保存加法器
公开(公告)号：US20050102346A1
公开(公告)日：2005-05-12
申请号：US10702992
申请日：2003-11-06
申请人： Wendy Belluomini , Ramyanshu Datta , Jente Kuang , Chandler McDowell , Robert Montoye , Hung Ngo
发明人： Wendy Belluomini , Ramyanshu Datta , Jente Kuang , Chandler McDowell , Robert Montoye , Hung Ngo
IPC分类号： G06F7/50 , G06F7/60
CPC分类号： G06F7/607
摘要： A 4-to-2 carry save adder with a reduction in the delay of outputting the sum and carry bits. The 4-to-2 carry save adder may include a lower order full order coupled to a higher order full adder. The carry save adder may further include a logic unit coupled to the higher order full adder where the logic unit is configured to generate a carry bit to be inputted to the higher order full adder that normally would be generated from the carry save adder located in the previous stage. By generating this carry bit (carry-in bit) in the current stage and not in the previous stage, the delay of the carry-in bit inputted to the higher order full adder is reduced thereby reducing the delay of outputting the sum and carry bits by the higher order full adder.
摘要翻译：一个4对2进位存储加法器，减少输出和输入位的延迟。 4对2进位存储加法器可以包括耦合到较高阶全加器的较低阶满载。进位保存加法器还可以包括耦合到高阶全加器的逻辑单元，其中逻辑单元被配置为产生要输入到通常将从位于该位置的进位保存加法器产生的高阶全加器的进位位前一阶段通过在当前阶段而不是在前一阶段生成该进位位（进位位），减少输入到较高阶全加器的进位位的延迟，从而减少输出和和输出位的延迟由高阶全加器。

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