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1. 发明授权

US09419108B2 Semiconductor structure and method for manufacturing the same 有权
标题翻译：半导体结构及其制造方法
公开(公告)号：US09419108B2
公开(公告)日：2016-08-16
申请号：US14406904
申请日：2012-08-17
申请人： Qingqing Liang , Huicai Zhong , Huilong Zhu , Chao Zhao , Tianchun Ye
发明人： Qingqing Liang , Huicai Zhong , Huilong Zhu , Chao Zhao , Tianchun Ye
IPC分类号： H01L29/66 , H01L29/78
CPC分类号： H01L29/66795 , H01L29/785 , H01L29/7855
摘要： One embodiment of present invention provides a method for manufacturing a semiconductor structure, which comprises: forming a gate stack on a semiconductor substrate and removing parts of the substrates situated on two sides of the gate stack; forming sidewall spacers on sidewalls of the gate stack and on sidewalls of the part of the substrate under the gate stack; forming doped regions in parts of the substrate on two sides of the gate stack, and forming a first dielectric layer to cover the entire semiconductor structure; selectively removing parts of the gate stack and parts of the first dielectric layer to form a channel region opening and source/drain region openings; forming a high K dielectric layer on sidewalls of the channel region opening; and implementing epitaxy process to form a continuous fin structure that spans across the channel region opening and the source/drain region openings.
摘要翻译：本发明的一个实施例提供了一种用于制造半导体结构的方法，其包括：在半导体衬底上形成栅极叠层并去除位于栅极叠层两侧的衬底的部分; 在所述栅极堆叠的侧壁上以及在所述栅极堆叠下的所述衬底的所述部分的侧壁上形成侧壁间隔物; 在所述栅极堆叠的两侧上在所述衬底的部分中形成掺杂区域，以及形成覆盖整个半导体结构的第一介电层; 选择性地去除所述栅极堆叠的部分和所述第一介电层的部分以形成沟道区域开口和源极/漏极区域开口; 在沟道区域开口的侧壁上形成高K电介质层; 并且实现外延工艺以形成跨越沟道区域开口和源极/漏极区域开口的连续翅片结构。

2. 发明申请

US20150236134A1 METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US20150236134A1
公开(公告)日：2015-08-20
申请号：US14412237
申请日：2012-07-18
申请人： Huicai Zhong , Qingqing Liang , Chao Zhao
发明人： Huicai Zhong , Qingqing Liang , Chao Zhao
IPC分类号： H01L29/66
CPC分类号： H01L29/66795 , H01L21/268 , H01L21/76283 , H01L29/665 , H01L29/785
摘要： A method of manufacturing a FinFET semiconductor device is provided, wherein the semiconductor fins are formed in a parallel arrangement which intersects the gates arranged in parallel. The polycrystalline silicon layer is deposited and then converted into a single crystal silicon layer such that the single crystal silicon layer and the semiconductor fins are integrated in essence, i.e., the source/drain region in the semiconductor fins is raised and the top area of the semiconductor fins is extended. Subsequently, the single crystal silicon layer above the top of the semiconductor fins is converted into a metal silicide so as to form a source/drain region contact. The source/drain region contact in the present invention has a larger area than that in a conventional FinFET, which decreases the contact resistance and facilitates the formation of a self-aligned metal plug in the follow-up process.
摘要翻译：提供一种制造FinFET半导体器件的方法，其中半导体鳍片形成为与并行布置的栅极相交的平行布置。沉积多晶硅层，然后转换为单晶硅层，使得单晶硅层和半导体鳍片本质上是集成的，即半导体鳍片中的源极/漏极区域被升高，并且顶部区域半导体鳍片延伸。随后，将半导体鳍片顶部上方的单晶硅层转换为金属硅化物，以形成源极/漏极区域接触。本发明中的源极/漏极区域的接触面积大于传统的FinFET的面积，这在以后的过程中降低了接触电阻并且有利于形成自对准的金属插塞。

3. 发明授权

US09012963B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US09012963B2
公开(公告)日：2015-04-21
申请号：US13501518
申请日：2011-11-18
申请人： Qingqing Liang , Miao Xu , Huilong Zhu , Huicai Zhong
发明人： Qingqing Liang , Miao Xu , Huilong Zhu , Huicai Zhong
IPC分类号： H01L29/66 , H01L29/786 , H01L29/49
CPC分类号： H01L29/78654 , H01L29/4908 , H01L29/78603 , H01L29/78648 , H01L29/78696
摘要： The present application discloses a semiconductor device comprising a source region and a drain region in an ultra-thin semiconductor layer; a channel region between the source region and the drain region in the ultra-thin semiconductor layer; a front gate stack above the channel region, the front gate comprising a front gate and a front gate dielectric between the front gate and the channel region; and a back gate stack below the channel region, the back gate stack comprising a back gate and a back gate dielectric between the back gate and the channel region, wherein the front gate is made of a high-Vt material, and the back gate is made of a low-Vt material. According to another embodiment, the front gate and the back gate are made of the same material, and the back gate is applied with a forward bias voltage during operation. The semiconductor device alleviates threshold voltage fluctuation due to varied thickness of the channel region by means of the back gate.
摘要翻译：本申请公开了一种半导体器件，其包括超薄半导体层中的源极区域和漏极区域; 在超薄半导体层中的源极区域和漏极区域之间的沟道区域; 在所述沟道区域上方的前栅极堆叠，所述前栅极包括在所述前栅极和所述沟道区域之间的前栅极和前栅极电介质; 以及在沟道区域下方的背栅极堆叠，所述背栅叠层包括在所述背栅极和沟道区域之间的背栅极和背栅电介质，其中所述前栅极由高Vt材料制成，并且所述背栅极由低Vt材料制成。根据另一实施例，前栅极和后栅极由相同的材料制成，并且背栅在工作期间被施加正偏压。半导体器件通过后栅极减小由沟道区域的厚度变化引起的阈值电压波动。

4. 发明授权

US08859378B2 Fin field-effect transistor and method for manufacturing the same 有权
标题翻译：翅片场效应晶体管及其制造方法
公开(公告)号：US08859378B2
公开(公告)日：2014-10-14
申请号：US13377141
申请日：2011-08-10
申请人： Qingqing Liang , Huicai Zhong , Huilong Zhu
发明人： Qingqing Liang , Huicai Zhong , Huilong Zhu
IPC分类号： H01L21/336 , H01L27/12 , H01L21/8234 , H01L21/84 , H01L27/088 , H01L29/66
CPC分类号： H01L27/1211 , H01L21/823431 , H01L21/845 , H01L27/0886 , H01L29/66545
摘要： Embodiments of the present invention disclose a method for manufacturing a Fin Field-Effect Transistor. When a fin is formed, a dummy gate across the fin is formed on the fin, a spacer is formed on sidewalls of the dummy gate, and a cover layer is formed on the first dielectric layer and on the fin outside the dummy gate and the spacer; then, an self-aligned and elevated source/drain region is formed at both sides of the dummy gate by the spacer, wherein the upper surfaces of the gate and the source/drain region are in the same plane. The upper surfaces of the gate and the source/drain region are in the same plane, making alignment of the contact plug easier; and the gate and the source/drain region are separated by the spacer, thereby improving alignment accuracy, solving inaccurate alignment of the contact plug, and improving device AC performance.
摘要翻译：本发明的实施例公开了一种制造Fin场效应晶体管的方法。当形成翅片时，在翅片上形成跨鳍片的虚拟栅极，在虚拟栅极的侧壁上形成间隔物，并且在第一介电层上形成覆盖层，并在模拟栅极外部形成覆盖层，间隔物然后，通过间隔件在虚拟栅极的两侧形成自对准和升高的源极/漏极区域，其中栅极和源极/漏极区域的上表面在同一平面内。栅极和源极/漏极区域的上表面位于相同的平面中，使接触插塞的对准更容易; 并且栅极和源极/漏极区域被间隔物分开，从而提高对准精度，解决接触插塞的不准确的对准以及提高器件AC性能。

5. 发明授权

US08748983B2 Embedded source/drain MOS transistor 有权
标题翻译：嵌入式源极/漏极MOS晶体管
公开(公告)号：US08748983B2
公开(公告)日：2014-06-10
申请号：US13380828
申请日：2011-08-12
申请人： Huicai Zhong , Chao Zhao , Qingqing Liang
发明人： Huicai Zhong , Chao Zhao , Qingqing Liang
IPC分类号： H01L27/12 , H01L21/70
CPC分类号： H01L29/0847 , H01L29/165 , H01L29/66636 , H01L29/78 , H01L29/7848
摘要： An embedded source/drain MOS transistor and a formation method thereof are provided. The embedded source/drain MOS transistor comprises: a semiconductor substrate; a gate structure on the semiconductor substrate; and a source/drain stack embedded in the semiconductor substrate at both sides of the gate structure with an upper surface of the source/drain stack being exposed, wherein the source/drain stack comprises a dielectric layer and a semiconductor layer above the dielectric layer. The present invention can cut off the path for the leakage current from the source region and the drain region to the semiconductor substrate, thereby reducing the leakage current from the source region and the drain region to the semiconductor substrate.
摘要翻译：提供一种嵌入式源极/漏极MOS晶体管及其形成方法。嵌入式源极/漏极MOS晶体管包括：半导体衬底; 半导体衬底上的栅极结构; 以及在源极/漏极叠层的上表面被暴露的栅极结构的两侧嵌入在半导体衬底中的源极/漏极堆叠，其中源极/漏极叠层包括电介质层和介电层上方的半导体层。本发明可以切断从源极区域和漏极区域到半导体衬底的漏电流的路径，从而减少从源极区域和漏极区域到半导体衬底的漏电流。

6. 发明申请

US20140124847A1 SEMICONDUCTOR DEVICES AND METHODS FOR MANUFACTURING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20140124847A1
公开(公告)日：2014-05-08
申请号：US14151441
申请日：2014-01-09
申请人： Huilong Zhu , Qingqing Liang , Huicai Zhong
发明人： Huilong Zhu , Qingqing Liang , Huicai Zhong
IPC分类号： H01L29/788 , H01L21/28 , H01L29/66
CPC分类号： H01L29/66825 , H01L21/28273 , H01L29/42324 , H01L29/7881
摘要： Semiconductor devices and methods for manufacturing the same are disclosed. In one aspect, the method comprises forming a first shielding layer on a substrate, and forming one of source and drain regions with the first shielding layer as a mask. Then, forming a second shielding layer on the substrate, and forming the other of the source and drain regions with the second shielding layer as a mask. Then, removing a portion of the second shielding layer which is next to the other of the source and drain regions. Lastly, forming a first gate dielectric layer, a floating gate layer, and a second gate dielectric layer, and forming a gate conductor as a spacer on a sidewall of a remaining portion of the second shielding layer.
摘要翻译：公开了半导体装置及其制造方法。一方面，该方法包括在衬底上形成第一屏蔽层，并且将第一屏蔽层作为掩模形成源区和漏区之一。然后，在衬底上形成第二屏蔽层，并且用第二屏蔽层作为掩模形成源区和漏区中的另一个。然后，去除位于源区和漏区另一个旁边的第二屏蔽层的一部分。最后，形成第一栅极电介质层，浮栅层和第二栅极电介质层，并在第二屏蔽层的剩余部分的侧壁上形成作为间隔物的栅极导体。

7. 发明申请

US20140027864A1 SEMICONDUCTOR DEVICES AND METHODS FOR MANUFACTURING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20140027864A1
公开(公告)日：2014-01-30
申请号：US13578872
申请日：2012-05-18
申请人： Huilong Zhu , Qingqing Liang , Huicai Zhong
发明人： Huilong Zhu , Qingqing Liang , Huicai Zhong
IPC分类号： H01L21/336 , H01L29/78
CPC分类号： H01L29/6659 , H01L29/66659 , H01L29/7835
摘要： Semiconductor devices and methods for manufacturing the same are disclosed. In one embodiment, the method comprises: forming a first shielding layer on a substrate, and forming a first spacer on a sidewall of the first shielding layer; forming one of source and drain regions with the first shielding layer and the first spacer as a mask; forming a second shielding layer on the substrate, and removing the first shielding layer; forming the other of the source and drain regions with the second shielding layer and the first spacer as a mask; removing at least a portion of the first spacer; and forming a gate dielectric layer, and forming a gate conductor in the form of spacer on a sidewall of the second shielding layer or on a sidewall of a remaining portion of the first spacer.
摘要翻译：公开了半导体装置及其制造方法。在一个实施例中，该方法包括：在衬底上形成第一屏蔽层，并在第一屏蔽层的侧壁上形成第一间隔物; 用第一屏蔽层和第一间隔件作为掩模形成源区和漏区之一; 在所述基板上形成第二屏蔽层，并移除所述第一屏蔽层; 用第二屏蔽层和第一间隔物作为掩模形成源区和漏区中的另一个; 去除所述第一间隔物的至少一部分; 以及形成栅极电介质层，以及在所述第二屏蔽层的侧壁或所述第一间隔物的剩余部分的侧壁上形成间隔物形式的栅极导体。

8. 发明申请

US20130228893A1 TRENCH ISOLATION STRUCTURE AND METHOD FOR FORMING THE SAME 有权
标题翻译： TRENCH隔离结构及其形成方法
公开(公告)号：US20130228893A1
公开(公告)日：2013-09-05
申请号：US13145301
申请日：2011-04-22
申请人： Huicai Zhong , Chao Zhao , Qingqing Liang
发明人： Huicai Zhong , Chao Zhao , Qingqing Liang
IPC分类号： H01L21/762 , H01L29/02
CPC分类号： H01L21/76224 , H01L21/76232 , H01L29/02
摘要： A trench isolation structure and a method of forming the same are provided. The trench isolation structure includes: a semiconductor substrate, and trenches formed on the surface of the semiconductor substrate and filled with a dielectric layer, wherein the material of the dielectric layer is a crystalline material. By using the present invention, the size of the divot can be reduced, and device performances can be improved.
摘要翻译：提供了沟槽隔离结构及其形成方法。沟槽隔离结构包括：半导体衬底和形成在半导体衬底的表面上并填充有电介质层的沟槽，其中电介质层的材料是结晶材料。通过使用本发明，可以减小纹路的尺寸，并且可以提高器件性能。

9. 发明申请

US20130037859A1 SEMICONDUCTOR DEVICE AND PROGRAMMING METHOD THEREOF 审中-公开
标题翻译：半导体器件及其编程方法
公开(公告)号：US20130037859A1
公开(公告)日：2013-02-14
申请号：US13321852
申请日：2011-08-12
申请人： Huicai Zhong , Qingqing Liang , Chao Zhao , Huilong Zhu
发明人： Huicai Zhong , Qingqing Liang , Chao Zhao , Huilong Zhu
IPC分类号： H01L27/10 , H01L21/326 , H01L23/522 , H01L29/788 , H01L29/92 , H01L23/525
CPC分类号： H01L23/481 , H01L23/525 , H01L23/5252 , H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device and a method for programming the same are provided. The semiconductor device comprises: a semiconductor substrate with an interconnect formed therein; a Through-Silicon Via (TSV) penetrating through the semiconductor substrate; and a programmable device which can be switched between on and off states, the TSV being connected to the interconnect by the programmable device. The present invention is beneficial in improving flexibility of TSV application.
摘要翻译：提供了半导体器件及其编程方法。半导体器件包括：其中形成有互连的半导体衬底; 穿透半导体衬底的透硅通孔（TSV）; 以及可以在导通和关断状态之间切换的可编程器件，TSV通过可编程器件连接到互连。本发明有利于提高TSV应用的灵活性。

10. 发明申请

US20120290998A1 DEVICE PERFORMANCE PREDICTION METHOD AND DEVICE STRUCTURE OPTIMIZATION METHOD 审中-公开
标题翻译：器件性能预测方法和器件结构优化方法
公开(公告)号：US20120290998A1
公开(公告)日：2012-11-15
申请号：US13320291
申请日：2011-04-26
申请人： Qingqing Liang , Huilong Zhu , Huicai Zhong , Meng Li
发明人： Qingqing Liang , Huilong Zhu , Huicai Zhong , Meng Li
IPC分类号： G06F17/50
CPC分类号： H01L22/20
摘要： The present application discloses a device performance prediction method and a device structure optimization method. According to an embodiment of the present invention, a set of structural parameters and/or process parameters for a semiconductor device constitutes a parameter point in a parameter space, and a behavioral model library is established with respect to a plurality of discrete predetermined parameter points in the parameter space, and the predetermined parameter points being associated with their respective performance indicator values in the behavioral model library. The device performance prediction method comprises: inputting a parameter point, called “predicting point”, whose performance indicator value is to be predicted; and if the predicting point has a corresponding record in the behavioral model library, outputting the corresponding performance indicator value as a predicted performance indicator value of the predicting point, or otherwise if there is no record corresponding to the predicting point in the behavioral model library, calculating a predicted performance indicator value of the predicting point by interpolation based on Delaunay triangulation.
摘要翻译：本申请公开了一种设备性能预测方法和设备结构优化方法。根据本发明的实施例，用于半导体器件的一组结构参数和/或工艺参数构成参数空间中的参数点，并且针对多个离散的预定参数点建立行为模型库参数空间以及与行为模型库中其各自的性能指标值相关联的预定参数点。设备性能预测方法包括：输入要预测其性能指标值的称为预测点的参数点; 并且如果预测点在行为模型库中具有对应的记录，则输出相应的表现指标值作为预测点的预测性能指标值，否则如果没有与行为模型库中的预测点相对应的记录，通过基于Delaunay三角测量的插值计算预测点的预测性能指标值。

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