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1. 发明申请

US20130241004A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20130241004A1
公开(公告)日：2013-09-19
申请号：US13520618
申请日：2012-04-11
申请人： Huaxiang Yin , Zuozhen Fu , Qiuxia Xu , Chao Zhao , Dapeng Chen
发明人： Huaxiang Yin , Zuozhen Fu , Qiuxia Xu , Chao Zhao , Dapeng Chen
IPC分类号： H01L27/088 , H01L21/8236
CPC分类号： H01L21/823807 , H01L21/823842 , H01L29/4966 , H01L29/517 , H01L29/518 , H01L29/66545 , H01L29/7845
摘要： The present invention discloses a semiconductor device, comprising substrates, a plurality of gate stack structures on the substrate, a plurality of gate spacer structures on both sides of each gate stack structure, a plurality of source and drain regions in the substrate on both sides of each gate spacer structure, the plurality of gate spacer structures comprising a plurality of first gate stack structures and a plurality of second gate stack structures, wherein each of the first gate stack structures comprises a first gate insulating layer, a first work function metal layer, a second work function metal diffusion blocking layer, and a gate filling layer; Each of the second gate stack structures comprises a second gate insulating layer, a first work function metal layer, a second work function metal layer, and a gate filling layer, characterized in that the first work function metal layer has a first stress, and the gate filling layer has a second stress. Two metal gate layers of different types and/or intensity of stress are formed, respectively, thus different stresses are applied to the channel regions of different MOSFETs effectively and accurately, the device carrier mobility is enhanced simply and efficiently, and the device performance is also enhanced.
摘要翻译：本发明公开了一种半导体器件，包括衬底，衬底上的多个栅极堆叠结构，在每个栅极堆叠结构的两侧上的多个栅极间隔结构，在衬底的两侧的多个源极和漏极区域每个栅极间隔结构，所述多个栅极间隔结构包括多个第一栅极堆叠结构和多个第二栅极堆叠结构，其中所述第一栅极堆叠结构中的每一个包括第一栅极绝缘层，第一功函数金属层，第二功函数金属扩散阻挡层和栅极填充层; 每个第二栅极堆叠结构包括第二栅极绝缘层，第一功函数金属层，第二功函数金属层和栅极填充层，其特征在于，第一功函数金属层具有第一应力，并且栅极填充层具有第二应力。形成不同类型和/或应力强度的两个金属栅极层，从而有效且准确地对不同MOSFET的沟道区域施加不同的应力，简单高效地提高器件载流子迁移率，器件性能也是增强。

2. 发明授权

US08994119B2 Semiconductor device with gate stacks having stress and method of manufacturing the same 有权
标题翻译：具有应力的栅极堆叠的半导体器件及其制造方法
公开(公告)号：US08994119B2
公开(公告)日：2015-03-31
申请号：US13520618
申请日：2012-04-11
申请人： Huaxiang Yin , Zuozhen Fu , Qiuxia Xu , Chao Zhao , Dapeng Chen
发明人： Huaxiang Yin , Zuozhen Fu , Qiuxia Xu , Chao Zhao , Dapeng Chen
IPC分类号： H01L27/088 , H01L21/8236 , H01L21/8238 , H01L29/49 , H01L29/78 , H01L29/51 , H01L29/66
CPC分类号： H01L21/823807 , H01L21/823842 , H01L29/4966 , H01L29/517 , H01L29/518 , H01L29/66545 , H01L29/7845
摘要： The present invention discloses a semiconductor device, comprising substrates, a plurality of gate stack structures on the substrate, a plurality of gate spacer structures on both sides of each gate stack structure, a plurality of source and drain regions in the substrate on both sides of each gate spacer structure, the plurality of gate spacer structures comprising a plurality of first gate stack structures and a plurality of second gate stack structures, wherein each of the first gate stack structures comprises a first gate insulating layer, a first work function metal layer, a second work function metal diffusion blocking layer, and a gate filling layer; Each of the second gate stack structures comprises a second gate insulating layer, a first work function metal layer, a second work function metal layer, and a gate filling layer, characterized in that the first work function metal layer has a first stress, and the gate filling layer has a second stress. Two metal gate layers of different types and/or intensity of stress are formed, respectively, thus different stresses are applied to the channel regions of different MOSFETs effectively and accurately, the device carrier mobility is enhanced simply and efficiently, and the device performance is also enhanced.
摘要翻译：本发明公开了一种半导体器件，包括衬底，衬底上的多个栅极堆叠结构，在每个栅极堆叠结构的两侧上的多个栅极间隔结构，在衬底的两侧的多个源极和漏极区域每个栅极间隔结构，所述多个栅极间隔结构包括多个第一栅极堆叠结构和多个第二栅极堆叠结构，其中所述第一栅极堆叠结构中的每一个包括第一栅极绝缘层，第一功函数金属层，第二功函数金属扩散阻挡层和栅极填充层; 每个第二栅极堆叠结构包括第二栅极绝缘层，第一功函数金属层，第二功函数金属层和栅极填充层，其特征在于，第一功函数金属层具有第一应力，并且栅极填充层具有第二应力。形成不同类型和/或应力强度的两个金属栅极层，从而有效且准确地对不同MOSFET的沟道区域施加不同的应力，简化高效地提高器件载流子迁移率，器件性能也增强。

3. 发明授权

US09384986B2 Dual-metal gate CMOS devices and method for manufacturing the same 有权
标题翻译：双金属栅极CMOS器件及其制造方法
公开(公告)号：US09384986B2
公开(公告)日：2016-07-05
申请号：US14396845
申请日：2012-05-17
申请人： Huaxiang Yin , Zuozhen Fu , Qiuxia Xu , Dapeng Chen
发明人： Huaxiang Yin , Zuozhen Fu , Qiuxia Xu , Dapeng Chen
IPC分类号： H01L21/28 , H01L29/66 , H01L21/8238 , H01L21/8234 , H01L27/092 , H01L29/51
CPC分类号： H01L21/28088 , H01L21/28 , H01L21/28008 , H01L21/28026 , H01L21/28044 , H01L21/28079 , H01L21/82345 , H01L21/823842 , H01L27/092 , H01L27/0928 , H01L29/517 , H01L29/66515 , H01L29/66545
摘要： A method for manufacturing a dual metal CMOS device comprising: forming a first type metal work function modulation layer in the first gate trench and the second gate trench; forming a second type work function metal diffusion source layer in the first gate trench and the second gate trench; forming a heat isolation layer that shields the region of the first type device; and thermally annealing the regions where the first type device and the second type device are located.
摘要翻译：一种用于制造双金属CMOS器件的方法，包括：在所述第一栅极沟槽和所述第二栅极沟槽中形成第一类型金属功函数调制层; 在所述第一栅极沟槽和所述第二栅极沟槽中形成第二类型功函数金属扩散源层; 形成屏蔽所述第一类型装置的区域的热隔离层; 并对第一类型器件和第二类型器件所在的区域进行热退火。

4. 发明申请

US20150102416A1 DUAL-METAL GATE CMOS DEVICES AND METHOD FOR MANUFACTURING THE SAME 有权
标题翻译：双金属门CMOS器件及其制造方法
公开(公告)号：US20150102416A1
公开(公告)日：2015-04-16
申请号：US14396845
申请日：2012-05-17
申请人： Huaxiang Yin , Zuozhen Fu , Qiuxia Xu , Dapeng Chen
发明人： Huaxiang Yin , Zuozhen Fu , Qiuxia Xu , Dapeng Chen
IPC分类号： H01L21/8234 , H01L29/51 , H01L27/092
CPC分类号： H01L21/28088 , H01L21/28 , H01L21/28008 , H01L21/28026 , H01L21/28044 , H01L21/28079 , H01L21/82345 , H01L21/823842 , H01L27/092 , H01L27/0928 , H01L29/517 , H01L29/66515 , H01L29/66545
摘要： A method for manufacturing a dual metal CMOS device comprising: forming a first type metal work function modulation layer in the first gate trench and the second gate trench; forming a second type work function metal diffusion source layer in the first gate trench and the second gate trench; forming a heat isolation layer that shields the region of the first type device; and thermally annealing the regions where the first type device and the second type device are located.
摘要翻译：一种用于制造双金属CMOS器件的方法，包括：在所述第一栅极沟槽和所述第二栅极沟槽中形成第一类型金属功函数调制层; 在所述第一栅极沟槽和所述第二栅极沟槽中形成第二类型功函数金属扩散源层; 形成屏蔽所述第一类型装置的区域的热隔离层; 并对第一类型器件和第二类型器件所在的区域进行热退火。

5. 发明申请

US20130240996A1 Semiconductor Device and Method of Manufacturing the Same 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：US20130240996A1
公开(公告)日：2013-09-19
申请号：US13520611
申请日：2012-04-11
申请人： Huaxiang Yin , Qiuxia Xu , Chao Zhao , Dapeng Chen
发明人： Huaxiang Yin , Qiuxia Xu , Chao Zhao , Dapeng Chen
IPC分类号： H01L27/088 , H01L21/336
CPC分类号： H01L21/823857 , H01L21/823842 , H01L29/4966 , H01L29/518 , H01L29/66545 , H01L29/66606 , H01L29/7833
摘要： The present invention discloses a semiconductor device, comprising a substrate, a plurality of gate stack structures on the substrate, a plurality of gate spacer structures on both sides of each gate stack structure, a plurality of source and drain regions in the substrate on both sides of each gate spacer structure, the plurality of gate spacer structures comprising a plurality of first gate stack structures and a plurality of second gate stack structures, wherein each of the first gate stack structures comprises a first gate insulating layer, a first work function metal layer, a second work function metal diffusion blocking layer, and a gate filling layer, the work function is close to the valence band (conduction band) edge; each of the second gate stack structures comprises a second gate insulating layer, a modified first work function metal layer, a second work function metal layer, and a gate filling layer, characterized in that the second work function metal layer comprises implanted work function-regulating doped ions, which are simultaneously diffused to the first work function layer below to regulate the threshold such that the work function of the gate is close to the valence band (conduction band) edge and is opposite the original first work function, to thereby regulate the work function accurately.
摘要翻译：本发明公开了一种半导体器件，包括衬底，衬底上的多个栅极堆叠结构，在每个栅极堆叠结构的两侧上的多个栅极间隔结构，在两侧的衬底中的多个源极和漏极区域所述多个栅极间隔结构包括多个第一栅极堆叠结构和多个第二栅极堆叠结构，其中所述第一栅极堆叠结构中的每一个包括第一栅极绝缘层，第一功函数金属层，第二功函数金属扩散阻挡层和栅极填充层，功函数接近价带（导带）边; 每个第二栅极堆叠结构包括第二栅极绝缘层，改性的第一功函数金属层，第二功函数金属层和栅极填充层，其特征在于，所述第二功函数金属层包括植入功函数调节掺杂离子，其同时扩散到下面的第一功函数层以调节阈值，使得栅极的功函数接近价带（导带）边缘并与原始第一功函数相反，从而调节工作功能准确。

6. 发明申请

US20140231923A1 SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME 审中-公开
标题翻译：半导体结构及其制造方法
公开(公告)号：US20140231923A1
公开(公告)日：2014-08-21
申请号：US14346537
申请日：2012-05-16
申请人： Huaxiang Yin , Qiuxia Xu , Dapeng Chen
发明人： Huaxiang Yin , Qiuxia Xu , Dapeng Chen
IPC分类号： H01L27/092 , H01L21/8238
CPC分类号： H01L27/092 , H01L21/76232 , H01L21/823807 , H01L29/165 , H01L29/665 , H01L29/66545 , H01L29/6659 , H01L29/66636 , H01L29/7834 , H01L29/7846 , H01L29/7848
摘要： The present invention provides a semiconductor structure, comprising: a substrate; a gate stack located on the substrate and comprising at least a gate dielectric layer and a gate electrode layer; source/drain regions, located in the substrate on both sides of the gate stack; an STI structure, located in the substrate on both sides of the source/drain regions, wherein the cross-section of the STI structure is trapezoidal, Sigma-shaped or inverted trapezoidal depending on the type of the semiconductor structure. Correspondingly, the present invention further to provides a method of manufacturing the semiconductor structure. In the present invention, STI structures having different shapes can be combined with different stress fillers to apply tensile stress or compressive stress laterally to the channel, which will produce a positive impact on the electron mobility of NMOS and the hole mobility of PMOS and increase the channel current of the device, thereby effectively improving the performance of the semiconductor structure.
摘要翻译：本发明提供一种半导体结构，包括：基板; 位于所述基板上并且至少包括栅极电介质层和栅极电极层的栅极堆叠; 源极/漏极区域，位于栅极堆叠两侧的衬底中; STI结构，位于源极/漏极区两侧的衬底中，其中根据半导体结构的类型，STI结构的横截面为梯形，Σ形或倒梯形。相应地，本发明还提供一种制造半导体结构的方法。在本发明中，具有不同形状的STI结构可以与不同的应力填料组合以向沟道侧向施加拉伸应力或压应力，这将对NMOS的电子迁移率和PMOS的空穴迁移率产生积极影响，并增加通道电流，从而有效地提高了半导体结构的性能。

7. 发明授权

US09276085B2 Semiconductor structure and method for manufacturing the same 有权
标题翻译：半导体结构及其制造方法
公开(公告)号：US09276085B2
公开(公告)日：2016-03-01
申请号：US14387143
申请日：2012-04-26
申请人： Huaxiang Yin , Xiaolong Ma , Changliang Qi , Qiuxia Xu , Dapeng Chen
发明人： Huaxiang Yin , Xiaolong Ma , Changliang Qi , Qiuxia Xu , Dapeng Chen
IPC分类号： H01L21/02 , H01L21/332 , H01L29/66 , H01L29/78
CPC分类号： H01L29/66575 , H01L29/6653 , H01L29/66545 , H01L29/6656 , H01L29/66636 , H01L29/7833
摘要： The present invention provides a semiconductor structure comprising a substrate; a gate stack on the substrate; a spacer on the sidewalls of the gate stack; a source/drain junction extension formed in the substrate on both sides of the gate stack by epitaxial growth; and a source/drain region in the substrate on both sides of the source/drain junction extension. Accordingly, the present invention also provides methods for manufacturing the semiconductor structure. The present invention can provide a source/drain junction extension with a high doping concentration and a low junction depth, thereby effectively improving the performance of the semiconductor structure.
摘要翻译：本发明提供一种包括基板的半导体结构; 衬底上的栅极堆叠; 在栅极堆叠的侧壁上的间隔物; 通过外延生长形成在栅极堆叠的两侧的衬底中的源极/漏极结延伸; 以及在源极/漏极结延伸部的两侧上的衬底中的源极/漏极区域。因此，本发明还提供了制造半导体结构的方法。本发明可以提供具有高掺杂浓度和低结深度的源极/漏极结延伸，从而有效地改善了半导体结构的性能。

8. 发明申请

US20140191335A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20140191335A1
公开(公告)日：2014-07-10
申请号：US13812941
申请日：2012-08-27
申请人： Huaxiang Yin , Changliang Qin , Xiaolong Ma , Qiuxia Xu , Dapeng Chen
发明人： Huaxiang Yin , Changliang Qin , Xiaolong Ma , Qiuxia Xu , Dapeng Chen
IPC分类号： H01L29/78 , H01L21/8234 , H01L27/088
CPC分类号： H01L29/7848 , H01L21/823412 , H01L21/823431 , H01L21/823807 , H01L21/823821 , H01L27/0886 , H01L29/66818 , H01L29/7845 , H01L29/785
摘要： The present invention discloses a semiconductor device, comprising a plurality of fins located on a substrate and extending along a first direction; a plurality of gate stack structures extending along a second direction and across each of the fins; a plurality of stress layers located in the fins on both sides of the gate stack structures and having a plurality of source and drain regions therein; a plurality of channel regions located in the fins below the gate stack structures; characterized in that the stress layers have connected parts in the fins and that the channel regions enclose the connected parts.
摘要翻译：本发明公开了一种半导体器件，包括位于基片上并沿着第一方向延伸的多个翅片; 多个栅极堆叠结构，沿着第二方向延伸并穿过每个所述散热片; 多个应力层，其位于所述栅极叠层结构的两侧的所述鳍片中，并且在其中具有多个源极和漏极区域; 多个通道区域，位于所述栅极叠层结构下方的鳍中; 其特征在于，应力层在翅片中具有连接部分，并且通道区域包围连接部分。

9. 发明授权

US08754482B2 Semiconductor device and manufacturing method thereof 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08754482B2
公开(公告)日：2014-06-17
申请号：US13394809
申请日：2011-11-25
申请人： Huaxiang Yin , Qiuxia Xu , Dapeng Chen
发明人： Huaxiang Yin , Qiuxia Xu , Dapeng Chen
IPC分类号： H01L21/8238 , H01L29/78
CPC分类号： H01L21/26506 , H01L21/26586 , H01L21/823807 , H01L21/823814 , H01L29/66636 , H01L29/7843 , H01L29/7847 , H01L29/7848
摘要： A semiconductor device and its manufacturing method are provided. The semiconductor device comprises: a semiconductor substrate of a first semiconductor material, a gate structure on the semiconductor substrate, a crystal lattice dislocation line in a channel under the gate structure for generating channel stress, wherein the crystal lattice dislocation line being at an angle to the channel.
摘要翻译：提供半导体器件及其制造方法。半导体器件包括：第一半导体材料的半导体衬底，半导体衬底上的栅极结构，用于产生沟道应力的栅极结构下方的沟道中的晶格位错线，其中晶格位错线与这个频道。

10. 发明授权

US08652891B1 Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08652891B1
公开(公告)日：2014-02-18
申请号：US13812867
申请日：2012-08-27
申请人： Huaxiang Yin , Changliang Qin , Qiuxia Xu , Dapeng Chen
发明人： Huaxiang Yin , Changliang Qin , Qiuxia Xu , Dapeng Chen
IPC分类号： H01L21/338
CPC分类号： H01L21/823431 , B82Y10/00 , B82Y40/00 , H01L21/823807 , H01L21/823814 , H01L21/823821 , H01L27/0886 , H01L29/0673 , H01L29/42392 , H01L29/66439 , H01L29/775 , H01L29/7853
摘要： The present invention discloses a semiconductor device, comprising a plurality of fins located on a substrate and extending along a first direction; a plurality of gate stack structures extending along a second direction and across each of the fins; a plurality of stress layers located in the fins on both sides of the gate stack structures and having a plurality of source and drain regions therein; a plurality of channel regions located between the plurality of source and drain regions along a first direction; characterized in that the plurality of gate stack structures enclose the plurality of channel regions. In accordance with the semiconductor device and the method of manufacturing the same of the present invention, an all-around nanowire metal multi-gate is formed in self-alignment by punching through and etching the fins at which the channel regions are located using a combination of the hard mask and the dummy gate, thus the device performance is enhanced.
摘要翻译：本发明公开了一种半导体器件，包括位于基片上并沿着第一方向延伸的多个翅片; 多个栅极堆叠结构，沿着第二方向延伸并穿过每个所述散热片; 多个应力层，其位于所述栅极叠层结构的两侧的所述鳍片中，并且在其中具有多个源极和漏极区域; 沿着第一方向位于所述多个源区和漏区之间的多个沟道区; 其特征在于，所述多个栅极堆叠结构包围所述多个沟道区域。根据本发明的半导体器件及其制造方法，通过使用组合来对通道区域所在的鳍进行冲压和蚀刻来形成全自动纳米线金属多栅极的自对准的硬掩模和伪栅极，从而提高了器件性能。

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