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1. 发明授权

US09276085B2 Semiconductor structure and method for manufacturing the same 有权
标题翻译：半导体结构及其制造方法
公开(公告)号：US09276085B2
公开(公告)日：2016-03-01
申请号：US14387143
申请日：2012-04-26
申请人： Huaxiang Yin , Xiaolong Ma , Changliang Qi , Qiuxia Xu , Dapeng Chen
发明人： Huaxiang Yin , Xiaolong Ma , Changliang Qi , Qiuxia Xu , Dapeng Chen
IPC分类号： H01L21/02 , H01L21/332 , H01L29/66 , H01L29/78
CPC分类号： H01L29/66575 , H01L29/6653 , H01L29/66545 , H01L29/6656 , H01L29/66636 , H01L29/7833
摘要： The present invention provides a semiconductor structure comprising a substrate; a gate stack on the substrate; a spacer on the sidewalls of the gate stack; a source/drain junction extension formed in the substrate on both sides of the gate stack by epitaxial growth; and a source/drain region in the substrate on both sides of the source/drain junction extension. Accordingly, the present invention also provides methods for manufacturing the semiconductor structure. The present invention can provide a source/drain junction extension with a high doping concentration and a low junction depth, thereby effectively improving the performance of the semiconductor structure.
摘要翻译：本发明提供一种包括基板的半导体结构; 衬底上的栅极堆叠; 在栅极堆叠的侧壁上的间隔物; 通过外延生长形成在栅极堆叠的两侧的衬底中的源极/漏极结延伸; 以及在源极/漏极结延伸部的两侧上的衬底中的源极/漏极区域。因此，本发明还提供了制造半导体结构的方法。本发明可以提供具有高掺杂浓度和低结深度的源极/漏极结延伸，从而有效地改善了半导体结构的性能。

2. 发明申请

US20150115374A1 SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME 有权
标题翻译：半导体结构及其制造方法
公开(公告)号：US20150115374A1
公开(公告)日：2015-04-30
申请号：US14387143
申请日：2012-04-26
申请人： Huaxiang Yin , Xiaolong Ma , Changliang Qi , Qiuxia Xu , Dapeng Chen
发明人： Huaxiang Yin , Xiaolong Ma , Changliang Qi , Qiuxia Xu , Dapeng Chen
IPC分类号： H01L29/66 , H01L29/78
CPC分类号： H01L29/66575 , H01L29/6653 , H01L29/66545 , H01L29/6656 , H01L29/66636 , H01L29/7833
摘要： The present invention provides a semiconductor structure comprising a substrate; a gate stack on the substrate; a spacer on the sidewalls of the gate stack; a source/drain junction extension formed in the substrate on both sides of the gate stack by epitaxial growth; and a source/drain region in the substrate on both sides of the source/drain junction extension. Accordingly, the present invention also provides methods for manufacturing the semiconductor structure. The present invention can provide a source/drain junction extension with a high doping concentration and a low junction depth, thereby effectively improving the performance of the semiconductor structure.
摘要翻译：本发明提供一种包括基板的半导体结构; 衬底上的栅极堆叠; 在栅极堆叠的侧壁上的间隔物; 通过外延生长形成在栅极堆叠的两侧的衬底中的源极/漏极结延伸; 以及在源极/漏极结延伸部的两侧上的衬底中的源极/漏极区域。因此，本发明还提供了制造半导体结构的方法。本发明可以提供具有高掺杂浓度和低结深度的源极/漏极结延伸，从而有效地改善了半导体结构的性能。

3. 发明授权

US09281398B2 Semiconductor structure and method for manufacturing the same 有权
标题翻译：半导体结构及其制造方法
公开(公告)号：US09281398B2
公开(公告)日：2016-03-08
申请号：US14355664
申请日：2012-07-03
申请人： Huaxiang Yin , Changliang Qin , Xiaolong Ma , Qiuxia Xu , Dapeng Chen
发明人： Huaxiang Yin , Changliang Qin , Xiaolong Ma , Qiuxia Xu , Dapeng Chen
IPC分类号： H01L21/336 , H01L29/78 , H01L29/66 , H01L29/10
CPC分类号： H01L29/7848 , H01L29/1037 , H01L29/1095 , H01L29/66636 , H01L29/7834
摘要： The present invention discloses a semiconductor device, which comprises a substrate, a gate stack structure on the substrate, a channel region in the substrate under the gate stack structure, and source and drain regions at both sides of the channel region, wherein there is a stressed layer under and at both sides of the channel region, in which the source and drain regions are formed. According to the semiconductor device and the method for manufacturing the same of the present invention, a stressed layer is formed at both sides of and under the channel region made of a silicon-based material so as to act on the channel region, thereby effectively increasing the carrier mobility of the channel region and improving the device performance.
摘要翻译：本发明公开了一种半导体器件，其包括衬底，衬底上的栅极堆叠结构，栅极堆叠结构下的衬底中的沟道区，以及沟道区两侧的源极和漏极区，其中存在在形成源极和漏极区的沟道区的下侧和两侧具有应力层。根据本发明的半导体器件及其制造方法，在由硅系材料制成的沟道区域的两侧和下方形成应力层，以作用于沟道区域，从而有效地增加通道区域的载波移动性和设备性能的提高。

4. 发明申请

US20140191335A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20140191335A1
公开(公告)日：2014-07-10
申请号：US13812941
申请日：2012-08-27
申请人： Huaxiang Yin , Changliang Qin , Xiaolong Ma , Qiuxia Xu , Dapeng Chen
发明人： Huaxiang Yin , Changliang Qin , Xiaolong Ma , Qiuxia Xu , Dapeng Chen
IPC分类号： H01L29/78 , H01L21/8234 , H01L27/088
CPC分类号： H01L29/7848 , H01L21/823412 , H01L21/823431 , H01L21/823807 , H01L21/823821 , H01L27/0886 , H01L29/66818 , H01L29/7845 , H01L29/785
摘要： The present invention discloses a semiconductor device, comprising a plurality of fins located on a substrate and extending along a first direction; a plurality of gate stack structures extending along a second direction and across each of the fins; a plurality of stress layers located in the fins on both sides of the gate stack structures and having a plurality of source and drain regions therein; a plurality of channel regions located in the fins below the gate stack structures; characterized in that the stress layers have connected parts in the fins and that the channel regions enclose the connected parts.
摘要翻译：本发明公开了一种半导体器件，包括位于基片上并沿着第一方向延伸的多个翅片; 多个栅极堆叠结构，沿着第二方向延伸并穿过每个所述散热片; 多个应力层，其位于所述栅极叠层结构的两侧的所述鳍片中，并且在其中具有多个源极和漏极区域; 多个通道区域，位于所述栅极叠层结构下方的鳍中; 其特征在于，应力层在翅片中具有连接部分，并且通道区域包围连接部分。

5. 发明申请

US20130256808A1 Semiconductor Device and Method of Manufacturing the Same 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20130256808A1
公开(公告)日：2013-10-03
申请号：US13520791
申请日：2012-04-11
申请人： Huaxiang Yin , xiaolong Ma , Qiuxia Xu , Dapeng Chen
发明人： Huaxiang Yin , xiaolong Ma , Qiuxia Xu , Dapeng Chen
IPC分类号： H01L27/088 , H01L21/8236
CPC分类号： H01L21/823807 , H01L29/7833 , H01L29/7843
摘要： The present invention discloses a semiconductor device, comprising a first MOSFET; a second MOSFET; a first stress liner covering the first MOSFET and having a first stress; a second stress liner covering the second MOSFET and having a second stress; wherein the second stress liner and/or the first stress liner comprise(s) a metal oxide. In accordance with the high-stress CMOS and method of manufacturing the same of the present invention, a stress layer comprising a metal oxide is formed selectively on PMOS and NMOS respectively by using a CMOS compatible process, whereby carrier mobility of the channel region is effectively enhanced and the performance of the device is improved.
摘要翻译：本发明公开了一种半导体器件，包括第一MOSFET; 第二个MOSFET; 覆盖所述第一MOSFET并具有第一应力的第一应力衬垫; 覆盖所述第二MOSFET并具有第二应力的第二应力衬垫; 其中所述第二应力衬垫和/或所述第一应力衬垫包括金属氧化物。根据本发明的高应力CMOS及其制造方法，通过使用CMOS兼容工艺，分别在PMOS和NMOS上选择性地形成包含金属氧化物的应力层，由此，沟道区域的载流子迁移率有效地增强了设备的性能，提高了设备性能。

6. 发明授权

US09548387B2 Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US09548387B2
公开(公告)日：2017-01-17
申请号：US13812941
申请日：2012-08-27
申请人： Huaxiang Yin , Changliang Qin , Xiaolong Ma , Qiuxia Xu , Dapeng Chen
发明人： Huaxiang Yin , Changliang Qin , Xiaolong Ma , Qiuxia Xu , Dapeng Chen
IPC分类号： H01L27/088 , H01L29/78 , H01L21/8234 , H01L21/8238 , H01L29/66
CPC分类号： H01L29/7848 , H01L21/823412 , H01L21/823431 , H01L21/823807 , H01L21/823821 , H01L27/0886 , H01L29/66818 , H01L29/7845 , H01L29/785
摘要： The present invention discloses a semiconductor device, comprising a plurality of fins located on a substrate and extending along a first direction; a plurality of gate stack structures extending along a second direction and across each of the fins; a plurality of stress layers located in the fins on both sides of the gate stack structures and having a plurality of source and drain regions therein; a plurality of channel regions located in the fins below the gate stack structures; characterized in that the stress layers have connected parts in the fins and that the channel regions enclose the connected parts.
摘要翻译：本发明公开了一种半导体器件，包括位于基片上并沿着第一方向延伸的多个翅片; 多个栅极堆叠结构，沿着第二方向延伸并穿过每个所述散热片; 多个应力层，其位于所述栅极叠层结构的两侧的所述鳍片中，并且在其中具有多个源极和漏极区域; 多个通道区域，位于所述栅极叠层结构下方的鳍中; 其特征在于，应力层在翅片中具有连接部分，并且通道区域包围连接部分。

7. 发明授权

US09312187B2 Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US09312187B2
公开(公告)日：2016-04-12
申请号：US13520791
申请日：2012-04-11
申请人： Huaxiang Yin , Xiaolong Ma , Qiuxia Xu , Dapeng Chen
发明人： Huaxiang Yin , Xiaolong Ma , Qiuxia Xu , Dapeng Chen
IPC分类号： H01L21/8238 , H01L29/78
CPC分类号： H01L21/823807 , H01L29/7833 , H01L29/7843
摘要： The present invention discloses a semiconductor device, comprising a first MOSFET; a second MOSFET; a first stress liner covering the first MOSFET and having a first stress; a second stress liner covering the second MOSFET and having a second stress; wherein the second stress liner and/or the first stress liner comprise(s) a metal oxide. In accordance with the high-stress CMOS and method of manufacturing the same of the present invention, a stress layer comprising a metal oxide is formed selectively on PMOS and NMOS respectively by using a CMOS compatible process, whereby carrier mobility of the channel region is effectively enhanced and the performance of the device is improved.
摘要翻译：本发明公开了一种半导体器件，包括第一MOSFET; 第二个MOSFET; 覆盖所述第一MOSFET并具有第一应力的第一应力衬垫; 覆盖所述第二MOSFET并具有第二应力的第二应力衬垫; 其中所述第二应力衬垫和/或所述第一应力衬垫包括金属氧化物。根据本发明的高应力CMOS及其制造方法，通过使用CMOS兼容工艺，分别在PMOS和NMOS上选择性地形成包含金属氧化物的应力层，由此，沟道区域的载流子迁移率有效地增强了设备的性能，提高了设备性能。

8. 发明申请

US20150179797A1 Semiconductor Structure and Method for Manufacturing the Same 有权
标题翻译：半导体结构及其制造方法
公开(公告)号：US20150179797A1
公开(公告)日：2015-06-25
申请号：US14355664
申请日：2012-07-03
申请人： Huaxiang Yin , Changliang Qin , Xiaolong Ma , Qiuxia Xu , Dapeng Chen
发明人： Huaxiang Yin , Changliang Qin , Xiaolong Ma , Qiuxia Xu , Dapeng Chen
IPC分类号： H01L29/78 , H01L29/10 , H01L29/66
CPC分类号： H01L29/7848 , H01L29/1037 , H01L29/1095 , H01L29/66636 , H01L29/7834
摘要： The present invention discloses a semiconductor device, which comprises a substrate, a gate stack structure on the substrate, a channel region in the substrate under the gate stack structure, and source and drain regions at both sides of the channel region, wherein there is a stressed layer under and at both sides of the channel region, in which the source and drain regions are formed. According to the semiconductor device and the method for manufacturing the same of the present invention, a stressed layer is formed at both sides of and under the channel region made of a silicon-based material so as to act on the channel region, thereby effectively increasing the carrier mobility of the channel region and improving the device performance.
摘要翻译：本发明公开了一种半导体器件，其包括衬底，衬底上的栅极堆叠结构，栅极堆叠结构下的衬底中的沟道区，以及沟道区两侧的源极和漏极区，其中存在在形成源极和漏极区的沟道区的下侧和两侧具有应力层。根据本发明的半导体器件及其制造方法，在由硅系材料制成的沟道区域的两侧和下方形成应力层，以作用于沟道区域，从而有效地增加通道区域的载波移动性和设备性能的提高。

9. 发明授权

US10068990B2 Method of manufacturing MOS transistor with stack of cascaded nanowires 有权
公开(公告)号：US10068990B2
公开(公告)日：2018-09-04
申请号：US14387830
申请日：2013-08-06
申请人： Huaxiang Yin , Xiaolong Ma , Weijia Xu , Qiuxia Xu , Huilong Zhu
发明人： Huaxiang Yin , Xiaolong Ma , Weijia Xu , Qiuxia Xu , Huilong Zhu
IPC分类号： H01L29/78 , H01L29/06 , H01L29/66 , H01L29/786 , H01L29/423
摘要： A MOS transistor with stacked nanowires and a method of manufacturing the same. The transistor may include a stack of cascaded nanowires extending in a first direction on a substrate; a gate stack extending in a second direction across the nanowire stack; source and drain regions disposed on opposite sides of the gate stack in the second direction; and a channel region constituted of the nanowire stack between the source and drain regions. The cascaded nanowires can be formed by repeated operations of etching back, and lateral etching and then filling of grooves, thereby increasing an effective width of the channel, increasing a total area of an effective conductive section, and thus improving a drive current.

10. 发明申请

US20140231923A1 SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME 审中-公开
标题翻译：半导体结构及其制造方法
公开(公告)号：US20140231923A1
公开(公告)日：2014-08-21
申请号：US14346537
申请日：2012-05-16
申请人： Huaxiang Yin , Qiuxia Xu , Dapeng Chen
发明人： Huaxiang Yin , Qiuxia Xu , Dapeng Chen
IPC分类号： H01L27/092 , H01L21/8238
CPC分类号： H01L27/092 , H01L21/76232 , H01L21/823807 , H01L29/165 , H01L29/665 , H01L29/66545 , H01L29/6659 , H01L29/66636 , H01L29/7834 , H01L29/7846 , H01L29/7848
摘要： The present invention provides a semiconductor structure, comprising: a substrate; a gate stack located on the substrate and comprising at least a gate dielectric layer and a gate electrode layer; source/drain regions, located in the substrate on both sides of the gate stack; an STI structure, located in the substrate on both sides of the source/drain regions, wherein the cross-section of the STI structure is trapezoidal, Sigma-shaped or inverted trapezoidal depending on the type of the semiconductor structure. Correspondingly, the present invention further to provides a method of manufacturing the semiconductor structure. In the present invention, STI structures having different shapes can be combined with different stress fillers to apply tensile stress or compressive stress laterally to the channel, which will produce a positive impact on the electron mobility of NMOS and the hole mobility of PMOS and increase the channel current of the device, thereby effectively improving the performance of the semiconductor structure.
摘要翻译：本发明提供一种半导体结构，包括：基板; 位于所述基板上并且至少包括栅极电介质层和栅极电极层的栅极堆叠; 源极/漏极区域，位于栅极堆叠两侧的衬底中; STI结构，位于源极/漏极区两侧的衬底中，其中根据半导体结构的类型，STI结构的横截面为梯形，Σ形或倒梯形。相应地，本发明还提供一种制造半导体结构的方法。在本发明中，具有不同形状的STI结构可以与不同的应力填料组合以向沟道侧向施加拉伸应力或压应力，这将对NMOS的电子迁移率和PMOS的空穴迁移率产生积极影响，并增加通道电流，从而有效地提高了半导体结构的性能。

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