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1. 发明授权

US07855143B2 Interconnect capping layer and method of fabrication 有权
标题翻译：互连覆盖层和制造方法
公开(公告)号：US07855143B2
公开(公告)日：2010-12-21
申请号：US11614996
申请日：2006-12-22
申请人： Huang Liu , Bangun Indajang , Wei Lu
发明人： Huang Liu , Bangun Indajang , Wei Lu
IPC分类号： H01L21/4763
CPC分类号： H01L21/76867 , H01L21/02074 , H01L21/76846 , H01L21/76847 , H01L21/76849 , H01L21/76856
摘要： The present invention relates to an interconnect capping layer and a method of fabricating a capping layer for an interconnect. In particular, but not exclusively, the invention relates to a capping layer for a copper interconnect used to interconnect elements in an integrated circuit. Embodiments of the invention provide a method of fabricating a capping layer for an interconnect in an integrated circuit, comprising the steps of: forming an interconnect comprising upper and lower lateral surfaces; forming a lateral diffusion stop layer between said lateral surfaces; and forming a capping layer.
摘要翻译：本发明涉及一种互连覆盖层和用于互连制造覆盖层的方法。特别地，但不排他地，本发明涉及一种覆盖层为用于互连在集成电路元件铜互连。本发明的实施例提供一种制造用于集成电路中的互连的覆盖层的方法，包括以下步骤：形成包括上侧表面和下侧表面的互连; 在所述侧表面之间形成横向扩散停止层; 并形成覆盖层。

2. 发明申请

US20080150137A1 Interconnect Capping Layer and Method of Fabrication 有权
标题翻译：互连封盖层和制造方法
公开(公告)号：US20080150137A1
公开(公告)日：2008-06-26
申请号：US11614996
申请日：2006-12-22
申请人： Huang LIU , Bangun Indajang , Wei Lu
发明人： Huang LIU , Bangun Indajang , Wei Lu
IPC分类号： H01L23/52 , H01L21/4763
CPC分类号： H01L21/76867 , H01L21/02074 , H01L21/76846 , H01L21/76847 , H01L21/76849 , H01L21/76856
摘要： The present invention relates to an interconnect capping layer and a method of fabricating a capping layer for an interconnect. In particular, but not exclusively, the invention relates to a capping layer for a copper interconnect used to interconnect elements in an integrated circuit. Embodiments of the invention provide a method of fabricating a capping layer for an interconnect in an integrated circuit, comprising the steps of: forming an interconnect comprising upper and lower lateral surfaces; forming a lateral diffusion stop layer between said lateral surfaces; and forming a capping layer.
摘要翻译：本发明涉及一种互连覆盖层和用于互连制造覆盖层的方法。特别地，但不排他地，本发明涉及一种覆盖层为用于互连在集成电路元件铜互连。本发明的实施例提供一种制造用于集成电路中的互连的覆盖层的方法，包括以下步骤：形成包括上侧表面和下侧表面的互连; 在所述侧表面之间形成横向扩散停止层; 并形成覆盖层。

3. 发明申请

US20090325359A1 INTEGRATED CIRCUIT SYSTEM EMPLOYING A MODIFIED ISOLATION STRUCTURE 审中-公开
标题翻译：采用改进隔离结构的集成电路系统
公开(公告)号：US20090325359A1
公开(公告)日：2009-12-31
申请号：US12165624
申请日：2008-06-30
申请人： Huang Liu , Johnny Widodo , Jeff Shu , Luona Goh Loh Nah , Jack Cheng , Wei Lu , Jingze Tian , Xuesong Rao
发明人： Huang Liu , Johnny Widodo , Jeff Shu , Luona Goh Loh Nah , Jack Cheng , Wei Lu , Jingze Tian , Xuesong Rao
IPC分类号： H01L21/762
CPC分类号： H01L21/76229
摘要： An integrated circuit system that includes: providing a substrate; forming a trench within the substrate; forming a liner on a sidewall of the trench; and forming a dielectric material at a trench bottom with a dielectric width dimension that exceeds that of a width dimension of the trench.
摘要翻译：一种集成电路系统，包括：提供衬底; 在衬底内形成沟槽; 在沟槽的侧壁上形成衬垫; 以及在介质宽度尺寸超过沟槽的宽度尺寸的沟槽底部形成电介质材料。

4. 发明授权

US07892900B2 Integrated circuit system employing sacrificial spacers 有权
标题翻译：采用牺牲间隔物的集成电路系统
公开(公告)号：US07892900B2
公开(公告)日：2011-02-22
申请号：US12098751
申请日：2008-04-07
申请人： Huang Liu , Wei Lu , Hai Cong , Alex K. H. See , Hui Peng Koh , Meisheng Zhou
发明人： Huang Liu , Wei Lu , Hai Cong , Alex K. H. See , Hui Peng Koh , Meisheng Zhou
IPC分类号： H01L21/00 , H01L21/84 , H01L21/336
CPC分类号： H01L21/823807 , H01L21/823864 , H01L29/7843
摘要： An integrated circuit system that includes: providing a substrate including a first device and a second device; configuring the first device and the second device to include a first spacer, a first liner made from a first dielectric layer, and a second spacer made from a sacrificial spacer material; forming a second dielectric layer over the integrated circuit system; forming a first device source/drain and a second device source/drain adjacent the second spacer and through the second dielectric layer; removing the second spacer without damaging the substrate; forming a third dielectric layer over the integrated circuit system before annealing; and forming a fourth dielectric layer over the integrated circuit system that promotes stress within the channel of the first device, the second device, or a combination thereof.
摘要翻译：一种集成电路系统，包括：提供包括第一装置和第二装置的基板; 配置第一器件和第二器件以包括第一间隔物，由第一介电层制成的第一衬垫和由牺牲间隔物材料制成的第二间隔物; 在所述集成电路系统上形成第二电介质层; 形成第一器件源极/漏极和邻近第二间隔物并通过第二介电层的第二器件源极/漏极; 去除所述第二间隔物而不损坏所述基底; 在退火之前在集成电路系统上形成第三电介质层; 以及在所述集成电路系统上形成促进所述第一装置，所述第二装置或其组合的通道内的应力的第四电介质层。

5. 发明授权

US07745320B2 Method for reducing silicide defects in integrated circuits 有权
标题翻译：降低集成电路中硅化物缺陷的方法
公开(公告)号：US07745320B2
公开(公告)日：2010-06-29
申请号：US12124177
申请日：2008-05-21
申请人： Jeff Jianhui Ye , Huang Liu , Alex K H See , Wei Lu , Hai Cong , Hui Peng Koh , Mei Sheng Zhou , Liang Choo Hsia
发明人： Jeff Jianhui Ye , Huang Liu , Alex K H See , Wei Lu , Hai Cong , Hui Peng Koh , Mei Sheng Zhou , Liang Choo Hsia
IPC分类号： H01L29/00 , H01L21/311
CPC分类号： H01L29/665 , H01L21/31116 , H01L29/6653 , H01L29/78
摘要： A method for forming silicide contacts in integrated circuits (ICs) is described. A spacer pull-back etch is performed during the salicidation process to reduce the stress between the spacer and source/drain silicide contact at the spacer undercut. This prevents the propagation of surface defects into the substrate, thereby minimizing the occurrence of silicide pipe defects. The spacer pull-back etch can be performed after a first annealing step to form the silicide contacts.
摘要翻译：描述了在集成电路（IC）中形成硅化物触点的方法。在水解过程期间进行间隔物拉回蚀刻以减少间隔物与间隔物底切下的源/漏硅化物接触之间的应力。这样可以防止表面缺陷进入衬底，从而使硅化物管缺陷的发生最小化。间隔物拉回蚀刻可以在第一退火步骤之后进行以形成硅化物接触。

6. 发明申请

US20090250762A1 INTEGRATED CIRCUIT SYSTEM EMPLOYING SACRIFICIAL SPACERS 有权
标题翻译：集成电路系统采用真空间隔
公开(公告)号：US20090250762A1
公开(公告)日：2009-10-08
申请号：US12098751
申请日：2008-04-07
申请人： Huang Liu , Wei Lu , Hai Cong , Alex K.H. See , Hui Peng Koh , Meisheng Zhou
发明人： Huang Liu , Wei Lu , Hai Cong , Alex K.H. See , Hui Peng Koh , Meisheng Zhou
IPC分类号： H01L21/8238
CPC分类号： H01L21/823807 , H01L21/823864 , H01L29/7843
摘要： An integrated circuit system that includes: providing a substrate including a first device and a second device; configuring the first device and the second device to include a first spacer, a first liner made from a first dielectric layer, and a second spacer made from a sacrificial spacer material; forming a second dielectric layer over the integrated circuit system; forming a first device source/drain and a second device source/drain adjacent the second spacer and through the second dielectric layer; removing the second spacer without damaging the substrate; forming a third dielectric layer over the integrated circuit system before annealing; and forming a fourth dielectric layer over the integrated circuit system that promotes stress within the channel of the first device, the second device, or a combination thereof.
摘要翻译：一种集成电路系统，包括：提供包括第一装置和第二装置的基板; 配置第一器件和第二器件以包括第一间隔物，由第一介电层制成的第一衬垫和由牺牲间隔物材料制成的第二间隔物; 在所述集成电路系统上形成第二电介质层; 形成第一器件源极/漏极和邻近第二间隔物并通过第二介电层的第二器件源极/漏极; 去除所述第二间隔物而不损坏所述基底; 在退火之前在集成电路系统上形成第三电介质层; 以及在所述集成电路系统上形成促进所述第一装置，所述第二装置或其组合的通道内的应力的第四电介质层。

7. 发明授权

US08354347B2 Method of forming high-k dielectric stop layer for contact hole opening 有权
公开(公告)号：US08354347B2
公开(公告)日：2013-01-15
申请号：US11953881
申请日：2007-12-11
申请人： Jianhui Ye , Huang Liu , Alex K H See , Wei Lu , Chun Hui Low , Chim Seng Seet , Mei Sheng Zhou , Liang Choo Hsia
发明人： Jianhui Ye , Huang Liu , Alex K H See , Wei Lu , Chun Hui Low , Chim Seng Seet , Mei Sheng Zhou , Liang Choo Hsia
IPC分类号： H01L21/461
CPC分类号： H01L21/76832 , H01L21/76895 , H01L21/76897
摘要： A composite etch stop layer which comprises primary and secondary stop layers is used to form contacts in a dielectric layer to contact regions in a substrate. The secondary etch stop layer includes a high-k dielectric material to achieve high etch selectivity with the dielectric layer during contact formation. The secondary stop layer is removed to expose the contact regions. Removal of the secondary stop layer is achieved with high selectivity to the materials therebelow.

8. 发明授权

US08035201B2 Reliable interconnection 有权
标题翻译：可靠的互连
公开(公告)号：US08035201B2
公开(公告)日：2011-10-11
申请号：US12473232
申请日：2009-05-27
申请人： Huang Liu , Jack Cheng , Wei Lu , Yihua Wang , Meisheng Zhou
发明人： Huang Liu , Jack Cheng , Wei Lu , Yihua Wang , Meisheng Zhou
IPC分类号： H01L23/00
CPC分类号： H01L21/02167 , H01L21/02211 , H01L21/02274 , H01L21/02348 , H01L21/3148 , H01L21/3185 , H01L21/76825 , H01L21/76829
摘要： Embodiments relate to a method for forming reliable interconnects by the use of a device layer that can serve as a barrier or an etch stop layer, among other applications. The device layer is UV resistant in that its dielectric constant and stress remain stable or relatively stable when subjected to UV curing.
摘要翻译：实施例涉及通过使用可用作阻挡层或蚀刻停止层的器件层形成可靠互连的方法以及其它应用。器件层是抗紫外线的，因为它的介电常数和应力在进行紫外线固化时保持稳定或相对稳定。

9. 发明授权

US08013372B2 Integrated circuit including a stressed dielectric layer with stable stress 有权
标题翻译：集成电路包括具有稳定应力的应力介电层
公开(公告)号：US08013372B2
公开(公告)日：2011-09-06
申请号：US12062535
申请日：2008-04-04
申请人： Huang Liu , Jeff Shu , Luona Goh , Wei Lu
发明人： Huang Liu , Jeff Shu , Luona Goh , Wei Lu
IPC分类号： H01L21/336
CPC分类号： H01L29/78 , H01L21/76224 , H01L29/665 , H01L29/7843
摘要： A method for fabricating an integrated circuit is provided. The method includes providing a substrate having an active region and an opening in the substrate adjacent to the active region. The opening is filled with a dielectric material so as to provide an isolation region in the substrate. A transistor is also formed in the active region and a pre-metal dielectric layer formed over the substrate and transistor. At least one of the dielectric layer in isolation region or the pre-metal dielectric layer includes a stressed O3 TEOS oxide having a stress retaining dopant, wherein the concentration of the stress retaining dopant is sufficient to retard stress degradation of the O3 TEOS oxide.
摘要翻译：提供一种制造集成电路的方法。该方法包括提供具有活性区域和邻近活性区域的衬底中的开口的衬底。开口填充有电介质材料，以便在衬底中提供隔离区。晶体管也形成在有源区和形成在衬底和晶体管上的预金属介电层。隔离区域或预金属介电层中的介电层中的至少一个包括具有应力保持掺杂剂的应力O 3 TEOS氧化物，其中应力保留掺杂剂的浓度足以延缓O 3 TEOS氧化物的应力降解。

10. 发明授权

US07960283B2 Method for reducing silicide defects in integrated circuits 有权
标题翻译：降低集成电路中硅化物缺陷的方法
公开(公告)号：US07960283B2
公开(公告)日：2011-06-14
申请号：US12825325
申请日：2010-06-28
申请人： Jeff Jianhui Ye , Huang Liu , Alex K H See , Wei Lu , Hai Cong , Hui Peng Koh , Mei Sheng Zhou , Liang Choo Hsia
发明人： Jeff Jianhui Ye , Huang Liu , Alex K H See , Wei Lu , Hai Cong , Hui Peng Koh , Mei Sheng Zhou , Liang Choo Hsia
IPC分类号： H01L21/28 , H01L21/311
CPC分类号： H01L29/665 , H01L21/31116 , H01L29/6653 , H01L29/78
摘要： A method for forming silicide contacts in integrated circuits (ICs) is described. A spacer pull-back etch is performed during the salicidation process to reduce the stress between the spacer and source/drain silicide contact at the spacer undercut. This prevents the propagation of surface defects into the substrate, thereby minimizing the occurrence of silicide pipe defects. The spacer pull-back etch can be performed after a first annealing step to form the silicide contacts.
摘要翻译：描述了在集成电路（IC）中形成硅化物触点的方法。在水解过程期间进行间隔物拉回蚀刻以减少间隔物与间隔物底切下的源/漏硅化物接触之间的应力。这样可以防止表面缺陷进入衬底，从而使硅化物管缺陷的发生最小化。间隔物拉回蚀刻可以在第一退火步骤之后进行以形成硅化物接触。

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