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1. 发明申请

US20090325359A1 INTEGRATED CIRCUIT SYSTEM EMPLOYING A MODIFIED ISOLATION STRUCTURE 审中-公开
标题翻译：采用改进隔离结构的集成电路系统
公开(公告)号：US20090325359A1
公开(公告)日：2009-12-31
申请号：US12165624
申请日：2008-06-30
申请人： Huang Liu , Johnny Widodo , Jeff Shu , Luona Goh Loh Nah , Jack Cheng , Wei Lu , Jingze Tian , Xuesong Rao
发明人： Huang Liu , Johnny Widodo , Jeff Shu , Luona Goh Loh Nah , Jack Cheng , Wei Lu , Jingze Tian , Xuesong Rao
IPC分类号： H01L21/762
CPC分类号： H01L21/76229
摘要： An integrated circuit system that includes: providing a substrate; forming a trench within the substrate; forming a liner on a sidewall of the trench; and forming a dielectric material at a trench bottom with a dielectric width dimension that exceeds that of a width dimension of the trench.
摘要翻译：一种集成电路系统，包括：提供衬底; 在衬底内形成沟槽; 在沟槽的侧壁上形成衬垫; 以及在介质宽度尺寸超过沟槽的宽度尺寸的沟槽底部形成电介质材料。

2. 发明授权

US07144828B2 He treatment to improve low-k adhesion property 有权
标题翻译：他处理提高低k粘附性能
公开(公告)号：US07144828B2
公开(公告)日：2006-12-05
申请号：US10768918
申请日：2004-01-30
申请人： Wei Lu , Luona Goh Loh Nah , John Sudijono
发明人： Wei Lu , Luona Goh Loh Nah , John Sudijono
IPC分类号： H01L21/42 , H01L21/324 , H01L21/477
CPC分类号： H01L21/02315 , H01L21/02126 , H01L21/02164 , H01L21/02167 , H01L21/0217 , H01L21/02304 , H01L21/02318 , H01L21/3105 , H01L21/31058 , H01L21/3121 , H01L21/3148 , H01L21/76801 , H01L21/76807 , H01L21/76826
摘要： A method of improving adhesion of low dielectric constant films to other dielectric films is described. A low dielectric constant material layer is deposited on a substrate. The low dielectric constant material layer is treated with helium plasma. An overlying layer is deposited on the low dielectric constant material layer wherein there is good adhesion between the low dielectric constant material layer and the overlying layer.
摘要翻译：描述了改善低介电常数膜对其它电介质膜的附着力的方法。低介电常数材料层沉积在基片上。用氦等离子体处理低介电常数材料层。在低介电常数材料层上沉积上覆层，其中在低介电常数材料层和上覆层之间存在良好的粘合性。

3. 发明授权

US07566656B2 Method and apparatus for providing void structures 有权
标题翻译：提供空隙结构的方法和装置
公开(公告)号：US07566656B2
公开(公告)日：2009-07-28
申请号：US11615004
申请日：2006-12-22
申请人： Huang Liu , Johnny Widodo , Wei Lu
发明人： Huang Liu , Johnny Widodo , Wei Lu
IPC分类号： H01L23/485
CPC分类号： H01L21/7682 , H01L21/76807 , H01L21/76831 , H01L2221/1063
摘要： The present invention relates to integrated circuits. In particular, but not exclusively, the invention relates to a method and apparatus for connecting elements of integrated circuits with interconnects having one or more voids formed between adjacent interconnects. Embodiments of the invention provide apparatus for connecting elements in an integrated circuit device, comprising: at least one interconnect comprising one or more sidewalls; an interconnect sidewall spacer element arranged to provide structural support to the interconnect and formed on at least one of the interconnect sidewalls; and at least one void adjacent said interconnect and extending from the sidewall spacer element.
摘要翻译：集成电路技术领域本发明涉及集成电路。具体而非排他地，本发明涉及用于连接具有在相邻互连件之间形成的一个或多个空隙的互连的集成电路的元件的方法和装置。本发明的实施例提供了用于连接集成电路器件中的元件的装置，包括：包括一个或多个侧壁的至少一个互连件; 互连侧壁间隔件，布置成提供对所述互连件的结构支撑并形成在所述互连侧壁中的至少一个上; 以及邻近所述互连并且从侧壁间隔元件延伸的至少一个空隙。

4. 发明申请

US20080153252A1 Method And Apparatus For Providing Void Structures 有权
标题翻译：提供空隙结构的方法和装置
公开(公告)号：US20080153252A1
公开(公告)日：2008-06-26
申请号：US11615004
申请日：2006-12-22
申请人： Huang LIU , Johnny Widodo , Wei Lu
发明人： Huang LIU , Johnny Widodo , Wei Lu
IPC分类号： H01L21/764
CPC分类号： H01L21/7682 , H01L21/76807 , H01L21/76831 , H01L2221/1063
摘要： The present invention relates to integrated circuits. In particular, but not exclusively, the invention relates to a method and apparatus for connecting elements of integrated circuits with interconnects having one or more voids formed between adjacent interconnects. Embodiments of the invention provide apparatus for connecting elements in an integrated circuit device, comprising: at least one interconnect comprising one or more sidewalls; an interconnect sidewall spacer element arranged to provide structural support to the interconnect and formed on at least one of the interconnect sidewalls; and at least one void adjacent said interconnect and extending from the sidewall spacer element.
摘要翻译：集成电路技术领域本发明涉及集成电路。具体而非排他地，本发明涉及用于连接具有在相邻互连件之间形成的一个或多个空隙的互连的集成电路的元件的方法和装置。本发明的实施例提供了用于连接集成电路器件中的元件的装置，包括：包括一个或多个侧壁的至少一个互连件; 互连侧壁间隔件，布置成提供对所述互连件的结构支撑并形成在所述互连侧壁中的至少一个上; 以及邻近所述互连并且从侧壁间隔元件延伸的至少一个空隙。

5. 发明授权

US08013372B2 Integrated circuit including a stressed dielectric layer with stable stress 有权
标题翻译：集成电路包括具有稳定应力的应力介电层
公开(公告)号：US08013372B2
公开(公告)日：2011-09-06
申请号：US12062535
申请日：2008-04-04
申请人： Huang Liu , Jeff Shu , Luona Goh , Wei Lu
发明人： Huang Liu , Jeff Shu , Luona Goh , Wei Lu
IPC分类号： H01L21/336
CPC分类号： H01L29/78 , H01L21/76224 , H01L29/665 , H01L29/7843
摘要： A method for fabricating an integrated circuit is provided. The method includes providing a substrate having an active region and an opening in the substrate adjacent to the active region. The opening is filled with a dielectric material so as to provide an isolation region in the substrate. A transistor is also formed in the active region and a pre-metal dielectric layer formed over the substrate and transistor. At least one of the dielectric layer in isolation region or the pre-metal dielectric layer includes a stressed O3 TEOS oxide having a stress retaining dopant, wherein the concentration of the stress retaining dopant is sufficient to retard stress degradation of the O3 TEOS oxide.
摘要翻译：提供一种制造集成电路的方法。该方法包括提供具有活性区域和邻近活性区域的衬底中的开口的衬底。开口填充有电介质材料，以便在衬底中提供隔离区。晶体管也形成在有源区和形成在衬底和晶体管上的预金属介电层。隔离区域或预金属介电层中的介电层中的至少一个包括具有应力保持掺杂剂的应力O 3 TEOS氧化物，其中应力保留掺杂剂的浓度足以延缓O 3 TEOS氧化物的应力降解。

6. 发明授权

US08035201B2 Reliable interconnection 有权
标题翻译：可靠的互连
公开(公告)号：US08035201B2
公开(公告)日：2011-10-11
申请号：US12473232
申请日：2009-05-27
申请人： Huang Liu , Jack Cheng , Wei Lu , Yihua Wang , Meisheng Zhou
发明人： Huang Liu , Jack Cheng , Wei Lu , Yihua Wang , Meisheng Zhou
IPC分类号： H01L23/00
CPC分类号： H01L21/02167 , H01L21/02211 , H01L21/02274 , H01L21/02348 , H01L21/3148 , H01L21/3185 , H01L21/76825 , H01L21/76829
摘要： Embodiments relate to a method for forming reliable interconnects by the use of a device layer that can serve as a barrier or an etch stop layer, among other applications. The device layer is UV resistant in that its dielectric constant and stress remain stable or relatively stable when subjected to UV curing.
摘要翻译：实施例涉及通过使用可用作阻挡层或蚀刻停止层的器件层形成可靠互连的方法以及其它应用。器件层是抗紫外线的，因为它的介电常数和应力在进行紫外线固化时保持稳定或相对稳定。

7. 发明申请

US20100301461A1 RELIABLE INTERCONNECTION 有权
标题翻译：可靠的互连
公开(公告)号：US20100301461A1
公开(公告)日：2010-12-02
申请号：US12473232
申请日：2009-05-27
申请人： Huang Liu , Jack Cheng , Wei Lu , Yihua Wang , Meisheng Zhou
发明人： Huang Liu , Jack Cheng , Wei Lu , Yihua Wang , Meisheng Zhou
IPC分类号： H01L23/00 , H01L21/312
CPC分类号： H01L21/02167 , H01L21/02211 , H01L21/02274 , H01L21/02348 , H01L21/3148 , H01L21/3185 , H01L21/76825 , H01L21/76829
摘要： Embodiments relate to a method for forming reliable interconnects by the use of a device layer that can serve as a barrier or an etch stop layer, among other applications. The device layer is UV resistant in that its dielectric constant and stress remain stable or relatively stable when subjected to UV curing.
摘要翻译：实施例涉及通过使用可用作阻挡层或蚀刻停止层的器件层形成可靠互连的方法以及其它应用。器件层是抗紫外线的，因为它的介电常数和应力在进行紫外线固化时保持稳定或相对稳定。

8. 发明授权

US08999863B2 Stress liner for stress engineering 有权
标题翻译：应力工程应力衬
公开(公告)号：US08999863B2
公开(公告)日：2015-04-07
申请号：US12133375
申请日：2008-06-05
申请人： Jae Gon Lee , Jingze Tian , Shyue Seng Tan , Luona Goh , Wei Lu , Elgin Quek
发明人： Jae Gon Lee , Jingze Tian , Shyue Seng Tan , Luona Goh , Wei Lu , Elgin Quek
IPC分类号： H01L27/092 , H01L21/8238 , H01L29/78 , H01L29/66
CPC分类号： H01L21/823807 , H01L29/665 , H01L29/7843
摘要： A stress liner having first and second stress type is provided over a first type and a second type transistor to improve reliability and performance without incurring area penalties or layout deficiencies.
摘要翻译：具有第一和第二应力类型的应力衬垫设置在第一类型和第二类型晶体管上，以提高可靠性和性能，而不会引起区域损失或布局缺陷。

9. 发明申请

US20090289284A1 High shrinkage stress silicon nitride (SiN) layer for NFET improvement 审中-公开
标题翻译：用于NFET改进的高收缩应力氮化硅（SiN）层
公开(公告)号：US20090289284A1
公开(公告)日：2009-11-26
申请号：US12154605
申请日：2008-05-23
申请人： Luona Goh , Jingze Tian , Wei Lu , Mei Sheng Zhou
发明人： Luona Goh , Jingze Tian , Wei Lu , Mei Sheng Zhou
IPC分类号： H01L29/78 , H01L21/3105
CPC分类号： H01L21/3125 , H01L21/0217 , H01L21/02222 , H01L21/02282 , H01L21/02348 , H01L29/6659 , H01L29/7843
摘要： A method (and semiconductor device) of forming a high shrinkage stressed silicon nitride layer for use as a contact etch stop layer (CESL) or capping layer in a stress management technique (SMT) provides increased tensile stress to a channel of an nFET device to enhance carrier mobility. A spin-on polysilazane-based dielectric material is applied to a semiconductor substrate and baked to form a film layer. The film layer is cured to remove hydrogen from the film which causes shrinkage in the film when it recrystallizes into silicon nitride. The resulting silicon nitride stressed layer introduces an increased level of tensile stress to the transistor channel region.
摘要翻译：在应力管理技术（SMT）中形成用作接触蚀刻停止层（CESL）或封盖层的高收缩应力氮化硅层的方法（和半导体器件）提供了对nFET器件的沟道增加的拉伸应力，增强载体流动性。将旋涂聚硅氮烷基介电材料施加到半导体衬底上并烘烤以形成膜层。固化膜层以从膜中除去氢，当其重结晶成氮化硅时，其导致膜的收缩。所得的氮化硅应力层向晶体管沟道区域引入增加的拉伸应力水平。

10. 发明授权

US07892900B2 Integrated circuit system employing sacrificial spacers 有权
标题翻译：采用牺牲间隔物的集成电路系统
公开(公告)号：US07892900B2
公开(公告)日：2011-02-22
申请号：US12098751
申请日：2008-04-07
申请人： Huang Liu , Wei Lu , Hai Cong , Alex K. H. See , Hui Peng Koh , Meisheng Zhou
发明人： Huang Liu , Wei Lu , Hai Cong , Alex K. H. See , Hui Peng Koh , Meisheng Zhou
IPC分类号： H01L21/00 , H01L21/84 , H01L21/336
CPC分类号： H01L21/823807 , H01L21/823864 , H01L29/7843
摘要： An integrated circuit system that includes: providing a substrate including a first device and a second device; configuring the first device and the second device to include a first spacer, a first liner made from a first dielectric layer, and a second spacer made from a sacrificial spacer material; forming a second dielectric layer over the integrated circuit system; forming a first device source/drain and a second device source/drain adjacent the second spacer and through the second dielectric layer; removing the second spacer without damaging the substrate; forming a third dielectric layer over the integrated circuit system before annealing; and forming a fourth dielectric layer over the integrated circuit system that promotes stress within the channel of the first device, the second device, or a combination thereof.
摘要翻译：一种集成电路系统，包括：提供包括第一装置和第二装置的基板; 配置第一器件和第二器件以包括第一间隔物，由第一介电层制成的第一衬垫和由牺牲间隔物材料制成的第二间隔物; 在所述集成电路系统上形成第二电介质层; 形成第一器件源极/漏极和邻近第二间隔物并通过第二介电层的第二器件源极/漏极; 去除所述第二间隔物而不损坏所述基底; 在退火之前在集成电路系统上形成第三电介质层; 以及在所述集成电路系统上形成促进所述第一装置，所述第二装置或其组合的通道内的应力的第四电介质层。

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