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1. 发明申请

US20110317479A1 Shared bit line SMT MRAM array with shunting transistors between the bit lines 有权
标题翻译：共享位线SMT MRAM阵列，在位线之间分流晶体管
公开(公告)号：US20110317479A1
公开(公告)日：2011-12-29
申请号：US12803523
申请日：2010-06-29
申请人： Hsu Kai Yang , Yutaka Nakamura , John Debrosse
发明人： Hsu Kai Yang , Yutaka Nakamura , John Debrosse
IPC分类号： G11C11/00
CPC分类号： G11C11/1653 , G11C7/18 , G11C11/161 , G11C11/1655 , G11C11/1675
摘要： An array of rows and columns of SMT MRAM cells has each of the columns associated with one of its adjacent columns. Each of the SMT MRAM cells of the column is connected to a true data bit line and each of the SMT MRAM cells of the associated pair of columns is connected to a shared complement data bit line. A shunting switch device is connected between each of the true data bit lines and the shared complement data bit line for selectively connecting one of the true data bit lines to the shared complement data bit line to effectively reduce the resistance of the complement data bit line and to eliminate program disturb effects in adjacent non-selected columns of the SMT MRAM cells.
摘要翻译： SMT MRAM单元格的行和列阵列具有与其相邻列之一相关联的每个列。列的每个SMT MRAM单元连接到真数据位线，并且相关联的列对的每个SMT MRAM单元连接到共享补码数据位线。分流开关装置连接在每个真实数据位线和共享补码数据位线之间，用于选择性地将一条真实数据位线连接到共享补码数据位线，以有效地减小补码数据位线的电阻，以消除SMT MRAM单元的相邻非选择列中的程序干扰效应。

2. 发明申请

US20100321985A1 Boosted gate voltage programming for spin-torque MRAM array 有权
标题翻译：用于自旋转矩MRAM阵列的升压门电压编程
公开(公告)号：US20100321985A1
公开(公告)日：2010-12-23
申请号：US12806094
申请日：2010-08-05
申请人： Hsu Kai Yang
发明人： Hsu Kai Yang
IPC分类号： G11C11/00 , H01L21/02
CPC分类号： G11C11/1697 , G11C11/1653 , G11C11/1655 , G11C11/1657 , G11C11/1659 , G11C11/1673 , G11C11/1675 , G11C11/1693 , Y10T29/49002
摘要： A gate voltage boosting circuit provides a voltage boost to a gate of a select switching MOS transistor of a spin-torque MRAM cell to prevent a programming current reduction through an MTJ device of the spin-torque MRAM cell. A spin-torque MRAM cell array is composed of spin-torque MRAM cells that include a MTJ element and a select switching device. A local word line is associated with one row of the plurality of spin-torque MRAM cells and is connected to a gate terminal of the select switching devices of the row of MRAM cells to control activation and deactivation. One gate voltage boosting circuit is placed between an associated global word line and an associated local word line. The gate voltage boosting circuits boost a voltage of a gate of the selected switching device during writing of a logical “1” to the MTJ element of a selected spin-torque MRAM cell.
摘要翻译：栅极升压电路为自旋转矩MRAM单元的选择开关MOS晶体管的栅极提供升压，以防止通过自旋转矩MRAM单元的MTJ器件的编程电流减小。自旋转矩MRAM单元阵列由包括MTJ元件和选择开关器件的自旋转矩MRAM单元组成。本地字线与多个自旋扭矩MRAM单元的一行相关联，并且连接到MRAM单元行的选择开关器件的栅极端子以控制激活和去激活。一个栅极升压电路放置在相关联的全局字线和相关的本地字线之间。栅极升压电路在将逻辑“1”写入所选择的自旋转矩MRAM单元的MTJ元件时，提高所选择的开关器件的栅极的电压。

3. 发明授权

US07499314B2 Reference cell scheme for MRAM 有权
标题翻译： MRAM参考单元方案
公开(公告)号：US07499314B2
公开(公告)日：2009-03-03
申请号：US12002161
申请日：2007-12-14
申请人： Hsu Kai Yang , Po-Kang Wang , Xizeng Shi
发明人： Hsu Kai Yang , Po-Kang Wang , Xizeng Shi
IPC分类号： G11C11/00
CPC分类号： G11C7/14 , G11C11/16
摘要： An MRAM reference cell sub-array provides a mid-point reference current to sense amplifiers. The MRAM reference cell sub-array has MRAM cells arranged in rows and columns. Bit lines are associated with each column of the sub-array. A coupling connects the bit lines of pairs of the columns together at a location proximally to the sense amplifiers. The MRAM cells of a first of the pair of columns are programmed to a first magneto-resistive state and the MRAM cells of a second of the pair of columns are programmed to a second magneto-resistive state. When one row of data MRAM cells is selected for reading, a row of paired MRAM reference cells are placed in parallel to generate the mid-point reference current for sensing. The MRAM reference sub-array may be programmed electrically or aided by a magnetic field. A method for verifying programming of the MRAM reference sub-array is discussed.
摘要翻译： MRAM参考单元子阵列提供了一个中点参考电流来检测放大器。 MRAM参考单元子阵列具有以行和列排列的MRAM单元。位线与子阵列的每一列相关联。耦合将位列对的位线连接到读出放大器的近端位置。一对列中的第一列的MRAM单元被编程为第一磁阻状态，并且该对列中的第二对的MRAM单元被编程为第二磁阻状态。当选择一行数据MRAM单元进行读取时，并行放置一对配对的MRAM参考单元，以生成用于检测的中点参考电流。 MRAM参考子阵列可以被电场编程或由磁场辅助。讨论了一种用于验证MRAM参考子阵列的编程的方法。

4. 发明申请

US20080266943A1 Spin-torque MRAM: spin-RAM, array 有权
标题翻译：旋转力矩MRAM：旋转RAM，阵列
公开(公告)号：US20080266943A1
公开(公告)日：2008-10-30
申请号：US11789324
申请日：2007-04-24
申请人： Hsu Kai Yang , Po-Kang Wang
发明人： Hsu Kai Yang , Po-Kang Wang
IPC分类号： G11C11/14
CPC分类号： G11C11/16
摘要： A spin-torque MRAM array has MRAM cells arranged in rows and columns. Bit lines are connected to each of the MRAM cells on each column. Source select lines are connected to each MRAM cell of a pair of rows and are oriented orthogonally to the bit lines. Write lines are connected to the gate of the gating MOS transistor of each MRAM cell of the rows. The MRAM cells are written in a two step process with selected MRAM cells written to a first logic level (0) in a first step and selected MRAM cells written to a second logic level (1) in a second step. A second embodiment of the spin-torque MRAM array has the bit lines commonly connected together to receive the data and the source select lines commonly connected together to receive an inverse of the data for writing.
摘要翻译：自旋扭矩MRAM阵列具有以行和列排列的MRAM单元。位线连接到每列上的每个MRAM单元。源选择线连接到一对行的每个MRAM单元并且与位线正交地定向。写入线连接到行的每个MRAM单元的选通MOS晶体管的栅极。 MRAM单元以两步过程写入，在第一步骤中将所选MRAM单元写入第一逻辑电平（0），并在第二步骤中将所选择的MRAM单元写入第二逻辑电平（1）。自旋扭矩MRAM阵列的第二实施例具有通常连接在一起的位线，以接收通常连接在一起的数据和源选择线，以接收用于写入的数据的倒数。

5. 发明授权

US07321507B2 Reference cell scheme for MRAM 有权
公开(公告)号：US07321507B2
公开(公告)日：2008-01-22
申请号：US11284299
申请日：2005-11-21
申请人： Hsu Kai Yang , Po-Kang Wang , Xizeng Shi
发明人： Hsu Kai Yang , Po-Kang Wang , Xizeng Shi
IPC分类号： G11C7/00
CPC分类号： G11C7/14 , G11C11/16
摘要： An MRAM reference cell sub-array provides a mid-point reference current to sense amplifiers. The MRAM reference cell sub-array has MRAM cells arranged in rows and columns. Bit lines are associated with each column of the sub-array. A coupling connects the bit lines of pairs of the columns together at a location proximally to the sense amplifiers. The MRAM cells of a first of the pair of columns are programmed to a first magneto-resistive state and the MRAM cells of a second of the pair of columns are programmed to a second magneto-resistive state. When one row of data MRAM cells is selected for reading, a row of paired MRAM reference cells are placed in parallel to generate the mid-point reference current for sensing. The MRAM reference sub-array may be programmed electrically or aided by a magnetic field. A method for verifying programming of the MRAM reference sub-array is discussed.

6. 发明授权

US09170879B2 Method and apparatus for scrubbing accumulated data errors from a memory system 有权
标题翻译：用于从存储器系统中擦除累积的数据错误的方法和装置
公开(公告)号：US09170879B2
公开(公告)日：2015-10-27
申请号：US12456923
申请日：2009-06-24
申请人： Hsu Kai Yang
发明人： Hsu Kai Yang
IPC分类号： G06F11/10 , G11C16/34 , G11C29/46
CPC分类号： G06F11/106 , G06F11/1096 , G11C16/3418 , G11C16/349 , G11C29/46
摘要： A data scrubbing apparatus corrects disturb data errors occurring in an array of memory cells such as SMT MRAM cells. The data scrubbing apparatus receives an error indication that an error has occurred during a read operation of a grouping of memory cells within the array of memory cells. The data scrubbing apparatus may generate an address describing the location of the memory cells to be scrubbed. The data scrubbing apparatus then commands the array of memory cells to write back the corrected data. Based on a scrub threshold value, the data scrubbing apparatus writes the corrected data back after a specific number of errors. The data scrubbing apparatus may further suspend writing back during a writing of data. The data scrubbing apparatus provides a busy indicator externally during a write back of corrected data.
摘要翻译：数据擦除装置校正在诸如SMT MRAM单元的存储单元阵列中发生的干扰数据错误。数据擦除装置接收在存储器单元阵列内的一组存储器单元的读取操作期间发生错误的错误指示。数据擦除装置可以生成描述要擦除的存储器单元的位置的地址。然后，数据擦除装置命令存储器单元阵列回写校正的数据。基于擦除阈值，数据擦除装置在经过特定数量的错误之后写入校正后的数据。数据擦除装置可以在写入数据期间进一步中止写回。在校正数据的回写期间，数据擦除装置在外部提供忙指示符。

7. 发明申请

US20110289386A1 Method and apparatus for scrubbing accumulated data errors from a memory system 有权
标题翻译：用于从存储器系统中擦除累积的数据错误的方法和装置
公开(公告)号：US20110289386A1
公开(公告)日：2011-11-24
申请号：US13136292
申请日：2011-07-28
申请人： Hsu Kai Yang
发明人： Hsu Kai Yang
IPC分类号： H03M13/03 , G06F11/10
CPC分类号： G06F11/106
摘要： A data scrubbing apparatus corrects disturb errors occurring in a memory cell array, such as SMT MRAM cells. The data scrubbing apparatus activates scrubbing of the data and associated error correction bits based on a number of errors corrected, at a power up of the memory cell array, or a programmed time interval. The data scrubbing apparatus may generate an address describing the location of the memory cells to be scrubbed. The data scrubbing apparatus then commands the array of memory cells to write back the corrected data, the associated error correction bits, and reference bits. The data scrubbing apparatus provides a busy indicator externally during a write back of corrected data.
摘要翻译：数据擦除装置校正存储单元阵列（例如SMT MRAM单元）中发生的干扰错误。数据擦除装置基于在存储器单元阵列的加电或编程的时间间隔上校正的错误的数量激活数据和相关联的纠错位的擦除。数据擦除装置可以生成描述要擦除的存储器单元的位置的地址。然后，数据擦除装置命令存储器单元阵列写回校正数据，相关联的纠错位和参考位。在校正数据的回写期间，数据擦除装置在外部提供忙指示符。

8. 发明申请

US20110038200A1 Gate drive voltage boost schemes for memory array II 有权
标题翻译：存储器阵列II的栅极驱动升压方案
公开(公告)号：US20110038200A1
公开(公告)日：2011-02-17
申请号：US12583255
申请日：2009-08-17
申请人： Hsu Kai Yang
发明人： Hsu Kai Yang
IPC分类号： G11C11/14 , G11C7/00
CPC分类号： G11C11/1697 , G11C11/1655 , G11C11/1657 , G11C11/1659 , G11C11/1675 , G11C13/0002
摘要： Magnetic memory elements such as Phase Change RAM and Spin Moment Transfer MRAM require high programming currents. These high programming currents require high gate to source/drain voltages for the cell transistors controlling these programming currents, which can degrade the reliability of these cell transistors. This invention describes a circuit and method to write information into individual memory cells while minimizing the gate voltage stress in the cell transistors of the memory cells in which no information is being written. The circuit of this invention has a separately controllable word line voltage supply for each row of the memory array and a separately controllable voltage supply for each bit line of the memory array. During the write operation the voltage is raised for the word line of only one row of the array. The bit line voltages are then adjusted so that a 1 is written into the desired cells in that row and a 0 is written into the desired cells in that row.
摘要翻译：诸如相变RAM和自旋转矩MRAM之类的磁存储元件需要高编程电流。这些高编程电流对于控制这些编程电流的单元晶体管需要高的栅极到源极/漏极电压，这可能降低这些单元晶体管的可靠性。本发明描述了一种将信息写入各个存储单元中的电路和方法，同时最小化其中不写入信息的存储单元的单元晶体管中的栅极电压应力。本发明的电路具有针对存储器阵列的每一行的可单独控制的字线电压电源和用于存储器阵列的每个位线的单独可控的电压源。在写入操作期间，只有阵列的一行的字线升高电压。然后调整位线电压，使得将1写入该行中的期望单元，并将0写入该行中期望的单元。

9. 发明授权

US07852662B2 Spin-torque MRAM: spin-RAM, array 有权
标题翻译：旋转力矩MRAM：旋转RAM，阵列
公开(公告)号：US07852662B2
公开(公告)日：2010-12-14
申请号：US11789324
申请日：2007-04-24
申请人： Hsu Kai Yang , Po-Kang Wang
发明人： Hsu Kai Yang , Po-Kang Wang
IPC分类号： G11C11/00
CPC分类号： G11C11/16
摘要： A spin-torque MRAM array has MRAM cells arranged in rows and columns. Bit lines are connected to each of the MRAM cells on each column. Source select lines are connected to each MRAM cell of a pair of rows and are oriented orthogonally to the bit lines. Write lines are connected to the gate of the gating MOS transistor of each MRAM cell of the rows. The MRAM cells are written in a two step process with selected MRAM cells written to a first logic level (0) in a first step and selected MRAM cells written to a second logic level (1) in a second step. A second embodiment of the spin-torque MRAM array has the bit lines commonly connected together to receive the data and the source select lines commonly connected together to receive an inverse of the data for writing.
摘要翻译：自旋扭矩MRAM阵列具有以行和列排列的MRAM单元。位线连接到每列上的每个MRAM单元。源选择线连接到一对行的每个MRAM单元并且与位线正交地定向。写入线连接到行的每个MRAM单元的选通MOS晶体管的栅极。 MRAM单元以两步过程写入，在第一步骤中将所选MRAM单元写入第一逻辑电平（0），并在第二步骤中将所选择的MRAM单元写入第二逻辑电平（1）。自旋扭矩MRAM阵列的第二实施例具有通常连接在一起的位线，以接收通常连接在一起的数据和源选择线，以接收用于写入的数据的倒数。

10. 发明授权

US07782661B2 Boosted gate voltage programming for spin-torque MRAM array 有权
公开(公告)号：US07782661B2
公开(公告)日：2010-08-24
申请号：US12313487
申请日：2008-11-20
申请人： Hsu Kai Yang
发明人： Hsu Kai Yang
IPC分类号： G11C11/00
CPC分类号： G11C11/1697 , G11C11/1653 , G11C11/1655 , G11C11/1657 , G11C11/1659 , G11C11/1673 , G11C11/1675 , G11C11/1693 , Y10T29/49002
摘要： A gate voltage boosting circuit provides a voltage boost to a gate of a select switching MOS transistor of a spin-torque MRAM cell to prevent a programming current reduction through an MTJ device of the spin-torque MRAM cell. A spin-torque MRAM cell array is composed of spin-torque MRAM cells that include a MTJ element and a select switching device. A local word line is associated with one row of the plurality of spin-torque MRAM cells and is connected to a gate terminal of the select switching devices of the row of MRAM cells to control activation and deactivation. One gate voltage boosting circuit is placed between an associated global word line and an associated local word line. The gate voltage boosting circuits boost a voltage of a gate of the selected switching device during writing of a logical “1” to the MTJ element of a selected spin-torque MRAM cell.

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