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    • 1. 发明申请
    • LIQUID CRYSTAL DISPLAY AND DRIVING METHOD THEREOF
    • 液晶显示及其驱动方法
    • US20100315322A1
    • 2010-12-16
    • US12647560
    • 2009-12-28
    • Hsiao-Chung ChengChao-Ching HsuMu-Lin Tung
    • Hsiao-Chung ChengChao-Ching HsuMu-Lin Tung
    • G09G3/36
    • G09G3/3677G09G3/3611G09G2310/067G09G2320/0219G09G2330/023G11C19/28
    • A liquid crystal display includes a gate driver, a control circuit and a charge-sharing circuit. The control circuit provides a charge-sharing signal according to the parasitic capacitances at a first output end and a second output end in the gate driver. The charge-sharing circuit generates a third clock signal and a fourth clock signal by performing charge-sharing on a first clock signal and a second clock signal according to the charge-sharing signal. The third clock signal includes a signal falling edge which descends from a high level to a first level, and the fourth clock signal includes a signal falling edge which descends from the high level to a second level. The gate driver outputs a first gate driving signal and a second gate driving signal respectively at the first and the second output end according the third or the fourth clock signal.
    • 液晶显示器包括栅极驱动器,控制电路和电荷共享电路。 控制电路根据栅极驱动器中的第一输出端和第二输出端处的寄生电容提供电荷共享信号。 电荷共享电路通过根据电荷共享信号在第一时钟信号和第二时钟信号上执行电荷共享来产生第三时钟信号和第四时钟信号。 第三时钟信号包括从高电平下降到第一电平的信号下降沿,并且第四时钟信号包括从高电平下降到第二电平的信号下降沿。 栅极驱动器根据第三或第四时钟信号在第一和第二输出端分别输出第一栅极驱动信号和第二栅极驱动信号。
    • 2. 发明授权
    • Liquid crystal display with reduced image flicker and driving method thereof
    • 降低图像闪烁的液晶显示器及其驱动方法
    • US08325126B2
    • 2012-12-04
    • US12647560
    • 2009-12-28
    • Hsiao-Chung ChengChao-Ching HsuMu-Lin Tung
    • Hsiao-Chung ChengChao-Ching HsuMu-Lin Tung
    • G09G3/36
    • G09G3/3677G09G3/3611G09G2310/067G09G2320/0219G09G2330/023G11C19/28
    • A liquid crystal display includes a gate driver, a control circuit and a charge-sharing circuit. The control circuit provides a charge-sharing signal according to the parasitic capacitances at a first output end and a second output end in the gate driver. The charge-sharing circuit generates a third clock signal and a fourth clock signal by performing charge-sharing on a first clock signal and a second clock signal according to the charge-sharing signal. The third clock signal includes a signal falling edge which descends from a high level to a first level, and the fourth clock signal includes a signal falling edge which descends from the high level to a second level. The gate driver outputs a first gate driving signal and a second gate driving signal respectively at the first and the second output end according the third or the fourth clock signal.
    • 液晶显示器包括栅极驱动器,控制电路和电荷共享电路。 控制电路根据栅极驱动器中的第一输出端和第二输出端处的寄生电容提供电荷共享信号。 电荷共享电路通过根据电荷共享信号在第一时钟信号和第二时钟信号上执行电荷共享来产生第三时钟信号和第四时钟信号。 第三时钟信号包括从高电平下降到第一电平的信号下降沿,并且第四时钟信号包括从高电平下降到第二电平的信号下降沿。 栅极驱动器根据第三或第四时钟信号在第一和第二输出端分别输出第一栅极驱动信号和第二栅极驱动信号。
    • 3. 发明授权
    • Level shift circuit, liquid crystal display device and charge sharing method
    • 液位移动电路,液晶显示装置和电荷共享方法
    • US08436801B2
    • 2013-05-07
    • US12684908
    • 2010-01-09
    • Chao-Ching HsuMu-Lin TungChung-Shen Cheng
    • Chao-Ching HsuMu-Lin TungChung-Shen Cheng
    • G09G3/36
    • H03K19/0175G09G3/3677G09G2310/0289G09G2330/023
    • A level shift circuit includes a control logic circuit, a plurality of level shift output buffers and a plurality of charge sharing circuits. The control logic circuit receives input clock pulse signals and a charge sharing signal and acquires voltage level information of each received signal. Each output buffer amplifies a corresponding input clock pulse signal and determines whether to output a signal according to the acquired information of the charge sharing signal. Each charge sharing circuit determines whether to be turned on according to the acquired information of a corresponding input clock pulse signal. When a charge sharing circuit is turned on, the output terminal of a corresponding output buffer and a predetermined voltage level are coupled to each other by the charge sharing circuit, so as to perform the charge sharing operation. Furthermore, a corresponding liquid crystal display device and a corresponding charge sharing method are also provided.
    • 电平移位电路包括控制逻辑电路,多个电平移位输出缓冲器和多个电荷共享电路。 控制逻辑电路接收输入时钟脉冲信号和电荷共享信号,并获取每个接收信号的电压电平信息。 每个输出缓冲器放大对应的输入时钟脉冲信号,并根据获取的电荷共享信号的信息确定是否输出信号。 每个电荷共享电路根据所获取的相应输入时钟脉冲信号的信息确定是否被接通。 当电荷共享电路接通时,相应的输出缓冲器的输出端和预定的电压电平通过电荷共享电路彼此耦合,从而进行电荷共享操作。 此外,还提供了相应的液晶显示装置和相应的电荷共享方法。
    • 4. 发明授权
    • Display device, display device driving method and source driving circuit
    • 显示装置,显示装置驱动方式和源驱动电路
    • US09105247B2
    • 2015-08-11
    • US12848717
    • 2010-08-02
    • Yi-Fan LinMu-Lin TungChao-Ching Hsu
    • Yi-Fan LinMu-Lin TungChao-Ching Hsu
    • G06F3/038G09G3/36
    • G09G3/3614G09G2300/0426G09G2330/021
    • A display device includes multiple first data lines, multiple second data lines, multiple pixel columns, at least a first charge sharing switch circuit and at least a second charge sharing switch circuit. The second data lines are alternately arranged with the first data lines. Each of the pixel columns includes multiple first pixels and multiple second pixels. The first pixels of each of the pixel columns are coupled to one of the first data lines, and the second pixels of each of the pixel columns are coupled to one of the second data lines. The first charge sharing switch circuit each is electrically coupled to at least a part of the first data lines. The second charge sharing switch circuit each is electrically coupled to at least a part of the second data lines. A display device driving method and a source driving circuit also are provided.
    • 显示装置包括多个第一数据线,多个第二数据线,多个像素列,至少第一电荷共享开关电路和至少第二电荷共享开关电路。 第二数据线与第一数据线交替布置。 每个像素列包括多个第一像素和多个第二像素。 每个像素列的第一像素被耦合到第一数据线中的一个,并且每个像素列的第二像素被耦合到第二数据线之一。 第一电荷共享开关电路各自电耦合到第一数据线的至少一部分。 第二电荷共享开关电路各自电耦合到第二数据线的至少一部分。 还提供了一种显示装置驱动方法和源极驱动电路。
    • 5. 发明授权
    • Charge-sharing method and device for clock signal generation
    • 用于时钟信号产生的电荷共享方法和装置
    • US07750715B2
    • 2010-07-06
    • US12315189
    • 2008-11-28
    • Chao-Ching HsuMu-Lin TungChung-Shen Cheng
    • Chao-Ching HsuMu-Lin TungChung-Shen Cheng
    • G06F1/04
    • G09G3/3611G09G3/3677G09G2330/023G11C7/222G11C19/00H03K19/0013H03K19/0016
    • A clock generation circuit has two output ends to provide a first clock signal and a second clock signal, in response to first and second input signals, respectively. A charge storage component is used to transfer some charge from the first output end to the charge storage component when the first clock signal is high for a period of time, and to transfer the charge from the charge storage component to the second output end when the second clock signal is low. At a different period of time in the clock cycle, the charge storage component is used to transfer some charge from the second output end to the charge storage component when the second clock signal is high for a period of time, and to transfer the charge from the charge storage component to the first output end when the first clock signal is low.
    • 时钟发生电路具有两个输出端,以分别响应于第一和第二输入信号提供第一时钟信号和第二时钟信号。 当第一时钟信号为高电平一段时间时,电荷存储部件用于将一些电荷从第一输出端传送到电荷存储部件,并且当电荷存储部件的电荷从电荷存储部件传送到第二输出端时, 第二个时钟信号为低电平。 在时钟周期的不同时间段,当第二时钟信号为高电平一段时间时,电荷存储部件用于将一些电荷从第二输出端传送到电荷存储部件,并将电荷从 当第一时钟信号为低时,电荷存储部件到第一输出端。
    • 6. 发明申请
    • CHARGE-SHARING METHOD AND DEVICE FOR CLOCK SIGNAL GENERATION
    • 充电共享方法和时钟信号发生装置
    • US20100134172A1
    • 2010-06-03
    • US12315189
    • 2008-11-28
    • Chao-Ching HsuMu-Lin TungChung-Shen Cheng
    • Chao-Ching HsuMu-Lin TungChung-Shen Cheng
    • G06F1/06
    • G09G3/3611G09G3/3677G09G2330/023G11C7/222G11C19/00H03K19/0013H03K19/0016
    • A clock generation circuit has two output ends to provide a first clock signal and a second clock signal, in response to first and second input signals, respectively. A charge storage component is used to transfer some charge from the first output end to the charge storage component when the first clock signal is high for a period of time, and to transfer the charge from the charge storage component to the second output end when the second clock signal is low. At a different period of time in the clock cycle, the charge storage component is used to transfer some charge from the second output end to the charge storage component when the second clock signal is high for a period of time, and to transfer the charge from the charge storage component to the first output end when the first clock signal is low.
    • 时钟发生电路具有两个输出端,以分别响应于第一和第二输入信号提供第一时钟信号和第二时钟信号。 当第一时钟信号为高电平一段时间时,电荷存储部件用于将一些电荷从第一输出端传送到电荷存储部件,并且当电荷存储部件的电荷从电荷存储部件传送到第二输出端时, 第二个时钟信号为低电平。 在时钟周期的不同时间段,当第二时钟信号为高电平一段时间时,电荷存储部件用于将一些电荷从第二输出端传送到电荷存储部件,并将电荷从 当第一时钟信号为低时,电荷存储部件到第一输出端。
    • 9. 发明申请
    • DISPLAY DEVICE, DISPLAY DEVICE DRIVING METHOD AND SOURCE DRIVING CIRCUIT
    • 显示设备,显示设备驱动方法和源驱动电路
    • US20110248985A1
    • 2011-10-13
    • US12848717
    • 2010-08-02
    • Yi-Fan LINMu-Lin TungChao-Ching Hsu
    • Yi-Fan LINMu-Lin TungChao-Ching Hsu
    • G06F3/038G09G3/36
    • G09G3/3614G09G2300/0426G09G2330/021
    • A display device includes multiple first data lines, multiple second data lines, multiple pixel columns, at least a first charge sharing switch circuit and at least a second charge sharing switch circuit. The second data lines are alternately arranged with the first data lines. Each of the pixel columns includes multiple first pixels and multiple second pixels. The first pixels of each of the pixel columns are coupled to one of the first data lines, and the second pixels of each of the pixel columns are coupled to one of the second data lines. The first charge sharing switch circuit each is electrically coupled to at least a part of the first data lines. The second charge sharing switch circuit each is electrically coupled to at least a part of the second data lines. A display device driving method and a source driving circuit also are provided.
    • 显示装置包括多个第一数据线,多个第二数据线,多个像素列,至少第一电荷共享开关电路和至少第二电荷共享开关电路。 第二数据线与第一数据线交替布置。 每个像素列包括多个第一像素和多个第二像素。 每个像素列的第一像素被耦合到第一数据线中的一个,并且每个像素列的第二像素被耦合到第二数据线之一。 第一电荷共享开关电路各自电耦合到第一数据线的至少一部分。 第二电荷共享开关电路各自电耦合到第二数据线的至少一部分。 还提供了一种显示装置驱动方法和源极驱动电路。