专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US5861766A Multimode frequency synthesizer having high loop gain in frequency seek mode 失效
标题翻译：在频率寻找模式下具有高环路增益的多模频率合成器
公开(公告)号：US5861766A
公开(公告)日：1999-01-19
申请号：US844221
申请日：1997-04-17
申请人： Howard Anthony Baumer , David Kyong-sik Chung , Gerald Weslie Shearer
发明人： Howard Anthony Baumer , David Kyong-sik Chung , Gerald Weslie Shearer
IPC分类号： G11B20/12 , H03L7/089 , H03L7/107 , H03L7/199 , H03L7/085
CPC分类号： H03L7/0898 , H03L7/0893 , H03L7/107 , H03L7/199 , G11B20/1258 , G11B2020/1282
摘要： A frequency synthesizer has multiple modes of operation including a relatively short-duration frequency seek mode and a relatively long-duration normal mode. The synthesizer responds to a reference frequency signal and produces a periodic signal at a frequency that is a rational number times the frequency of the reference frequency signal. The synthesizer comprises a VCO, a feedforward state machine, a feedback state machine, a phase comparator, controllable gain circuitry between the phase comparator and the VCO, and logic circuitry that coordinates the operation of the feedforward and feedback state machines during the seek mode.
摘要翻译：频率合成器具有多种操作模式，包括相对较短持续时间的频率寻找模式和相对较长持续时间的正常模式。合成器对参考频率信号进行响应，并以基频频率信号的有效数乘以频率产生周期信号。合成器包括VCO，前馈状态机，反馈状态机，相位比较器，相位比较器和VCO之间的可控增益电路，以及在搜索模式期间协调前馈和反馈状态机的操作的逻辑电路。

2. 发明授权

US06982604B2 CDR lock detector with hysteresis 失效
标题翻译： CDR锁定检测器具有迟滞
公开(公告)号：US06982604B2
公开(公告)日：2006-01-03
申请号：US10979925
申请日：2004-11-02
申请人： David Kyong-sik Chung
发明人： David Kyong-sik Chung
IPC分类号： H03L7/095
CPC分类号： H03L7/095 , Y10S331/02
摘要： A lock-detect circuit is configured to detect whether an incoming signal has acquired a lock to a reference signal using a first frequency detect window and to detect whether the incoming signal has lost a previously acquired a lock to the reference signal using a second frequency detect window different from the first frequency detect window. The two signals are applied to two different down-counters that are first synchronized before initiating the count-downs. If the offset between the counts of the two counters is less than the first frequency detect window, the incoming signal is detected as having acquired a lock to the reference signal. If the offset between the counts of the two counters is greater than the second frequency detect window, the incoming signal is detected as having lost its previously acquired lock to the reference signal.
摘要翻译：锁定检测电路被配置为检测输入信号是否已经使用第一频率检测窗口获取对参考信号的锁定，并且使用第二频率检测来检测输入信号是否已经丢失了对参考信号的先前获取的锁定窗口与第一个频率检测窗口不同。这两个信号被应用于在启动倒计时之前首先同步的两个不同的下位计数器。如果两个计数器的计数之间的偏移量小于第一个频率检测窗口，则输入信号被检测为已经获取了对参考信号的锁定。如果两个计数器的计数之间的偏移量大于第二个频率检测窗口，则输入信号被检测为已经失去其对参考信号的先前获得的锁定。

3. 发明授权

US06833763B2 CDR lock detector with hysteresis 失效
标题翻译： CDR锁定检测器具有迟滞
公开(公告)号：US06833763B2
公开(公告)日：2004-12-21
申请号：US10829755
申请日：2004-04-22
申请人： David Kyong-sik Chung
发明人： David Kyong-sik Chung
IPC分类号： H03L7095
CPC分类号： H03L7/095 , Y10S331/02
摘要： A lock-detect circuit is configured to detect whether an incoming signal has acquired a lock to a reference signal using a first frequency detect window and to detect whether the incoming signal has lost a previously acquired a lock to the reference signal using a second frequency detect window different from the first frequency detect window. The two signals are applied to two different down-counters that are first synchronized before initiating their count-downs. If the offset between the counts of the two counters is less than the first frequency detect window, the incoming signal is detected as having acquired a lock to the reference signal. If the offset between the counts of the two counters is greater than the second frequency detect window, the incoming signal is detected as having lost its previously acquired lock to the reference signal.
摘要翻译：锁定检测电路被配置为检测输入信号是否已经使用第一频率检测窗口获取对参考信号的锁定，并且使用第二频率检测来检测输入信号是否已经丢失了对参考信号的先前获取的锁定窗口与第一个频率检测窗口不同。这两个信号被应用于在启动倒数计数之前首先同步的两个不同的向下计数器。如果两个计数器的计数之间的偏移量小于第一个频率检测窗口，则输入信号被检测为已经获取了对参考信号的锁定。如果两个计数器的计数之间的偏移量大于第二个频率检测窗口，则输入信号被检测为已经失去其对参考信号的先前获得的锁定。

4. 发明授权

US06747518B1 CDR lock detector with hysteresis 有权
公开(公告)号：US06747518B1
公开(公告)日：2004-06-08
申请号：US10335190
申请日：2002-12-30
申请人： David Kyong-sik Chung
发明人： David Kyong-sik Chung
IPC分类号： H03L07095
CPC分类号： H03L7/095 , Y10S331/02
摘要： A lock-detect circuit is configured to detect whether an incoming signal has acquired a lock to a reference signal using a first frequency detect window and to detect whether the incoming signal has lost a previously acquired a lock to the reference signal using a second frequency detect window different from the first frequency detect window. The two signals are applied to two different down-counters that are first synchronized before initiating their count-downs. If the offset between the counts of the two counters is less than the first frequency detect window, the incoming signal is detected as having acquired a lock to the reference signal. If the offset between the counts of the two counters is greater than the second frequency detect window, the incoming signal is detected as having lost its previously acquired lock to the reference signal.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式