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1. 发明授权

US06212121B1 Semiconductor memory device with multiple sub-arrays of different sizes 有权
标题翻译：具有不同尺寸的多个子阵列的半导体存储器件
公开(公告)号：US06212121B1
公开(公告)日：2001-04-03
申请号：US09451466
申请日：1999-11-30
申请人： Hoon Ryu , Moon-Chan Hwang , Jun-Young Jeon
发明人： Hoon Ryu , Moon-Chan Hwang , Jun-Young Jeon
IPC分类号： G11C800
CPC分类号： G11C8/12
摘要： A semiconductor memory device includes a memory cell array divided into a plurality of sub-arrays. The number of memory cells per bit line in at least one of the sub-arrays differs from the number of memory cells per bit line in other sub-arrays. When the sense amplifiers can accommodate a bit line loading of (2M+2M/N) memory cells per bit line, the size and bit line loading of one of more of the sub-arrays can be increased. This can provide sub-arrays of different sizes and can reduce the number of the sub-arrays and the number of the sense amplifier regions. Accordingly, the chip efficiency is improved. Maximum current for sensing during simultaneous accesses of multiple arrays can access two sub-arrays with different bit line loadings and avoid simultaneously accessing two sub-arrays having high bit-line loadings.
摘要翻译：半导体存储器件包括分成多个子阵列的存储单元阵列。至少一个子阵列中每位线的存储单元的数量与其他子阵列中每位线的存储单元的数量不同。当读出放大器可以容纳每个位线的（2M + 2M / N）个存储单元的位线负载时，可以增加更多子阵列之一的大小和位线负载。这可以提供不同尺寸的子阵列，并且可以减少子阵列的数量和读出放大器区域的数量。因此，提高了芯片效率。在同时访问多个阵列期间感测的最大电流可以访问具有不同位线负载的两个子阵列，并避免同时访问具有高位线负载的两个子阵列。

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