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1. 发明授权

US06212121B1 Semiconductor memory device with multiple sub-arrays of different sizes 有权
标题翻译：具有不同尺寸的多个子阵列的半导体存储器件
公开(公告)号：US06212121B1
公开(公告)日：2001-04-03
申请号：US09451466
申请日：1999-11-30
申请人： Hoon Ryu , Moon-Chan Hwang , Jun-Young Jeon
发明人： Hoon Ryu , Moon-Chan Hwang , Jun-Young Jeon
IPC分类号： G11C800
CPC分类号： G11C8/12
摘要： A semiconductor memory device includes a memory cell array divided into a plurality of sub-arrays. The number of memory cells per bit line in at least one of the sub-arrays differs from the number of memory cells per bit line in other sub-arrays. When the sense amplifiers can accommodate a bit line loading of (2M+2M/N) memory cells per bit line, the size and bit line loading of one of more of the sub-arrays can be increased. This can provide sub-arrays of different sizes and can reduce the number of the sub-arrays and the number of the sense amplifier regions. Accordingly, the chip efficiency is improved. Maximum current for sensing during simultaneous accesses of multiple arrays can access two sub-arrays with different bit line loadings and avoid simultaneously accessing two sub-arrays having high bit-line loadings.
摘要翻译：半导体存储器件包括分成多个子阵列的存储单元阵列。至少一个子阵列中每位线的存储单元的数量与其他子阵列中每位线的存储单元的数量不同。当读出放大器可以容纳每个位线的（2M + 2M / N）个存储单元的位线负载时，可以增加更多子阵列之一的大小和位线负载。这可以提供不同尺寸的子阵列，并且可以减少子阵列的数量和读出放大器区域的数量。因此，提高了芯片效率。在同时访问多个阵列期间感测的最大电流可以访问具有不同位线负载的两个子阵列，并避免同时访问具有高位线负载的两个子阵列。

2. 发明授权

US6026047A Integrated circuit memory device with hierarchical work line structure 有权
标题翻译：具有分层工作线结构的集成电路存储器件
公开(公告)号：US6026047A
公开(公告)日：2000-02-15
申请号：US185090
申请日：1998-11-03
申请人： Hoon Ryu , Jun-Young Jeon
发明人： Hoon Ryu , Jun-Young Jeon
IPC分类号： G11C11/407 , G11C8/08 , G11C8/10 , G11C8/14 , G11C8/00
CPC分类号： G11C8/14 , G11C8/08 , G11C8/10
摘要： A dynamic random access memory device includes sub-word line drivers to drive sub-word lines up to a boosted voltage level. Each sub-word line driver generates a sub-word drive signal to drive a corresponding sub-word line in response to main-word decode signal and a sub-word decode signal. Each of the sub-word line drivers includes an N-channel MOS pull-up transistor and an N-channel MOS precharge transistor whose threshold voltages are different from each other. The conduction path of the pull-up transistor is coupled between the sub-word decode signal and the corresponding sub-word line. The precharge transistor has a conduction path coupled between the main-word line and the control electrode of the pull-up transistor. The control electrode of the precharge transistor is coupled to the boosted voltage. The boosted voltage is larger than the power supply voltage by twice the threshold voltage of the pull-up transistor. The threshold voltage of the precharge transistor is smaller than that of the pull-up transistor.
摘要翻译：动态随机存取存储器件包括用于驱动子字线直到提升的电压电平的子字线驱动器。每个子字线驱动器响应于主字解码信号和子字解码信号产生子字驱动信号以驱动对应的子字线。每个子字线驱动器包括N沟道MOS上拉晶体管和阈值电压彼此不同的N沟道MOS预充电晶体管。上拉晶体管的导通路径耦合在子字解码信号和对应的子字线之间。预充电晶体管具有耦合在主字线和上拉晶体管的控制电极之间的导通路径。预充电晶体管的控制电极耦合到升压电压。升压电压大于电源电压的两倍于上拉晶体管的阈值电压。预充电晶体管的阈值电压小于上拉晶体管的阈值电压。

3. 发明申请

US20100306605A1 Apparatus and Method for Manufacturing a Multiple-Chip Memory Device 有权
标题翻译：用于制造多芯片存储器件的装置和方法
公开(公告)号：US20100306605A1
公开(公告)日：2010-12-02
申请号：US12856225
申请日：2010-08-13
申请人： KoonHee Lee , Ryan Patterson , Hoon Ryu , Klaus Nierle
发明人： KoonHee Lee , Ryan Patterson , Hoon Ryu , Klaus Nierle
IPC分类号： G11C29/08 , G06F11/26
CPC分类号： G11C29/802 , G11C5/04 , G11C2029/4402 , G11C2029/5606
摘要： A method for manufacturing a multiple-chip memory device includes making a volatile memory element on a semiconductor substrate, examining the volatile memory element for one or more initial errors, correcting the one or more initial errors on the semiconductor substrate, incorporating the volatile memory element into the multiple-chip memory device, and incorporating a non-volatile memory element into the multiple-chip memory device. The volatile memory element is examined for one or more secondary errors, after incorporating the volatile memory element and the non-volatile memory element into the multiple-chip memory device. Repair information is stored in a non-volatile memory element, the repair information identifying the one or more secondary errors.
摘要翻译：一种用于制造多芯片存储器件的方法包括在半导体衬底上制造易失性存储器元件，检查易失性存储元件的一个或多个初始误差，校正半导体衬底上的一个或多个初始误差，并结合易失性存储元件进入多芯片存储器件，并将非易失性存储器元件结合到多芯片存储器件中。在将易失性存储器元件和非易失性存储器元件并入到多芯片存储器件中之后，检查易失性存储元件中的一个或多个次级错误。修复信息存储在非易失性存储器元件中，修复信息识别一个或多个次要错误。

4. 发明申请

US20100070676A1 Memory Data Bus Placement and Control 审中-公开
标题翻译：内存数据总线布局和控制
公开(公告)号：US20100070676A1
公开(公告)日：2010-03-18
申请号：US12209542
申请日：2008-09-12
申请人： Hoon Ryu
发明人： Hoon Ryu
IPC分类号： G06F12/06
CPC分类号： G11C8/12 , G11C7/10 , G11C7/1048 , G11C7/18 , G11C8/04
摘要： In one embodiment, a memory device comprises a plurality of memory banks. At least two of the memory banks share the same bus. Logic is coupled to the memory banks via the different buses. The logic controls access to the memory banks. A bi-directional tri-state buffer is interposed between adjacent memory banks along the same bus so that each bus is segmented into a plurality of sections, each bus section being coupled to one or more different ones of the memory banks.
摘要翻译：在一个实施例中，存储器件包括多个存储体。至少有两个存储器共享相同的总线。逻辑通过不同的总线耦合到存储体。该逻辑控制对存储体的访问。双向三态缓冲器被插入相邻存储体之间的同一总线，使得每个总线被分段成多个部分，每个总线部分耦合到一个或多个不同的存储体。

5. 发明授权

US06281745B1 Internal power supply voltage generating circuit of semiconductor memory device 有权
标题翻译：半导体存储器件的内部电源电压发生电路
公开(公告)号：US06281745B1
公开(公告)日：2001-08-28
申请号：US09511848
申请日：2000-02-23
申请人： Jae Hoon Kim , Hyun Soon Jang , Hoon Ryu
发明人： Jae Hoon Kim , Hyun Soon Jang , Hoon Ryu
IPC分类号： G05F302
CPC分类号： G05F1/465
摘要： A flexible internal power supply voltage generating circuit of a semiconductor memory device includes a step-down circuit and a selection circuit. The selection circuit selects the step-down circuit for use when the semiconductor device uses a high external power supply voltage but bypasses the step-down circuit for a low external power supply voltage. One such circuit additionally includes a power supply terminal and a control circuit. The power supply terminal receives an external power supply voltage. The control circuit compares a feedback internal power supply voltage with a reference voltage at the time of driving a word line and then generates a control voltage signal for controlling a DIP of an internal power supply voltage caused by driving the word line. A selection circuit selectively connects a high voltage node or a low voltage node to the power supply terminal according to the external power supply voltage. The step-down circuit connects to the high voltage node and reduces the external power supply voltage when the power supply terminal receives the high supply voltage. The driver is between a common connection point of the step-down circuit and the low voltage node and an internal circuit and drives the external power supply voltage in the internal circuit in response to the control signal. Accordingly, when a high voltage is applied, the high voltage is stepped down and provided to the driver, thereby controlling a reverse overshoot of the internal power supply voltage.
摘要翻译：半导体存储器件的柔性内部电源电压产生电路包括降压电路和选择电路。选择电路选择半导体器件使用高外部电源电压时使用的降压电路，但是为了低的外部电源电压而绕过降压电路。一个这样的电路还包括电源端子和控制电路。电源端子接收外部电源电压。控制电路将反馈内部电源电压与驱动字线时的参考电压进行比较，然后生成用于控制由驱动字线引起的内部电源电压的DIP的控制电压信号。选择电路根据外部电源电压选择性地将高压节点或低压节点连接到电源端子。当电源端子接收到高电源电压时，降压电路连接到高压节点并降低外部电源电压。驱动器在降压电路的公共连接点和低电压节点之间以及内部电路之间，响应于控制信号驱动内部电路中的外部电源电压。因此，当施加高电压时，高压被降低并提供给驱动器，从而控制内部电源电压的反向过冲。

6. 发明授权

US07684273B2 Sense amplifier biasing method and apparatus 失效
标题翻译：感应放大器偏置方式和装置
公开(公告)号：US07684273B2
公开(公告)日：2010-03-23
申请号：US11939903
申请日：2007-11-14
申请人： Hoon Ryu
发明人： Hoon Ryu
IPC分类号： G11C7/02
CPC分类号： G11C7/02 , G11C7/062 , G11C7/1048 , G11C11/4091 , G11C2207/065
摘要： A memory device includes sense amplifier circuitry, a current sink and a resistive element. The sense amplifier circuitry is operable to evaluate data read from a memory array included in the memory device responsive to a bias voltage applied to the sense amplifier circuitry. The current sink is operable to sink a bias current. The resistive element couples the current sink to the sense amplifier circuitry. The bias voltage applied to the sense amplifier circuitry corresponds to the voltage drop across the resistive element and current sink as induced by the bias current.
摘要翻译：存储器件包括读出放大器电路，电流吸收器和电阻元件。感测放大器电路可操作以响应于施加到感测放大器电路的偏置电压来评估从包括在存储器件中的存储器阵列读取的数据。电流吸收器可操作以吸收偏置电流。电阻元件将电流吸收器耦合到读出放大器电路。施加到感测放大器电路的偏置电压对应于由偏置电流引起的电阻元件和电流吸收器两端的电压降。

7. 发明授权

US08468401B2 Apparatus and method for manufacturing a multiple-chip memory device with multi-stage testing 有权
标题翻译：用于制造具有多级测试的多芯片存储器件的装置和方法
公开(公告)号：US08468401B2
公开(公告)日：2013-06-18
申请号：US12856225
申请日：2010-08-13
申请人： KoonHee Lee , Ryan Patterson , Hoon Ryu , Klaus Nierle
发明人： KoonHee Lee , Ryan Patterson , Hoon Ryu , Klaus Nierle
IPC分类号： G06F11/00
CPC分类号： G11C29/802 , G11C5/04 , G11C2029/4402 , G11C2029/5606
摘要： A method for manufacturing a multiple-chip memory device includes making a volatile memory element on a semiconductor substrate, examining the volatile memory element for one or more initial errors, correcting the one or more initial errors on the semiconductor substrate, incorporating the volatile memory element into the multiple-chip memory device, and incorporating a non-volatile memory element into the multiple-chip memory device. The volatile memory element is examined for one or more secondary errors, after incorporating the volatile memory element and the non-volatile memory element into the multiple-chip memory device. Repair information is stored in a non-volatile memory element, the repair information identifying the one or more secondary errors.
摘要翻译：一种用于制造多芯片存储器件的方法包括在半导体衬底上制造易失性存储器元件，检查易失性存储元件的一个或多个初始误差，校正半导体衬底上的一个或多个初始误差，并结合易失性存储元件进入多芯片存储器件，并将非易失性存储器元件结合到多芯片存储器件中。在将易失性存储器元件和非易失性存储器元件并入到多芯片存储器件中之后，检查易失性存储元件中的一个或多个次级错误。修复信息存储在非易失性存储器元件中，修复信息识别一个或多个次要错误。

8. 发明授权

US06198341B1 Substrate bias voltage generating circuit for use in a semiconductor device 失效
标题翻译：用于半导体器件的衬底偏压生成电路
公开(公告)号：US06198341B1
公开(公告)日：2001-03-06
申请号：US09337485
申请日：1999-06-21
申请人： Hoon Ryu
发明人： Hoon Ryu
IPC分类号： G05F110
CPC分类号： H02M3/073
摘要： A circuit is provided for biasing a semiconductor substrate. The circuit comprises a driving signal generating circuit and a charge pump circuit. The driving signal generating circuit produces first to fourth charge pump driving signals in response to an oscillation signal. Each of the first and fourth charge pump driving signals has a high voltage level that is higher than a power supply voltage. Accordingly, even though the power supply voltage is lowered, a loss of a pump efficiency is prevented because a PMOS transistor in the charge pump circuit is driven by the charge pump driving signal having the voltage higher than the power supply voltage.
摘要翻译：提供用于偏置半导体衬底的电路。电路包括驱动信号发生电路和电荷泵电路。驱动信号发生电路响应于振荡信号产生第一至第四电荷泵驱动信号。第一和第四电荷泵驱动信号中的每一个具有高于电源电压的高电压电平。因此，即使电源电压降低，由于电荷泵电路中的PMOS晶体管被具有高于电源电压的电压的电荷泵驱动信号驱动，所以可以防止泵效率的损失。

9. 发明授权

US5995434A Dynamic random access memory device having a self-refresh mode 失效
标题翻译：具有自刷新模式的动态随机存取存储器件
公开(公告)号：US5995434A
公开(公告)日：1999-11-30
申请号：US95931
申请日：1998-06-12
申请人： Hoon Ryu
发明人： Hoon Ryu
IPC分类号： G11C11/409 , G11C7/12 , G11C11/403 , G11C11/406 , G11C11/407 , G11C11/4074 , G11C11/4094 , G11C7/00
CPC分类号： G11C7/12 , G11C11/406 , G11C11/4074 , G11C11/4094
摘要： Is disclosed a semiconductor memory device having a self-refresh mode, the semiconductor memory device comprises a bit line precharge voltage generating circuit which is composed of a first voltage generator and a second voltage generator. The bit line precharge voltage generating circuit generates a bit line precharge voltage in response to a control signal indicating a self-refresh mode. During a time period in which the operating voltage is maintained at a first power supply voltage and the control signal is activated, the bit line precharge voltage is maintained at a voltage level between half the second power supply voltage and half the first power supply voltage though the operating voltage in the DRAM is changed from the second power supply voltage level to the first power supply voltage level. A voltage variation (or, a sense margin of a sense amplifier) on a bit line is increased, so that there is prevented a read malfunction for data `1` induced when the refresh operation is performed during the time period.
摘要翻译：公开了一种具有自刷新模式的半导体存储器件，该半导体存储器件包括由第一电压发生器和第二电压发生器组成的位线预充电电压产生电路。位线预充电电压产生电路响应于指示自刷新模式的控制信号产生位线预充电电压。在工作电压保持在第一电源电压并且控制信号被激活的时间段期间，位线预充电电压保持在第二电源电压的一半和第一电源电压的一半之间的电压电平 DRAM中的工作电压从第二电源电压电平变为第一电源电压电平。位线上的电压变化（或读出放大器的检测余量）增加，从而防止了在该时间段期间执行刷新操作时引起的数据“1”的读取故障。

10. 发明授权

US07802133B2 System and method for addressing errors in a multiple-chip memory device 有权
标题翻译：用于解决多芯片存储器件中的错误的系统和方法
公开(公告)号：US07802133B2
公开(公告)日：2010-09-21
申请号：US11819759
申请日：2007-06-29
申请人： KoonHee Lee , Ryan Patterson , Hoon Ryu , Klaus Nierle
发明人： KoonHee Lee , Ryan Patterson , Hoon Ryu , Klaus Nierle
IPC分类号： G06F11/00
CPC分类号： G11C29/802 , G11C5/04 , G11C2029/4402 , G11C2029/5606
摘要： A multiple-chip memory device, comprising: a volatile memory element configured to store a plurality of bits of information, and later access the plurality of bits of information; a non-volatile memory element configured to store initial repair information identifying one or more errors in the volatile memory element; and a master memory controller configured to read the initial repair information, and to provide processed repair information and volatile memory control signals to the volatile memory element, wherein the volatile memory element is configured to store and access the plurality of bits of information based on the processed repair information and logical address information.
摘要翻译：一种多芯片存储器件，包括：易失性存储器元件，被配置为存储多个位的信息，并且稍后访问所述多个位的信息; 非易失性存储器元件，被配置为存储识别所述易失性存储元件中的一个或多个错误的初始修复信息; 以及主存储器控制器，被配置为读取所述初始修复信息，并且向所述易失性存储器元件提供经处理的修复信息和易失性存储器控制信号，其中所述易失性存储器元件被配置为基于所述易失性存储器元件存储和访问所述多个位信息处理修复信息和逻辑地址信息。

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