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1. 发明授权

US07192873B1 Method of manufacturing nano scale semiconductor device using nano particles 有权
标题翻译：使用纳米颗粒制造纳米级半导体器件的方法
公开(公告)号：US07192873B1
公开(公告)日：2007-03-20
申请号：US11240473
申请日：2005-10-03
申请人： Hoon Kim , In-jae Song , Won-joo Kim , Byoung-Iyong Choi
发明人： Hoon Kim , In-jae Song , Won-joo Kim , Byoung-Iyong Choi
IPC分类号： H01L21/311
CPC分类号： H01L21/8238 , H01L21/3212 , H01L33/08 , H01L33/24 , Y10S977/755 , Y10S977/758 , Y10S977/773
摘要： Provided is a method of manufacturing a nano scale semiconductor device, such as a nano scale P-N junction device or a CMOS using nano particles without using a mask or a fine pattern. The method includes dispersing uniformly a plurality of nano particles on a semiconductor substrate, forming an insulating layer covering the nano particles on the semiconductor substrate, partly removing the upper surfaces of the nano particles and the insulating layer, selectively removing the nano particles from the insulating layer, and partly forming doped semiconductor layers in the semiconductor substrate by partly doping the semiconductor substrate through spaces formed by removing the nano particles.
摘要翻译：提供了一种使用纳米级P-N结器件或使用纳米颗粒的CMOS而不使用掩模或精细图案的纳米级半导体器件的制造方法。该方法包括在半导体衬底上均匀分散多个纳米颗粒，形成覆盖半导体衬底上的纳米颗粒的绝缘层，部分去除纳米颗粒和绝缘层的上表面，从绝缘体中选择性地除去纳米颗粒层，并且通过部分地通过去除纳米颗粒形成的空间将半导体衬底部分地掺杂在半导体衬底中部分地形成掺杂半导体层。

2. 发明申请

US20070054445A1 METHOD OF MANUFACTURING NANO SCALE SEMICONDUCTOR DEVICE USING NANO PARTICLES 有权
标题翻译：使用纳米颗粒制造纳米尺度半导体器件的方法
公开(公告)号：US20070054445A1
公开(公告)日：2007-03-08
申请号：US11240473
申请日：2005-10-03
申请人： Hoon Kim , In-jae Song , Won-joo Kim , Byoung-lyong Choi
发明人： Hoon Kim , In-jae Song , Won-joo Kim , Byoung-lyong Choi
IPC分类号： H01L21/338 , H01L21/461
CPC分类号： H01L21/8238 , H01L21/3212 , H01L33/08 , H01L33/24 , Y10S977/755 , Y10S977/758 , Y10S977/773
摘要： Provided is a method of manufacturing a nano scale semiconductor device, such as a nano scale P-N junction device or a CMOS using nano particles without using a mask or a fine pattern. The method includes dispersing uniformly a plurality of nano particles on a semiconductor substrate, forming an insulating layer covering the nano particles on the semiconductor substrate, partly removing the upper surfaces of the nano particles and the insulating layer, selectively removing the nano particles from the insulating layer, and partly forming doped semiconductor layers in the semiconductor substrate by partly doping the semiconductor substrate through spaces formed by removing the nano particles.
摘要翻译：提供了一种使用纳米级P-N结器件或使用纳米颗粒的CMOS而不使用掩模或精细图案的纳米级半导体器件的制造方法。该方法包括在半导体衬底上均匀分散多个纳米颗粒，形成覆盖半导体衬底上的纳米颗粒的绝缘层，部分去除纳米颗粒和绝缘层的上表面，从绝缘体中选择性地除去纳米颗粒层，并且通过部分地通过去除纳米颗粒形成的空间将半导体衬底部分地掺杂在半导体衬底中部分地形成掺杂半导体层。

3. 发明申请

US20050145896A1 Memory device and method of manufacturing the same 有权
标题翻译：存储器件及其制造方法
公开(公告)号：US20050145896A1
公开(公告)日：2005-07-07
申请号：US11002812
申请日：2004-12-03
申请人： In-jae Song , Won-joo Kim , Sun-ae Seo
发明人： In-jae Song , Won-joo Kim , Sun-ae Seo
IPC分类号： H01L21/8247 , H01L21/28 , H01L21/336 , H01L21/8242 , H01L27/115 , H01L29/423 , H01L29/788 , H01L29/792 , H01L29/76
CPC分类号： H01L29/792 , H01L21/28282 , H01L29/66833
摘要： A memory device and a method of fabricating the same are provided. The method includes forming a gate stack on a semiconductor substrate and partially exposing upper end portions of the semiconductor substrate by etching the gate stack to form a gate stack structure, and implanting a dopant into the exposed portions of the semiconductor substrate to form source and drain regions, wherein the gate stack structure is etched such that its width increases from top to bottom. Accordingly, it is possible to manufacture a memory device with high integration, using a simplified manufacture process.
摘要翻译：提供了一种存储器件及其制造方法。该方法包括在半导体衬底上形成栅极叠层，并通过蚀刻栅叠层来部分地暴露半导体衬底的上端部分以形成栅叠层结构，并将掺杂剂注入半导体衬底的暴露部分以形成源极和漏极区域，其中蚀刻栅极堆叠结构，使得其宽度从顶部向底部增加。因此，可以使用简化的制造工艺来制造具有高集成度的存储器件。

4. 发明授权

US07491997B2 Memory device and method of manufacturing the same 有权
标题翻译：存储器件及其制造方法
公开(公告)号：US07491997B2
公开(公告)日：2009-02-17
申请号：US11002812
申请日：2004-12-03
申请人： In-jae Song , Won-joo Kim , Sun-ae Seo
发明人： In-jae Song , Won-joo Kim , Sun-ae Seo
IPC分类号： H01L29/76
CPC分类号： H01L29/792 , H01L21/28282 , H01L29/66833
摘要： A memory device and a method of fabricating the same are provided. The method includes forming a gate stack on a semiconductor substrate and partially exposing upper end portions of the semiconductor substrate by etching the gate stack to form a gate stack structure, and implanting a dopant into the exposed portions of the semiconductor substrate to form source and drain regions, wherein the gate stack structure is etched such that its width increases from top to bottom. Accordingly, it is possible to manufacture a memory device with high integration, using a simplified manufacture process.
摘要翻译：提供了一种存储器件及其制造方法。该方法包括在半导体衬底上形成栅极叠层，并通过蚀刻栅叠层来部分地暴露半导体衬底的上端部分以形成栅叠层结构，并将掺杂剂注入半导体衬底的暴露部分以形成源极和漏极区域，其中蚀刻栅极堆叠结构，使得其宽度从顶部向底部增加。因此，可以使用简化的制造工艺来制造具有高集成度的存储器件。

5. 发明申请

US20060257753A1 Photomask and method thereof 审中-公开
标题翻译：光掩模及其方法
公开(公告)号：US20060257753A1
公开(公告)日：2006-11-16
申请号：US11356258
申请日：2006-02-17
申请人： Won-joo Kim , I-hun Song , Suk-pil Kim , Seung-hyuk Chang , Won-Il Ryu , Hoon Kim
发明人： Won-joo Kim , I-hun Song , Suk-pil Kim , Seung-hyuk Chang , Won-Il Ryu , Hoon Kim
IPC分类号： G03C5/00 , G21K5/00 , G03F1/00
CPC分类号： G21K1/062 , B82Y10/00 , B82Y40/00 , G03F1/24 , G21K2201/067
摘要： A photomask and method thereof. In an example method, a photomask may be manufactured by forming an oxide layer on a surface, patterning the oxide layer to form an oxide pattern, the oxide pattern including a plurality of oxide pattern bodies and a plurality of oxide windows, filling the plurality of oxide windows with an absorbent to form an absorbent pattern and reducing the plurality of oxide pattern bodies. An example photomask may include an oxide pattern-based absorbent pattern including a plurality of absorbent pattern bodies and a plurality of absorbent pattern windows.
摘要翻译：光掩模及其方法。在一个示例性方法中，可以通过在表面上形成氧化物层来形成光掩模，图案化氧化物层以形成氧化物图案，氧化物图案包括多个氧化物图案体和多个氧化物窗口，具有吸收剂的氧化物窗口以形成吸收图案并且还原多个氧化物图案体。示例性光掩模可以包括基于氧化物图案的吸收图案，其包括多个吸收图案体和多个吸收图案窗。

6. 发明授权

US08624665B2 Method of operating semiconductor device 有权
标题翻译：操作半导体器件的方法
公开(公告)号：US08624665B2
公开(公告)日：2014-01-07
申请号：US12462176
申请日：2009-07-30
申请人： Sang-moo Choi , Won-joo Kim , Tae-hee Lee , Dae-kil Cha
发明人： Sang-moo Choi , Won-joo Kim , Tae-hee Lee , Dae-kil Cha
IPC分类号： H03K3/01
CPC分类号： H01L27/10802 , G11C11/404 , G11C2207/2227 , G11C2211/4016 , H01L21/84 , H01L27/10844 , H01L29/7841
摘要： Provided is a method of operating a semiconductor device, wherein an operating mode is set by adjusting timing of a voltage pulse or by adjusting a voltage level of the voltage pulse.
摘要翻译：提供了一种操作半导体器件的方法，其中通过调整电压脉冲的定时或通过调节电压脉冲的电压电平来设置操作模式。

7. 发明授权

US08283711B2 Non-volatile memory devices having data storage layer 有权
标题翻译：具有数据存储层的非易失性存储器件
公开(公告)号：US08283711B2
公开(公告)日：2012-10-09
申请号：US12149209
申请日：2008-04-29
申请人： Young-gu Jin , Yoon-dong Park , Won-joo Kim , Seung-hoon Lee , Suk-pil Kim
发明人： Young-gu Jin , Yoon-dong Park , Won-joo Kim , Seung-hoon Lee , Suk-pil Kim
IPC分类号： H01L29/792
CPC分类号： G11C5/02 , G11C5/025 , H01L27/2409 , H01L27/249 , H01L45/04 , H01L45/06 , H01L45/1226 , H01L45/143 , H01L45/144 , H01L45/146
摘要： Provided are a non-volatile memory device, which may have a stacked structure and may be easily integrated at increased density, and a method of fabricating and using the non-volatile memory device. The non-volatile memory device may include at least one pair of first electrode lines. At least one second electrode line may be between the at least one pair of first electrode lines. At least one data storage layer may be between the at least one pair of first electrode lines and the at least one second electrode line and may locally store a resistance change.
摘要翻译：提供了一种非易失性存储器件，其可以具有堆叠结构并且可以容易地以增加的密度集成，以及制造和使用非易失性存储器件的方法。非易失性存储器件可以包括至少一对第一电极线。至少一个第二电极线可以在所述至少一对第一电极线之间。至少一个数据存储层可以在至少一对第一电极线和至少一个第二电极线之间，并且可以局部地存储电阻变化。

8. 发明授权

US08058701B2 Antifuse structures, antifuse array structures, methods of manufacturing the same 有权
标题翻译：防污结构，反熔丝阵列结构，制造方法
公开(公告)号：US08058701B2
公开(公告)日：2011-11-15
申请号：US12216094
申请日：2008-06-30
申请人： Deok-kee Kim , Yoon-dong Park , Seung-hoon Lee , I-hun Song , Won-joo Kim , Young-gu Jin , Hyuk-soon Choi , Suk-pil Kim
发明人： Deok-kee Kim , Yoon-dong Park , Seung-hoon Lee , I-hun Song , Won-joo Kim , Young-gu Jin , Hyuk-soon Choi , Suk-pil Kim
IPC分类号： H01L23/52
CPC分类号： H01L23/5252 , G11C17/16 , H01L27/1021 , H01L2924/0002 , H01L2924/00
摘要： Antifuse structures, antifuse arrays, methods of manufacturing, and methods of operating the same are provided. An antifuse structure includes bitlines formed as first diffusing regions within a semiconductor substrate, an insulation layer formed on the bitlines, and wordlines formed on the insulation layer. An antifuse array includes a plurality of antifuse structures arranged in an array.
摘要翻译：提供了防泡结构，反熔丝阵列，制造方法和操作方法。反熔丝结构包括在半导体衬底内形成为第一扩散区的位线，形成在位线上的绝缘层，以及形成在绝缘层上的字线。反熔丝阵列包括排列成阵列的多个反熔丝结构。

9. 发明授权

US08017477B2 Nonvolatile memory devices and methods of fabricating the same 失效
标题翻译：非易失性存储器件及其制造方法
公开(公告)号：US08017477B2
公开(公告)日：2011-09-13
申请号：US11704205
申请日：2007-02-09
申请人： Won-joo Kim , Suk-pil Kim , Yoon-dong Park
发明人： Won-joo Kim , Suk-pil Kim , Yoon-dong Park
IPC分类号： H01L21/336
CPC分类号： H01L27/115 , H01L27/11521 , H01L27/11568 , H01L29/42332 , H01L29/42336 , H01L29/42352 , H01L29/66621 , H01L29/7881 , H01L29/792
摘要： A nonvolatile memory device includes a plurality of first control gate electrodes, second control gate electrodes, first storage node films, and second storage node films. The first control gate electrodes are recessed into a semiconductor substrate. Each second control gate electrode is disposed between two adjacent first control gate electrodes. The second control gate electrodes are disposed on the semiconductor substrate over the first control gate electrodes. The first storage node films are disposed between the semiconductor substrate and the first control gate electrodes. The second storage node films are disposed between the semiconductor substrate and the second control gate electrodes. A method of fabricating the nonvolatile memory device includes forming the first storage node films, forming the first control gate electrodes, forming the second storage node films, and forming the second control gate electrodes.
摘要翻译：非易失性存储器件包括多个第一控制栅电极，第二控制栅电极，第一存储节点膜和第二存储节点膜。第一控制栅电极凹入半导体衬底。每个第二控制栅电极设置在两个相邻的第一控制栅电极之间。第二控制栅电极设置在第一控制栅电极上的半导体衬底上。第一存储节点膜设置在半导体衬底和第一控制栅电极之间。第二存储节点膜设置在半导体衬底和第二控制栅电极之间。一种制造非易失性存储器件的方法包括形成第一存储节点膜，形成第一控制栅电极，形成第二存储节点膜，以及形成第二控制栅电极。

10. 发明授权

US07961539B2 Method of operating semiconductor device 有权
标题翻译：操作半导体器件的方法
公开(公告)号：US07961539B2
公开(公告)日：2011-06-14
申请号：US12591202
申请日：2009-11-12
申请人： Sang-moo Choi , Won-joo Kim , Tae-hee Lee
发明人： Sang-moo Choi , Won-joo Kim , Tae-hee Lee
IPC分类号： G11C13/00
CPC分类号： H01L27/108 , H01L27/10802 , H01L27/10844 , H01L29/7841 , H01L29/78654
摘要： Provided is a method of operating a semiconductor device, in which a gate voltage or a drain voltage is adjusted in order to add carriers to or remove carriers from a body region, thereby realizing semiconductor having a plurality of data states.
摘要翻译：提供了一种操作半导体器件的方法，其中调整栅极电压或漏极电压以便将载体添加到身体区域或从身体区域移除载体，从而实现具有多个数据状态的半导体。

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