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1. 发明申请

US20050035408A1 Methods of fabricating a dielectric plug in MOSFETs to suppress short-channel effects 有权
标题翻译：在MOSFET中制造电介质塞以抑制短沟道效应的方法
公开(公告)号：US20050035408A1
公开(公告)日：2005-02-17
申请号：US10931507
申请日：2004-09-01
申请人： Hongmei Wang , Zhongze Wang
发明人： Hongmei Wang , Zhongze Wang
IPC分类号： H01L21/336 , H01L29/06 , H01L29/94 , H01L21/338 , H01L29/76 , H01L31/062 , H01L31/113 , H01L31/119 , H01L47/00
CPC分类号： H01L29/66628 , H01L29/0649 , H01L29/0653 , H01L29/66636
摘要： The invention provides a technique to fabricate a dielectric plug in a MOSFET. The dielectric plug is fabricated by forming an oxide layer over exposed source and drain regions in the substrate including a gate electrode stack. The formed oxide layer in the source and drain regions are then substantially removed to expose the substrate in the source and drain regions and to leave a portion of the oxide layer under the gate electrode stack to form the dielectric plug and a channel region between the source and drain regions.
摘要翻译：本发明提供了一种制造MOSFET中的电介质塞的技术。通过在包括栅极电极堆叠的衬底中的暴露的源极和漏极区域上形成氧化物层来制造电介质插塞。然后基本上除去源极和漏极区域中形成的氧化物层以暴露源极和漏极区域中的衬底并且将氧化物层的一部分留在栅极电极堆叠下方以形成电介质插塞以及在源极之间的沟道区域和漏区。

2. 发明授权

US06977419B2 MOSFETs including a dielectric plug to suppress short-channel effects 有权
标题翻译： MOSFET包括电介质塞以抑制短沟道效应
公开(公告)号：US06977419B2
公开(公告)日：2005-12-20
申请号：US10931507
申请日：2004-09-01
申请人： Hongmei Wang , Zhongze Wang
发明人： Hongmei Wang , Zhongze Wang
IPC分类号： H01L21/336 , H01L29/06
CPC分类号： H01L29/66628 , H01L29/0649 , H01L29/0653 , H01L29/66636
摘要： The invention provides a technique to fabricate a dielectric plug in a MOSFET. The dielectric plug is fabricated by forming an oxide layer over exposed source and drain regions in the substrate including a gate electrode stack. The formed oxide layer in the source and drain regions are then substantially removed to expose the substrate in the source and drain regions and to leave a portion of the oxide layer under the gate electrode stack to form the dielectric plug and a channel region between the source and drain regions.
摘要翻译：本发明提供了一种制造MOSFET中的电介质塞的技术。通过在包括栅极电极堆叠的衬底中的暴露的源极和漏极区域上形成氧化物层来制造电介质插塞。然后基本上除去源极和漏极区域中形成的氧化物层以暴露源极和漏极区域中的衬底并且将氧化物层的一部分留在栅极电极堆叠下方以形成电介质插塞以及在源极之间的沟道区域和漏区。

3. 发明授权

US06812103B2 Methods of fabricating a dielectric plug in MOSFETS to suppress short-channel effects 有权
标题翻译：在MOSFET中制造电介质塞以抑制短沟道效应的方法
公开(公告)号：US06812103B2
公开(公告)日：2004-11-02
申请号：US10175774
申请日：2002-06-20
申请人： Hongmei Wang , Zhongze Wang
发明人： Hongmei Wang , Zhongze Wang
IPC分类号： H01L21336
CPC分类号： H01L29/66628 , H01L29/0649 , H01L29/0653 , H01L29/66636
摘要： The invention provides a technique to fabricate a dielectric plug in a MOSFET. The dielectric plug is fabricated by forming an oxide layer over exposed source and drain regions in the substrate including a gate electrode stack. The formed oxide layer in the source and drain regions are then substantially removed to expose the substrate in the source and drain regions and to leave a portion of the oxide layer under the gate electrode stack to form the dielectric plug and a channel region between the source and drain regions.
摘要翻译：本发明提供了一种制造MOSFET中的电介质塞的技术。通过在包括栅极电极堆叠的衬底中的暴露的源极和漏极区域上形成氧化物层来制造电介质插塞。然后基本上除去源极和漏极区域中形成的氧化物层以暴露源极和漏极区域中的衬底并且将氧化物层的一部分留在栅极电极堆叠下方以形成电介质插塞以及源极之间的沟道区域和漏区。

4. 发明授权

US07154146B2 Dielectric plug in mosfets to suppress short-channel effects 有权
公开(公告)号：US07154146B2
公开(公告)日：2006-12-26
申请号：US11283015
申请日：2005-11-18
申请人： Hongmei Wang , Zhongze Wang
发明人： Hongmei Wang , Zhongze Wang
IPC分类号： H01L21/336
CPC分类号： H01L29/66628 , H01L29/0649 , H01L29/0653 , H01L29/66636
摘要： The invention provides a technique to fabricate a dielectric plug in a MOSFET. The invention includes apparatus and systems that include one or more devices including a MOSFET having a dielectric plug. The dielectric plug is fabricated by forming an oxide layer over exposed source and drain regions in the substrate including a gate electrode stack. The formed oxide layer in the source and drain regions are then substantially removed to expose the substrate in the source and drain regions and to leave a portion of the oxide layer under the gate electrode stack to form the dielectric plug and a channel region between the source and drain regions.

5. 发明申请

US20060076619A1 Dielectric plug in mosfets to suppress short-channel effects 有权
标题翻译：介质插头在mosfets中抑制短路效应
公开(公告)号：US20060076619A1
公开(公告)日：2006-04-13
申请号：US11283015
申请日：2005-11-18
申请人： Hongmei Wang , Zhongze Wang
发明人： Hongmei Wang , Zhongze Wang
IPC分类号： H01L29/76
CPC分类号： H01L29/66628 , H01L29/0649 , H01L29/0653 , H01L29/66636
摘要： The invention provides a technique to fabricate a dielectric plug in a MOSFET. The invention includes apparatus and systems that include one or more devices including a MOSFET having a dielectric plug. The dielectric plug is fabricated by forming an oxide layer over exposed source and drain regions in the substrate including a gate electrode stack. The formed oxide layer in the source and drain regions are then substantially removed to expose the substrate in the source and drain regions and to leave a portion of the oxide layer under the gate electrode stack to form the dielectric plug and a channel region between the source and drain regions.
摘要翻译：本发明提供了一种制造MOSFET中的电介质塞的技术。本发明包括包括一个或多个器件的器件和系统，该器件和系统包括具有电介质插塞的MOSFET。通过在包括栅极电极堆叠的衬底中的暴露的源极和漏极区域上形成氧化物层来制造电介质插塞。然后基本上除去源极和漏极区域中形成的氧化物层以暴露源极和漏极区域中的衬底，并且将氧化物层的一部分留在栅极电极堆叠下方以形成电介质插塞以及源极之间的沟道区域和漏区。

6. 发明授权

US09575727B2 Methods for generating random data using phase change materials and related devices and systems 有权
标题翻译：使用相变材料和相关设备和系统生成随机数据的方法
公开(公告)号：US09575727B2
公开(公告)日：2017-02-21
申请号：US14497777
申请日：2014-09-26
申请人： Karthik Sarpatwari , Hongmei Wang , Sanjay Rangan
发明人： Karthik Sarpatwari , Hongmei Wang , Sanjay Rangan
IPC分类号： G06F7/58 , G09C1/00 , G11C13/00 , H04L9/08 , H04L9/32
CPC分类号： G06F21/44 , G06F7/58 , G06F7/588 , G09C1/00 , G11C13/0004 , G11C13/0069 , G11C13/0097 , G11C2013/0092 , H04L9/0866 , H04L9/3278 , H04L2209/12
摘要： Devices and systems operable to generate random numbers are disclosed and described. Such include an array of phase change material cells electrically coupled to circuitry configured to initially set all cells in the array to a high state, send a programming pulse through the array having a current sufficient to randomly set each cell to either the high state or a low state to generate a random distribution of cell states across the array, and to read the random distribution of cell states out of the array.
摘要翻译：公开和描述了可操作以产生随机数的装置和系统。这样包括电耦合到被配置为初始地将阵列中的所有单元设置为高状态的电路的相变材料单元的阵列，通过阵列发送编程脉冲，该阵列具有足以将每个单元随机地设置为高状态或低状态以在阵列上产生单元状态的随机分布，并且读取阵列外的单元状态的随机分布。

7. 发明授权

US08273619B2 Methods of implanting dopant into channel regions 失效
标题翻译：将掺杂剂注入通道区域的方法
公开(公告)号：US08273619B2
公开(公告)日：2012-09-25
申请号：US12848662
申请日：2010-08-02
申请人： Hongmei Wang , Kurt D. Beigel , Fred D. Fishburn , Rongsheng Yang
发明人： Hongmei Wang , Kurt D. Beigel , Fred D. Fishburn , Rongsheng Yang
IPC分类号： H01L21/8238
CPC分类号： H01L21/26513 , H01L21/324 , H01L21/823412 , H01L27/0811 , H01L27/088 , H01L29/66537 , H01L29/7833
摘要： The invention includes methods of forming channel region implants for two transistor devices simultaneously, in which a mask is utilized to block a larger percentage of a channel region location of one of the devices relative to the other. The invention also pertains to methods of forming capacitor structures in which a first capacitor electrode is spaced from a semiconductor substrate by a dielectric material, a second capacitor electrode comprises a conductively-doped diffusion region within the semiconductor material, and a capacitor channel region location is beneath the dielectric material and adjacent the conductively-doped diffusion region. An implant mask is formed to cover only a first portion of the capacitor channel region location and to leave a second portion of the capacitor channel region location uncovered. While the implant mask is in place, dopant is implanted into the uncovered second portion of the capacitor channel region location.
摘要翻译：本发明包括同时形成两个晶体管器件的沟道区域植入物的方法，其中掩模用于阻挡相对于另一个器件之一的较大百分比的沟道区域位置。本发明还涉及形成电容器结构的方法，其中第一电容器电极通过电介质材料与半导体衬底隔开，第二电容器电极包括半导体材料内的导电掺杂扩散区，电容器通道区位置为在介电材料的下方并与导电掺杂的扩散区相邻。形成注入掩模以仅覆盖电容器沟道区位置的第一部分并且留下未覆盖的电容器沟道区位置的第二部分。当植入掩模就位时，掺杂剂被注入到电容器通道区域位置的未覆盖的第二部分中。

8. 发明申请

US20100297822A1 Methods of forming capacitor structures, methods of forming threshold voltage implant regions, and methods of implanting dopant into channel regions 失效
标题翻译：形成电容器结构的方法，形成阈值电压注入区域的方法以及将掺杂剂注入沟道区域的方法
公开(公告)号：US20100297822A1
公开(公告)日：2010-11-25
申请号：US12848662
申请日：2010-08-02
申请人： Hongmei Wang , Kurt D. Beigel , Fred D. Fishburn , Rongsheng Yang
发明人： Hongmei Wang , Kurt D. Beigel , Fred D. Fishburn , Rongsheng Yang
IPC分类号： H01L21/336 , H01L21/265
CPC分类号： H01L21/26513 , H01L21/324 , H01L21/823412 , H01L27/0811 , H01L27/088 , H01L29/66537 , H01L29/7833
摘要： The invention includes methods of forming channel region implants for two transistor devices simultaneously, in which a mask is utilized to block a larger percentage of a channel region location of one of the devices relative to the other. The invention also pertains to methods of forming capacitor structures in which a first capacitor electrode is spaced from a semiconductor substrate by a dielectric material, a second capacitor electrode comprises a conductively-doped diffusion region within the semiconductor material, and a capacitor channel region location is beneath the dielectric material and adjacent the conductively-doped diffusion region. An implant mask is formed to cover only a first portion of the capacitor channel region location and to leave a second portion of the capacitor channel region location uncovered. While the implant mask is in place, dopant is implanted into the uncovered second portion of the capacitor channel region location.
摘要翻译：本发明包括同时形成两个晶体管器件的沟道区域植入物的方法，其中掩模用于阻挡相对于另一个器件之一的较大百分比的沟道区域位置。本发明还涉及形成电容器结构的方法，其中第一电容器电极通过电介质材料与半导体衬底隔开，第二电容器电极包括半导体材料内的导电掺杂扩散区，电容器通道区位置为在介电材料的下方并与导电掺杂的扩散区相邻。形成注入掩模以仅覆盖电容器沟道区位置的第一部分并且留下未覆盖的电容器沟道区位置的第二部分。当植入掩模就位时，掺杂剂被注入到电容器通道区域位置的未覆盖的第二部分中。

9. 发明授权

US07767514B2 Methods of implanting dopant into channel regions 有权
标题翻译：将掺杂剂注入通道区域的方法
公开(公告)号：US07767514B2
公开(公告)日：2010-08-03
申请号：US11406863
申请日：2006-04-18
申请人： Hongmei Wang , Kurt D. Beigel , Fred D. Fishburn , Rongsheng Yang
发明人： Hongmei Wang , Kurt D. Beigel , Fred D. Fishburn , Rongsheng Yang
IPC分类号： H01L21/8238
CPC分类号： H01L21/26513 , H01L21/324 , H01L21/823412 , H01L27/0811 , H01L27/088 , H01L29/66537 , H01L29/7833
摘要： The invention includes methods of forming channel region implants for two transistor devices simultaneously, in which a mask is utilized to block a larger percentage of a channel region location of one of the devices relative to the other. The invention also pertains to methods of forming capacitor structures in which a first capacitor electrode is spaced from a semiconductor substrate by a dielectric material, a second capacitor electrode comprises a conductively-doped diffusion region within the semiconductor material, and a capacitor channel region location is beneath the dielectric material and adjacent the conductively-doped diffusion region. An implant mask is formed to cover only a first portion of the capacitor channel region location and to leave a second portion of the capacitor channel region location uncovered. While the implant mask is in place, dopant is implanted into the uncovered second portion of the capacitor channel region location.
摘要翻译：本发明包括同时形成两个晶体管器件的沟道区域植入物的方法，其中掩模用于阻挡相对于另一个器件之一的较大百分比的沟道区域位置。本发明还涉及形成电容器结构的方法，其中第一电容器电极通过电介质材料与半导体衬底隔开，第二电容器电极包括半导体材料内的导电掺杂扩散区，电容器通道区位置为在介电材料的下方并与导电掺杂的扩散区相邻。形成注入掩模以仅覆盖电容器沟道区位置的第一部分并且留下未覆盖的电容器沟道区位置的第二部分。当植入掩模就位时，掺杂剂被注入到电容器通道区域位置的未覆盖的第二部分中。

10. 发明授权

US07674670B2 Methods of forming threshold voltage implant regions 失效
标题翻译：形成阈值电压注入区域的方法
公开(公告)号：US07674670B2
公开(公告)日：2010-03-09
申请号：US11406893
申请日：2006-04-18
申请人： Hongmei Wang , Kurt D. Beigel , Fred D. Fishburn , Rongsheng Yang
发明人： Hongmei Wang , Kurt D. Beigel , Fred D. Fishburn , Rongsheng Yang
IPC分类号： H01L21/8238
CPC分类号： H01L21/26513 , H01L21/324 , H01L21/823412 , H01L27/0811 , H01L27/088 , H01L29/66537 , H01L29/7833
摘要： The invention includes methods of forming channel region implants for two transistor devices simultaneously, in which a mask is utilized to block a larger percentage of a channel region location of one of the devices relative to the other. The invention also pertains to methods of forming capacitor structures in which a first capacitor electrode is spaced from a semiconductor substrate by a dielectric material, a second capacitor electrode comprises a conductively-doped diffusion region within the semiconductor material, and a capacitor channel region location is beneath the dielectric material and adjacent the conductively-doped diffusion region. An implant mask is formed to cover only a first portion of the capacitor channel region location and to leave a second portion of the capacitor channel region location uncovered. While the implant mask is in place, dopant is implanted into the uncovered second portion of the capacitor channel region location.
摘要翻译：本发明包括同时形成两个晶体管器件的沟道区域植入物的方法，其中掩模用于阻挡相对于另一个器件之一的较大百分比的沟道区域位置。本发明还涉及形成电容器结构的方法，其中第一电容器电极通过电介质材料与半导体衬底隔开，第二电容器电极包括半导体材料内的导电掺杂扩散区，电容器通道区位置为在介电材料的下方并与导电掺杂的扩散区相邻。形成注入掩模以仅覆盖电容器沟道区位置的第一部分并且留下未覆盖的电容器沟道区位置的第二部分。当植入掩模就位时，掺杂剂被注入到电容器通道区域位置的未覆盖的第二部分中。

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