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1. 发明授权

US07442600B2 Methods of forming threshold voltage implant regions 失效
标题翻译：形成阈值电压注入区域的方法
公开(公告)号：US07442600B2
公开(公告)日：2008-10-28
申请号：US10925736
申请日：2004-08-24
申请人： Hongmei Wang , Kurt D. Beigel , Fred D. Fishburn , Rongsheng Yang
发明人： Hongmei Wang , Kurt D. Beigel , Fred D. Fishburn , Rongsheng Yang
IPC分类号： H01L21/8238
CPC分类号： H01L21/26513 , H01L21/324 , H01L21/823412 , H01L27/0811 , H01L27/088 , H01L29/66537 , H01L29/7833
摘要： The invention includes methods of forming channel region implants for two transistor devices simultaneously, in which a mask is utilized to block a larger percentage of a channel region location of one of the devices relative to the other. The invention also pertains to methods of forming capacitor structures in which a first capacitor electrode is spaced from a semiconductor substrate by a dielectric material, a second capacitor electrode comprises a conductively-doped diffusion region within the semiconductor material, and a capacitor channel region location is beneath the dielectric material and adjacent the conductively-doped diffusion region. An implant mask is formed to cover only a first portion of the capacitor channel region location and to leave a second portion of the capacitor channel region location uncovered. While the implant mask is in place, dopant is implanted into the uncovered second portion of the capacitor channel region location.
摘要翻译：本发明包括同时形成两个晶体管器件的沟道区域植入物的方法，其中掩模用于阻挡相对于另一个器件之一的较大百分比的沟道区域位置。本发明还涉及形成电容器结构的方法，其中第一电容器电极通过电介质材料与半导体衬底隔开，第二电容器电极包括半导体材料内的导电掺杂扩散区，电容器通道区位置为在介电材料的下方并与导电掺杂的扩散区相邻。形成注入掩模以仅覆盖电容器沟道区位置的第一部分并且留下未覆盖的电容器沟道区位置的第二部分。当植入掩模就位时，掺杂剂被注入到电容器通道区域位置的未覆盖的第二部分中。

2. 发明授权

US08273619B2 Methods of implanting dopant into channel regions 失效
标题翻译：将掺杂剂注入通道区域的方法
公开(公告)号：US08273619B2
公开(公告)日：2012-09-25
申请号：US12848662
申请日：2010-08-02
申请人： Hongmei Wang , Kurt D. Beigel , Fred D. Fishburn , Rongsheng Yang
发明人： Hongmei Wang , Kurt D. Beigel , Fred D. Fishburn , Rongsheng Yang
IPC分类号： H01L21/8238
CPC分类号： H01L21/26513 , H01L21/324 , H01L21/823412 , H01L27/0811 , H01L27/088 , H01L29/66537 , H01L29/7833
摘要： The invention includes methods of forming channel region implants for two transistor devices simultaneously, in which a mask is utilized to block a larger percentage of a channel region location of one of the devices relative to the other. The invention also pertains to methods of forming capacitor structures in which a first capacitor electrode is spaced from a semiconductor substrate by a dielectric material, a second capacitor electrode comprises a conductively-doped diffusion region within the semiconductor material, and a capacitor channel region location is beneath the dielectric material and adjacent the conductively-doped diffusion region. An implant mask is formed to cover only a first portion of the capacitor channel region location and to leave a second portion of the capacitor channel region location uncovered. While the implant mask is in place, dopant is implanted into the uncovered second portion of the capacitor channel region location.
摘要翻译：本发明包括同时形成两个晶体管器件的沟道区域植入物的方法，其中掩模用于阻挡相对于另一个器件之一的较大百分比的沟道区域位置。本发明还涉及形成电容器结构的方法，其中第一电容器电极通过电介质材料与半导体衬底隔开，第二电容器电极包括半导体材料内的导电掺杂扩散区，电容器通道区位置为在介电材料的下方并与导电掺杂的扩散区相邻。形成注入掩模以仅覆盖电容器沟道区位置的第一部分并且留下未覆盖的电容器沟道区位置的第二部分。当植入掩模就位时，掺杂剂被注入到电容器通道区域位置的未覆盖的第二部分中。

3. 发明申请

US20100297822A1 Methods of forming capacitor structures, methods of forming threshold voltage implant regions, and methods of implanting dopant into channel regions 失效
标题翻译：形成电容器结构的方法，形成阈值电压注入区域的方法以及将掺杂剂注入沟道区域的方法
公开(公告)号：US20100297822A1
公开(公告)日：2010-11-25
申请号：US12848662
申请日：2010-08-02
申请人： Hongmei Wang , Kurt D. Beigel , Fred D. Fishburn , Rongsheng Yang
发明人： Hongmei Wang , Kurt D. Beigel , Fred D. Fishburn , Rongsheng Yang
IPC分类号： H01L21/336 , H01L21/265
CPC分类号： H01L21/26513 , H01L21/324 , H01L21/823412 , H01L27/0811 , H01L27/088 , H01L29/66537 , H01L29/7833
摘要： The invention includes methods of forming channel region implants for two transistor devices simultaneously, in which a mask is utilized to block a larger percentage of a channel region location of one of the devices relative to the other. The invention also pertains to methods of forming capacitor structures in which a first capacitor electrode is spaced from a semiconductor substrate by a dielectric material, a second capacitor electrode comprises a conductively-doped diffusion region within the semiconductor material, and a capacitor channel region location is beneath the dielectric material and adjacent the conductively-doped diffusion region. An implant mask is formed to cover only a first portion of the capacitor channel region location and to leave a second portion of the capacitor channel region location uncovered. While the implant mask is in place, dopant is implanted into the uncovered second portion of the capacitor channel region location.
摘要翻译：本发明包括同时形成两个晶体管器件的沟道区域植入物的方法，其中掩模用于阻挡相对于另一个器件之一的较大百分比的沟道区域位置。本发明还涉及形成电容器结构的方法，其中第一电容器电极通过电介质材料与半导体衬底隔开，第二电容器电极包括半导体材料内的导电掺杂扩散区，电容器通道区位置为在介电材料的下方并与导电掺杂的扩散区相邻。形成注入掩模以仅覆盖电容器沟道区位置的第一部分并且留下未覆盖的电容器沟道区位置的第二部分。当植入掩模就位时，掺杂剂被注入到电容器通道区域位置的未覆盖的第二部分中。

4. 发明授权

US07767514B2 Methods of implanting dopant into channel regions 有权
标题翻译：将掺杂剂注入通道区域的方法
公开(公告)号：US07767514B2
公开(公告)日：2010-08-03
申请号：US11406863
申请日：2006-04-18
申请人： Hongmei Wang , Kurt D. Beigel , Fred D. Fishburn , Rongsheng Yang
发明人： Hongmei Wang , Kurt D. Beigel , Fred D. Fishburn , Rongsheng Yang
IPC分类号： H01L21/8238
CPC分类号： H01L21/26513 , H01L21/324 , H01L21/823412 , H01L27/0811 , H01L27/088 , H01L29/66537 , H01L29/7833
摘要： The invention includes methods of forming channel region implants for two transistor devices simultaneously, in which a mask is utilized to block a larger percentage of a channel region location of one of the devices relative to the other. The invention also pertains to methods of forming capacitor structures in which a first capacitor electrode is spaced from a semiconductor substrate by a dielectric material, a second capacitor electrode comprises a conductively-doped diffusion region within the semiconductor material, and a capacitor channel region location is beneath the dielectric material and adjacent the conductively-doped diffusion region. An implant mask is formed to cover only a first portion of the capacitor channel region location and to leave a second portion of the capacitor channel region location uncovered. While the implant mask is in place, dopant is implanted into the uncovered second portion of the capacitor channel region location.
摘要翻译：本发明包括同时形成两个晶体管器件的沟道区域植入物的方法，其中掩模用于阻挡相对于另一个器件之一的较大百分比的沟道区域位置。本发明还涉及形成电容器结构的方法，其中第一电容器电极通过电介质材料与半导体衬底隔开，第二电容器电极包括半导体材料内的导电掺杂扩散区，电容器通道区位置为在介电材料的下方并与导电掺杂的扩散区相邻。形成注入掩模以仅覆盖电容器沟道区位置的第一部分并且留下未覆盖的电容器沟道区位置的第二部分。当植入掩模就位时，掺杂剂被注入到电容器通道区域位置的未覆盖的第二部分中。

5. 发明授权

US07674670B2 Methods of forming threshold voltage implant regions 失效
标题翻译：形成阈值电压注入区域的方法
公开(公告)号：US07674670B2
公开(公告)日：2010-03-09
申请号：US11406893
申请日：2006-04-18
申请人： Hongmei Wang , Kurt D. Beigel , Fred D. Fishburn , Rongsheng Yang
发明人： Hongmei Wang , Kurt D. Beigel , Fred D. Fishburn , Rongsheng Yang
IPC分类号： H01L21/8238
CPC分类号： H01L21/26513 , H01L21/324 , H01L21/823412 , H01L27/0811 , H01L27/088 , H01L29/66537 , H01L29/7833
摘要： The invention includes methods of forming channel region implants for two transistor devices simultaneously, in which a mask is utilized to block a larger percentage of a channel region location of one of the devices relative to the other. The invention also pertains to methods of forming capacitor structures in which a first capacitor electrode is spaced from a semiconductor substrate by a dielectric material, a second capacitor electrode comprises a conductively-doped diffusion region within the semiconductor material, and a capacitor channel region location is beneath the dielectric material and adjacent the conductively-doped diffusion region. An implant mask is formed to cover only a first portion of the capacitor channel region location and to leave a second portion of the capacitor channel region location uncovered. While the implant mask is in place, dopant is implanted into the uncovered second portion of the capacitor channel region location.
摘要翻译：本发明包括同时形成两个晶体管器件的沟道区域植入物的方法，其中掩模用于阻挡相对于另一个器件之一的较大百分比的沟道区域位置。本发明还涉及形成电容器结构的方法，其中第一电容器电极通过电介质材料与半导体衬底隔开，第二电容器电极包括半导体材料内的导电掺杂扩散区，电容器通道区位置为在介电材料的下方并与导电掺杂的扩散区相邻。形成注入掩模以仅覆盖电容器沟道区位置的第一部分并且留下未覆盖的电容器沟道区位置的第二部分。当植入掩模就位时，掺杂剂被注入到电容器通道区域位置的未覆盖的第二部分中。

6. 发明授权

US07638392B2 Methods of forming capacitor structures 失效
标题翻译：形成电容器结构的方法
公开(公告)号：US07638392B2
公开(公告)日：2009-12-29
申请号：US11406862
申请日：2006-04-18
申请人： Hongmei Wang , Kurt D. Beigel , Fred D. Fishburn , Rongsheng Yang
发明人： Hongmei Wang , Kurt D. Beigel , Fred D. Fishburn , Rongsheng Yang
IPC分类号： H01L21/8242
CPC分类号： H01L21/26513 , H01L21/324 , H01L21/823412 , H01L27/0811 , H01L27/088 , H01L29/66537 , H01L29/7833
摘要： The invention includes methods of forming channel region implants for two transistor devices simultaneously, in which a mask is utilized to block a larger percentage of a channel region location of one of the devices relative to the other. The invention also pertains to methods of forming capacitor structures in which a first capacitor electrode is spaced from a semiconductor substrate by a dielectric material, a second capacitor electrode comprises a conductively-doped diffusion region within the semiconductor material, and a capacitor channel region location is beneath the dielectric material and adjacent the conductively-doped diffusion region. An implant mask is formed to cover only a first portion of the capacitor channel region location and to leave a second portion of the capacitor channel region location uncovered. While the implant mask is in place, dopant is implanted into the uncovered second portion of the capacitor channel region location.
摘要翻译：本发明包括同时形成两个晶体管器件的沟道区域植入物的方法，其中掩模用于阻挡相对于另一个器件之一的较大百分比的沟道区域位置。本发明还涉及形成电容器结构的方法，其中第一电容器电极通过电介质材料与半导体衬底隔开，第二电容器电极包括半导体材料内的导电掺杂扩散区，电容器通道区位置为在介电材料的下方并与导电掺杂的扩散区相邻。形成注入掩模以仅覆盖电容器沟道区位置的第一部分并且留下未覆盖的电容器沟道区位置的第二部分。当植入掩模就位时，掺杂剂被注入到电容器通道区域位置的未覆盖的第二部分中。

7. 发明申请

US20120099366A1 MULTI-RESISTIVE INTEGRATED CIRCUIT MEMORY 有权
标题翻译：多电阻集成电路存储器
公开(公告)号：US20120099366A1
公开(公告)日：2012-04-26
申请号：US13345417
申请日：2012-01-06
申请人： R Jacob Baker , Kurt D. Beigel
发明人： R Jacob Baker , Kurt D. Beigel
IPC分类号： G11C11/00
CPC分类号： H01L28/82 , G11C5/04 , G11C11/15 , H01L23/5223 , H01L27/0214 , H01L27/0805 , H01L2924/0002 , Y10S257/905 , Y10S257/906 , Y10S257/908 , H01L2924/00
摘要： A capacitor for use in integrated circuits comprises a layer of conductive material. The layer of conductive material including at least a first portion and a second portion, wherein the first portion and the second portion are arranged in a predetermined pattern relative to one another to provide a maximum amount of capacitance per semiconductor die area.
摘要翻译：用于集成电路的电容器包括一层导电材料。所述导电材料层包括至少第一部分和第二部分，其中所述第一部分和所述第二部分相对于彼此以预定图案布置，以提供每半导体管芯面积的最大量的电容。

8. 发明申请

US20120001245A1 Recessed Access Device for a Memory 有权
标题翻译：嵌入式存储设备
公开(公告)号：US20120001245A1
公开(公告)日：2012-01-05
申请号：US13231554
申请日：2011-09-13
申请人： Kurt D. Beigel , Jigish D. Trivedi , Kevin G. Duesman
发明人： Kurt D. Beigel , Jigish D. Trivedi , Kevin G. Duesman
IPC分类号： H01L27/108 , H01L27/105
CPC分类号： H01L29/66621 , H01L27/10876
摘要： Semiconductor memory devices having recessed access devices are disclosed. In some embodiments, a method of forming the recessed access device includes forming a device recess in a substrate material that extends to a first depth in the substrate that includes a gate oxide layer in the recess. The device recess may be extended to a second depth that is greater that the first depth to form an extended portion of the device recess. A field oxide layer may be provided within an interior of the device recess that extends inwardly into the interior of the device recess and into the substrate. Active regions may be formed in the substrate that abut the field oxide layer, and a gate material may be deposited into the device recess.
摘要翻译：公开了具有凹入式存取装置的半导体存储器件。在一些实施例中，形成凹陷进入装置的方法包括在衬底材料中形成器件凹部，该衬底材料延伸到衬底中的第一深度，该第一深度包括凹陷中的栅极氧化物层。装置凹部可以延伸到大于第一深度的第二深度，以形成装置凹部的延伸部分。场氧化物层可以设置在器件凹部的内部，其内部延伸到器件凹部的内部并进入衬底。活性区域可以形成在衬底中，其邻接场氧化物层，并且栅极材料可以沉积到器件凹部中。

9. 发明授权

US07642591B2 Multi-resistive integrated circuit memory 有权
标题翻译：多电阻集成电路存储器
公开(公告)号：US07642591B2
公开(公告)日：2010-01-05
申请号：US11379441
申请日：2006-04-20
申请人： R. Jacob Baker , Kurt D. Beigel
发明人： R. Jacob Baker , Kurt D. Beigel
IPC分类号： H01L41/00
CPC分类号： H01L28/82 , G11C5/04 , G11C11/15 , H01L23/5223 , H01L27/0214 , H01L27/0805 , H01L2924/0002 , Y10S257/905 , Y10S257/906 , Y10S257/908 , H01L2924/00
摘要： A capacitor for use in integrated circuits comprises a layer of conductive material. The layer of conductive material including at least a first portion and a second portion, wherein the first portion and the second portion are arranged in a predetermined pattern relative to one another to provide a maximum amount of capacitance per semiconductor die area.
摘要翻译：用于集成电路的电容器包括一层导电材料。所述导电材料层包括至少第一部分和第二部分，其中所述第一部分和所述第二部分相对于彼此以预定图案布置，以提供每半导体管芯面积的最大量的电容。

10. 发明授权

US07054208B2 Method and device for testing a sense amp 失效
标题翻译：检测放大器的方法和装置
公开(公告)号：US07054208B2
公开(公告)日：2006-05-30
申请号：US11076472
申请日：2005-03-08
申请人： Kurt D. Beigel , Douglas J. Cutter
发明人： Kurt D. Beigel , Douglas J. Cutter
IPC分类号： G11C7/00
CPC分类号： G11C29/026 , G11C11/401 , G11C29/02 , G11C29/025 , G11C29/028 , G11C29/12 , G11C29/44 , G11C29/48 , G11C29/50 , G11C29/50012 , G11C29/56 , G11C2029/5004
摘要： As part of a memory array, a circuit is provided for altering the drive applied to an access transistor that regulates electrical communication within the memory array. In one embodiment, the circuit is used to alter the drive applied to a sense amp's voltage-pulling transistor, thereby allowing modification of the voltage-pulling rate for components of the sense amp. A sample of test data is written to the memory array and read several times at varying drive rates in order to determine the sense amp's ability to accommodate external circuitry. In another embodiment, the circuit is used to alter the drive applied to a bleeder device that regulates communication between the digit lines of the memory array and its cell plate. Slowing communication allows defects within the memory array to have a more pronounced effect and hence increases the chances of finding such defects during testing. The circuit is configured to accept and apply a plurality of voltages, either through a contact pad or from a series of discrete voltage sources coupled to the circuit.
摘要翻译：作为存储器阵列的一部分，提供了用于改变施加到调节存储器阵列内的电通信的存取晶体管的驱动电路的电路。在一个实施例中，该电路用于改变施加到感测放大器的电压 - 牵引晶体管的驱动，从而允许改变感测放大器部件的电压提升率。将测试数据的样本写入存储器阵列，并以变化的驱动速率读取数次，以便确定感测放大器容纳外部电路的能力。在另一个实施例中，电路用于改变施加到泄放装置的驱动，其调节存储器阵列的数字线与其单元板之间的通信。缓慢的通信允许存储器阵列中的缺陷具有更显着的效果，因此增加了在测试期间发现这些缺陷的机会。电路被配置为通过接触焊盘或耦合到电路的一系列离散电压源来接受和施加多个电压。

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