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1. 发明申请

US20120001264A1 ETCHANTS AND METHODS OF FABRICATING SEMICONDUCTOR DEVICES USING THE SAME 审中-公开
标题翻译：使用该方法制备半导体器件的蚀刻和方法
公开(公告)号：US20120001264A1
公开(公告)日：2012-01-05
申请号：US13173360
申请日：2011-06-30
申请人： Hong-suk Kim , Jin-gyun Kim , Hun-Hyeong Lim , Ki-hyun Hwang , Jae-Young Ahn , Jun-kyu Yang
发明人： Hong-suk Kim , Jin-gyun Kim , Hun-Hyeong Lim , Ki-hyun Hwang , Jae-Young Ahn , Jun-kyu Yang
IPC分类号： H01L21/28 , C09K13/04 , H01L27/088
CPC分类号： C09K13/04 , H01L21/764 , H01L21/823437 , H01L27/11578 , H01L27/11582 , H01L29/7926
摘要： Provided according to embodiments of the present invention are methods of fabricating semiconductor devices using an etchant. In some embodiments, the etchant may be highly selective and may act to reduce interference between wordlines in the semiconductor device. In some embodiments of the invention, provided are methods of fabricating a semiconductor device that include forming a plurality of gate patterns on a substrate; forming first insulation layers between the gate patterns; wet-etching the first insulation layers to form first insulation layer residues; and forming air gaps between the plurality of gate patterns. Related etchant solutions and semiconductor devices are also provided.
摘要翻译：根据本发明的实施例提供的是使用蚀刻剂制造半导体器件的方法。在一些实施例中，蚀刻剂可以是高度选择性的并且可以用于减小半导体器件中的字线之间的干扰。在本发明的一些实施例中，提供了制造半导体器件的方法，该半导体器件包括在衬底上形成多个栅极图案; 在栅极图案之间形成第一绝缘层; 湿蚀刻第一绝缘层以形成第一绝缘层残留物; 以及在所述多个栅极图案之间形成气隙。还提供了相关蚀刻剂溶液和半导体器件。

2. 发明申请

US20150115348A1 VERTICAL-TYPE NONVOLATILE MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：垂直型非易失性存储器件及其制造方法
公开(公告)号：US20150115348A1
公开(公告)日：2015-04-30
申请号：US14525361
申请日：2014-10-28
申请人： Phil-ouk Nam , Jun-kyu Yang , Hun-hyeong Lim , Ki-hyun Hwang , Jae-young Ahn , Dong-chul Yoo
发明人： Phil-ouk Nam , Jun-kyu Yang , Hun-hyeong Lim , Ki-hyun Hwang , Jae-young Ahn , Dong-chul Yoo
IPC分类号： H01L27/115 , H01L21/3205 , H01L29/66 , H01L21/02 , H01L29/792
CPC分类号： H01L27/11582 , H01L27/11524 , H01L27/11575 , H01L29/66666 , H01L29/66833 , H01L29/7926
摘要： A vertical-type nonvolatile memory device includes a first vertical channel structure, and first and second stacked structure. The first vertical channel structure extends vertically on a substrate. The first stacked structure includes gate electrodes and first interlayer insulating layers. The gate layers and the first interlayer insulating layers are alternately and vertically stacked on each other. The first stacked structure is disposed on a first sidewall of the first vertical channel structure. The second stacked structure includes first sacrificial layers and second interlayer insulating layers. The first sacrificial layers and the second interlayer insulating layers are alternately and vertically stacked on each other. The second stacked structure is disposed on a second sidewall of the first vertical channel structure. The first sacrificial layers is formed of a polysilicon layer.
摘要翻译：垂直型非易失性存储器件包括第一垂直沟道结构以及第一和第二堆叠结构。第一垂直通道结构在衬底上垂直延伸。第一堆叠结构包括栅电极和第一层间绝缘层。栅极层和第一层间绝缘层彼此交替地和垂直地堆叠。第一堆叠结构设置在第一垂直通道结构的第一侧壁上。第二堆叠结构包括第一牺牲层和第二层间绝缘层。第一牺牲层和第二层间绝缘层彼此交替地和垂直地堆叠。第二堆叠结构设置在第一垂直通道结构的第二侧壁上。第一牺牲层由多晶硅层形成。

3. 发明授权

US08748249B2 Vertical structure non-volatile memory device and method of manufacturing the same 有权
标题翻译：垂直结构非易失性存储器件及其制造方法
公开(公告)号：US08748249B2
公开(公告)日：2014-06-10
申请号：US13456415
申请日：2012-04-26
申请人： Jun-kyu Yang , Ki-hyun Hwang , Phil-ouk Nam , Jae-young Ahn , Han-mei Choi , Dong-chul Yoo
发明人： Jun-kyu Yang , Ki-hyun Hwang , Phil-ouk Nam , Jae-young Ahn , Han-mei Choi , Dong-chul Yoo
IPC分类号： H01L21/8238
CPC分类号： H01L29/7926 , H01L27/11556 , H01L27/11582 , H01L29/7889
摘要： A vertical structure non-volatile memory device in which a gate dielectric layer is prevented from protruding toward a substrate; a resistance of a ground selection line (GSL) electrode is reduced so that the non-volatile memory device is highly integrated and has improved reliability, and a method of manufacturing the same are provided. The method includes: sequentially forming a polysilicon layer and an insulating layer on a silicon substrate; forming a gate dielectric layer and a channel layer through the polysilicon layer and the insulating layer, the gate dielectric layer and the channel layer extending in a direction perpendicular to the silicon substrate; forming an opening for exposing the silicon substrate, through the insulating layer and the polysilicon layer; removing the polysilicon layer exposed through the opening, by using a halogen-containing reaction gas at a predetermined temperature; and filling a metallic layer in the space formed by removing the polysilicon layer.
摘要翻译：一种垂直结构的非易失性存储器件，其中防止栅介质层向衬底突出; 降低了接地选择线（GSL）电极的电阻，使得非易失性存储器件高度集成并且具有改进的可靠性，并且提供了其制造方法。该方法包括：在硅衬底上依次形成多晶硅层和绝缘层; 通过所述多晶硅层和所述绝缘层形成栅介质层和沟道层，所述栅介质层和所述沟道层在垂直于所述硅衬底的方向上延伸; 形成用于使所述硅衬底暴露于所述绝缘层和所述多晶硅层的开口; 通过在预定温度下使用含卤素反应气体去除通过开口暴露的多晶硅层; 并在通过去除多晶硅层形成的空间中填充金属层。

4. 发明授权

US08617947B2 Method of manufacturing semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US08617947B2
公开(公告)日：2013-12-31
申请号：US13456392
申请日：2012-04-26
申请人： Jun-kyu Yang , Phil-ouk Nam , Ki-hyun Hwang , Jae-young Ahn , Han-mei Choi , Bi-o Kim
发明人： Jun-kyu Yang , Phil-ouk Nam , Ki-hyun Hwang , Jae-young Ahn , Han-mei Choi , Bi-o Kim
IPC分类号： H01L21/8238
CPC分类号： H01L29/7926 , H01L27/11582 , H01L29/66757 , H01L29/66765 , H01L29/66833
摘要： A method of manufacturing a semiconductor device includes forming a channel region, forming a buffer layer on the channel region, and heat-treating the channel region by using a gas containing halogen atoms.
摘要翻译：制造半导体器件的方法包括形成通道区域，在沟道区域上形成缓冲层，并且通过使用含有卤素原子的气体来热处理沟道区域。

5. 发明申请

US20110300686A1 Methods of Fabricating Non-Volatile Memory Devices 审中-公开
标题翻译：制造非易失性存储器件的方法
公开(公告)号：US20110300686A1
公开(公告)日：2011-12-08
申请号：US13155678
申请日：2011-06-08
申请人： Soo-doo Chae , Ki-hyun Hwang , Han-mei Choi , Jun-kyu Yang , Byong-ju Kim
发明人： Soo-doo Chae , Ki-hyun Hwang , Han-mei Choi , Jun-kyu Yang , Byong-ju Kim
IPC分类号： H01L21/02
CPC分类号： H01L27/101 , H01L27/0688 , H01L27/2409 , H01L27/249 , H01L45/1226 , H01L45/1633
摘要： Methods of forming non-volatile memory devices include forming a semiconductor layer having a first impurity region of first conductivity type extending adjacent a first side thereof and a second impurity region of second conductivity type extending adjacent a second side thereof, on a substrate. A first electrically conductive layer is also provided, which is electrically coupled to the first impurity region. The semiconductor layer is converted into a plurality of semiconductor diodes having respective first terminals electrically coupled to the first electrically conductive layer. The first electrically conductive layer operates as a word line or bit line of the non-volatile memory device. The converting may include patterning the first impurity region into a plurality of cathodes or anodes of the plurality of semiconductor diodes (e.g., P-i-N diodes).
摘要翻译：形成非易失性存储器件的方法包括在衬底上形成半导体层，该半导体层具有在其第一侧附近延伸的第一导电类型的第一杂质区和邻近其第二侧延伸的第二导电类型的第二杂质区。还提供了第一导电层，其电耦合到第一杂质区。半导体层被转换成具有电耦合到第一导电层的相应的第一端子的多个半导体二极管。第一导电层用作非易失性存储器件的字线或位线。转换可以包括将第一杂质区域图案化成多个半导体二极管（例如，P-i-N二极管）的多个阴极或阳极。

6. 发明申请

US20080246078A1 Charge trap flash memory device and memory card and system including the same 有权
标题翻译：充电陷阱闪存设备和存储卡及系统包括相同
公开(公告)号：US20080246078A1
公开(公告)日：2008-10-09
申请号：US12080315
申请日：2008-04-02
申请人： Zong-liang Huo , In-seok Yeo , Seung-Hyun Lim , Kyong-hee Joo , Jun-kyu Yang
发明人： Zong-liang Huo , In-seok Yeo , Seung-Hyun Lim , Kyong-hee Joo , Jun-kyu Yang
IPC分类号： H01L29/792
CPC分类号： H01L21/28273 , B82Y10/00 , H01L29/42332 , H01L29/7881
摘要： A charge trap flash memory device and method of making same are provided. The device includes: a tunnel insulating layer, a charge trap layer; a blocking insulating layer; and a gate electrode sequentially formed on a substrate. The charge trap layer includes: plural trap layers comprising a first material having a first band gap energy level; spaced apart nanodots, each nanodot being at least partially surrounded by at least one of the trap layers, wherein the nanodots comprise a second material having a second band gap energy level that is lower than the first band gap energy level; and an intermediate blocking layer comprising a third material having a third band gap energy level that is higher than the first band gap energy level, formed between at least two of the trap layers. This structure prevents loss of charges from the charge trap layer and improves charge storage capacity.
摘要翻译：提供了一种电荷阱闪存器件及其制造方法。该器件包括：隧道绝缘层，电荷陷阱层; 阻挡绝缘层; 以及依次形成在基板上的栅电极。电荷陷阱层包括：多个陷阱层，包括具有第一带隙能级的第一材料; 间隔开的纳米点，每个纳米点至少部分地被至少一个捕获层包围，其中该纳米点包括具有低于第一带隙能级的第二带隙能级的第二材料; 以及中间阻挡层，其包括形成在至少两个捕获层之间的具有高于第一带隙能级的第三带隙能级的第三材料。这种结构防止电荷陷阱层的电荷损失并且改善电荷存储容量。

7. 发明授权

US08269268B2 Charge trap flash memory device and memory card and system including the same 有权
标题翻译：充电陷阱闪存设备和存储卡及系统包括相同
公开(公告)号：US08269268B2
公开(公告)日：2012-09-18
申请号：US12080315
申请日：2008-04-02
申请人： Zong-liang Huo , In-seok Yeo , Seung-Hyun Lim , Kyong-hee Joo , Jun-kyu Yang
发明人： Zong-liang Huo , In-seok Yeo , Seung-Hyun Lim , Kyong-hee Joo , Jun-kyu Yang
IPC分类号： H01L29/792
CPC分类号： H01L21/28273 , B82Y10/00 , H01L29/42332 , H01L29/7881
摘要： The device includes: a tunnel insulating layer, a charge trap layer; a blocking insulating layer; and a gate electrode sequentially formed on a substrate. The charge trap layer includes: plural trap layers comprising a first material having a first band gap energy level; spaced apart nanodots, each nanodot being at least partially surrounded by at least one of the trap layers, wherein the nanodots comprise a second material having a second band gap energy level that is lower than the first band gap energy level; and an intermediate blocking layer comprising a third material having a third band gap energy level that is higher than the first band gap energy level, formed between at least two of the trap layers. This structure prevents loss of charges from the charge trap layer and improves charge storage capacity.
摘要翻译：该器件包括：隧道绝缘层，电荷陷阱层; 阻挡绝缘层; 以及依次形成在基板上的栅电极。电荷陷阱层包括：多个陷阱层，包括具有第一带隙能级的第一材料; 间隔开的纳米点，每个纳米点至少部分地被至少一个捕获层包围，其中该纳米点包括具有低于第一带隙能级的第二带隙能级的第二材料; 以及中间阻挡层，其包括形成在至少两个所述捕获层之间的具有高于所述第一带隙能级的第三带隙能级的第三材料。这种结构防止电荷陷阱层的电荷损失并且改善电荷存储容量。

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