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1. 发明授权

US07730285B1 Data processing system with partial bypass reorder buffer and combined load/store arithmetic logic unit and processing method thereof 有权
标题翻译：具有部分旁路重排序缓冲器和组合加载/存储算术逻辑单元的数据处理系统及其处理方法
公开(公告)号：US07730285B1
公开(公告)日：2010-06-01
申请号：US11497805
申请日：2006-08-02
申请人： Hong-Yi Chen , Richard Lee , Geoffrey K. Yung , Jensen Tjeng
发明人： Hong-Yi Chen , Richard Lee , Geoffrey K. Yung , Jensen Tjeng
IPC分类号： G06F9/312
CPC分类号： G06F9/3838 , G06F9/3828 , G06F9/3855 , G06F9/3857
摘要： A data processing system includes a plurality of functional units that selectively execute instructions. A register file includes a plurality of registers that store data corresponding to the instructions. A reorder buffer communicates with the register file and stores the data, includes at least one bypassable buffer location, and includes at least one non-bypassable buffer location.
摘要翻译：数据处理系统包括有选择地执行指令的多个功能单元。寄存器文件包括存储对应于指令的数据的多个寄存器。重排序缓冲器与寄存器文件通信并存储数据，包括至少一个可旁路缓冲器位置，并且包括至少一个不可旁路缓冲器位置。

2. 发明授权

US07685372B1 Transparent level 2 cache controller 失效
标题翻译：透明级2缓存控制器
公开(公告)号：US07685372B1
公开(公告)日：2010-03-23
申请号：US11034677
申请日：2005-01-13
申请人： Hong-Yi Chen , Geoffrey K. Yung
发明人： Hong-Yi Chen , Geoffrey K. Yung
IPC分类号： G06F12/00
CPC分类号： G06F12/1063 , G06F12/0811 , G06F12/0837
摘要： A digital system that connects to a bus that employs physical addresses comprises a processing core. A level one (L1) cache communicates with the processing core. A level two (L2) cache communicates with the L1 cache. Both the L1 cache and the L2 cache are indexed by virtual addresses and tagged with virtual addresses. A bus unit communicates with the L2 cache and with the bus.
摘要翻译：连接到采用物理地址的总线的数字系统包括一个处理核心。一级（L1）缓存与处理核心通信。二级（L2）缓存与L1高速缓存通信。 L1高速缓存和L2高速缓存由虚拟地址索引并用虚拟地址标记。总线单元与二级缓存和总线进行通信。

3. 发明授权

US08347034B1 Transparent level 2 cache that uses independent tag and valid random access memory arrays for cache access 有权
标题翻译：透明的2级缓存，使用独立的标签和有效的随机存取存储器阵列进行缓存访问
公开(公告)号：US08347034B1
公开(公告)日：2013-01-01
申请号：US11034846
申请日：2005-01-13
申请人： Hong-Yi Chen , Geoffrey K. Yung
发明人： Hong-Yi Chen , Geoffrey K. Yung
IPC分类号： G06F12/00 , G06F13/00
CPC分类号： G06F12/0891 , G06F12/0804 , G06F12/0837
摘要： A computer cache for a memory comprises a data random-access memory (RAM) containing a plurality of cache lines. Each of the cache lines stores a segment of the memory. A tag RAM contains a plurality of address tags that correspond to the cache lines. A valid RAM contains a plurality of validity values that correspond to the cache lines. The valid RAM is stored separately from the tag RAM and the data RAM. The valid RAM is selectively independently clearable. A hit module determines whether data is stored in the computer cache based upon the valid RAM and the tag RAM.
摘要翻译：用于存储器的计算机缓存器包括包含多个高速缓存线的数据随机存取存储器（RAM）。每个高速缓存线存储存储器的一段。标签RAM包含与高速缓存行对应的多个地址标签。有效RAM包含与高速缓存行对应的多个有效值。有效的RAM与标签RAM和数据RAM分开存储。有效的RAM可以选择性地独立清除。命中模块基于有效的RAM和标签RAM来确定数据是否存储在计算机高速缓存中。

4. 发明授权

US07949833B1 Transparent level 2 cache controller 有权
标题翻译：透明级2缓存控制器
公开(公告)号：US07949833B1
公开(公告)日：2011-05-24
申请号：US12728583
申请日：2010-03-22
申请人： Hong-Yi Chen , Geoffrey K. Yung
发明人： Hong-Yi Chen , Geoffrey K. Yung
IPC分类号： G06F12/00
CPC分类号： G06F12/1063 , G06F12/0811 , G06F12/0837
摘要： A digital system that connects to a bus that employs physical addresses comprises a processing core. A level one (L1) cache communicates with the processing core. A level two (L2) cache communicates with the L1 cache. Both the L1 cache and the L2 cache are indexed by virtual addresses and tagged with virtual addresses. A bus unit communicates with the L2 cache and with the bus.
摘要翻译：连接到采用物理地址的总线的数字系统包括一个处理核心。一级（L1）缓存与处理核心通信。二级（L2）缓存与L1高速缓存通信。 L1高速缓存和L2高速缓存由虚拟地址索引并用虚拟地址标记。总线单元与二级缓存和总线进行通信。

5. 发明授权

US08909903B1 Providing data to registers between execution stages 有权
标题翻译：在执行阶段之间向寄存器提供数据
公开(公告)号：US08909903B1
公开(公告)日：2014-12-09
申请号：US13311184
申请日：2011-12-05
申请人： Hong-Yi Chen , Jensen Tjeng
发明人： Hong-Yi Chen , Jensen Tjeng
IPC分类号： G06F9/30
CPC分类号： G06F9/3822 , G06F9/3873 , G06F9/3877
摘要： In some implementations, a processor is provided having a buffer to store one or more instructions, a decoder configured to decode the one or more instructions and generate one or more decoded instructions, a processor register file to store one or more operands, and a plurality of execution units. Each execution unit includes a plurality of execution stages and a plurality of registers. The plurality of execution stages is configured to execute one or more decoded instructions using the one or more operands. The plurality of registers is positioned between the plurality of execution stages to latch data between the plurality of execution stages.
摘要翻译：在一些实施方式中，提供具有存储一个或多个指令的缓冲器的处理器，被配置为对一个或多个指令进行解码并生成一个或多个解码指令的解码器，用于存储一个或多个操作数的处理器寄存器文件和多个的执行单位。每个执行单元包括多个执行级和多个寄存器。多个执行级被配置为使用一个或多个操作数来执行一个或多个解码指令。多个寄存器位于多个执行级之间，以在多个执行级之间锁存数据。

6. 发明授权

US08392799B1 Systems and methods for arbitrating use of processor memory 有权
标题翻译：用于仲裁处理器内存使用的系统和方法
公开(公告)号：US08392799B1
公开(公告)日：2013-03-05
申请号：US13465964
申请日：2012-05-07
申请人： Pantas Sutardja , Hong-Yi Chen
发明人： Pantas Sutardja , Hong-Yi Chen
IPC分类号： G11C29/00
CPC分类号： G11C29/00 , G11B20/18 , G11B2220/657 , G11C2029/0411
摘要： A system including a processor, a first-in first-out (FIFO) module, and an arbiter module. The processor includes i) a processor core and ii) a memory. The FIFO module is configured to receive streaming data, output the streaming data to the memory of the processor, and selectively generate a control signal. The arbiter module is configured to adjust, based on the control signal, a priority in which at least one of the processor core and the FIFO module accesses the memory of the processor.
摘要翻译：一种包括处理器，先进先出（FIFO）模块和仲裁器模块的系统。该处理器包括i）处理器核心和ii）存储器。 FIFO模块被配置为接收流数据，将流数据输出到处理器的存储器，并且选择性地生成控制信号。仲裁器模块被配置为基于控制信号来调整处理器核心和FIFO模块中的至少一个访问处理器的存储器的优先级。

7. 发明授权

US07827423B2 Low power computer with main and auxiliary processors 有权
标题翻译：低功耗电脑配有主处理器和辅助处理器
公开(公告)号：US07827423B2
公开(公告)日：2010-11-02
申请号：US12151526
申请日：2008-05-07
申请人： Sehat Sutardja , Hong-Yi Chen
发明人： Sehat Sutardja , Hong-Yi Chen
IPC分类号： G06F1/32
CPC分类号： G06F1/3293 , G06F1/3203 , G06F1/324 , G06F1/3275 , G06F12/08 , G06F12/0866 , G06F12/0897 , G06F13/28 , G06F2212/222 , Y02D10/122 , Y02D10/126 , Y02D10/13 , Y02D10/14 , Y02D50/20
摘要： A processing device comprises a processor, low power nonvolatile memory that communicates with the processor, high power nonvolatile memory that communicates with the processor. The processing device manages data using a cache hierarchy comprising a high power (HP) nonvolatile memory level for data in the high power nonvolatile memory and a low power (LP) nonvolatile memory level for data in the low power nonvolatile memory. The LP nonvolatile memory level has a higher level in the cache hierarchy than the HP nonvolatile memory level.
摘要翻译：处理装置包括处理器，与处理器通信的低功率非易失性存储器，与处理器通信的高功率非易失性存储器。处理装置使用包括用于高功率非易失性存储器中的数据的高功率（HP）非易失性存储器级别和用于低功率非易失性存储器中的数据的低功率（LP）非易失性存储器级别）的高速缓存层级来管理数据。 LP非易失性存储器级别在高速缓存层级中具有比HP非易失性存储器级别更高的级别。

8. 发明申请

US20080189518A1 PROCESSOR INSTRUCTION CACHE WITH DUAL-READ MODES 有权
标题翻译：具有双读模式的处理器指令高速缓存
公开(公告)号：US20080189518A1
公开(公告)日：2008-08-07
申请号：US12061296
申请日：2008-04-02
申请人： Sehat Sutardja , Jason T. Su , Hong-Yi Chen , Jason Sheu , Jensen Tjeng
发明人： Sehat Sutardja , Jason T. Su , Hong-Yi Chen , Jason Sheu , Jensen Tjeng
IPC分类号： G06F9/312
CPC分类号： G06F12/0882 , G06F9/30054 , G06F9/30058 , G06F9/3804 , G06F9/3844 , G11C7/06 , G11C7/1018 , G11C7/1051 , G11C7/106 , G11C7/1078 , G11C7/1087 , G11C7/12 , G11C7/22 , G11C2207/2245 , G11C2207/2281 , Y02D10/13
摘要： A processor includes a cache memory that has an array, word lines, and bit lines. A control module accesses cells of the array during access cycles to access instructions stored in the cache memory. The control module performs one of a first discrete read and a first sequential read to access instructions in a first set of cells of the array that are connected to a first word line and selectively performs one of a second discrete read and a second sequential read based on a branch instruction to access instructions in a second set of cells of the array that are connected to a second word line. The second word line is different than the first word line.
摘要翻译：处理器包括具有阵列，字线和位线的高速缓冲存储器。控制模块在访问周期期间访问阵列的单元以访问存储在高速缓冲存储器中的指令。控制模块执行第一离散读取和第一顺序读取之一以访问连接到第一字线的阵列的第一组单元中的指令，并且选择性地执行第二离散读取和第二顺序读取之一在分支指令上访问连接到第二字线的阵列的第二组单元格中的指令。第二个字线与第一个字线不同。

9. 发明申请

US20060212687A1 Dual thread processor 有权
标题翻译：双线程处理器
公开(公告)号：US20060212687A1
公开(公告)日：2006-09-21
申请号：US11084364
申请日：2005-03-18
申请人： Hong-Yi Chen , Sehat Sutardja
发明人： Hong-Yi Chen , Sehat Sutardja
IPC分类号： G06F9/44
CPC分类号： G06F9/3851 , G06F9/3012 , G06F9/30123 , G06F9/3861 , G06F9/3867
摘要： A pipeline processor architecture, processor, and methods are provided. In one implementation, a processor is provided that includes an instruction fetch unit operable to fetch instructions associated with a plurality of processor threads, a decoder responsive to the instruction fetch unit, issue logic responsive to the decoder, and a register file including a plurality of banks corresponding to the plurality of processor threads. Each bank is operable to store data associated with a corresponding processor thread. The processor can include a set of registers corresponding to each of a plurality of processor threads. Each register within a set is located either before or after a pipeline stage of the processor.
摘要翻译：提供了流水线处理器架构，处理器和方法。在一个实现中，提供了一种处理器，其包括指令获取单元，其可操作以获取与多个处理器线程相关联的指令，响应于指令提取单元的解码器，响应于解码器的发布逻辑，以及包括多个对应于多个处理器线程的存储体。每个存储体可操作地存储与相应处理器线程相关联的数据。处理器可以包括与多个处理器线程中的每一个对应的一组寄存器。一组中的每个寄存器位于处理器的流水线阶段之前或之后。

10. 发明授权

US5864372A Apparatus for implementing a block matching algorithm for motion estimation in video image processing 失效
标题翻译：用于在视频图像处理中实现用于运动估计的块匹配算法的装置
公开(公告)号：US5864372A
公开(公告)日：1999-01-26
申请号：US763089
申请日：1996-12-10
申请人： Hong-Yi Chen , Qing-Ming Shu
发明人： Hong-Yi Chen , Qing-Ming Shu
IPC分类号： H04N7/26 , H04N7/32
CPC分类号： H04N19/51
摘要： An apparatus for implementing block matching for motion estimation in video image processing. The apparatus receives the pixel data of an original image block and the pixel data of a compared image block selected from a number of compared image blocks during video image processing. The selected image blocks are compared to determine a movement vector. The apparatus has a multi-stage pipelined tree-architecture that includes four stages. The first computational stage produces corresponding pairs of difference data and sign data. A second compression stage in the process pipeline includes a compression array that receives all the difference data and sign data, which are added together to produce compressed summation data and compressed sign data. The third summation stage in the pipeline receives the compressed summation and sign data and produces a mean absolute error for the original and compared image block pixels. A last minimization stage receives the mean absolute error for each of the compared image blocks and determines a minimum mean absolute error from among them. The compression array includes of a number of full and half adders arranged in a multi-level configuration in which none of the adder operand inputs and the carry-in inputs is left un-connected.
摘要翻译：一种用于在视频图像处理中实现运动估计的块匹配的装置。在视频图像处理期间，该装置接收原始图像块的像素数据和从多个比较的图像块中选择的比较图像块的像素数据。比较所选择的图像块以确定运动矢量。该装置具有包括四个阶段的多级流水线树结构。第一个计算阶段产生相应的差分数据和符号数据对。处理流程中的第二压缩级包括接收所有差分数据和符号数据的压缩阵列，它们相加在一起以产生压缩求和数据和压缩符号数据。流水线中的第三求和级接收压缩求和和符号数据，并产生原始和比较的图像块像素的平均绝对误差。最后一个最小化阶段接收每个比较图像块的平均绝对误差，并确定其中的最小平均绝对误差。压缩阵列包括以多电平配置布置的多个全加和半加法器，其中加法器操作数输入和进位输入都不被保持不连接。

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