专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07550390B2 Method and apparatus for dielectric etching during integrated circuit fabrication 有权
标题翻译：在集成电路制造期间的电介质蚀刻的方法和装置
公开(公告)号：US07550390B2
公开(公告)日：2009-06-23
申请号：US11326031
申请日：2006-01-04
申请人： Hong-Ji Lee , Chun-Hung Lee , Nan-Tsu Lian
发明人： Hong-Ji Lee , Chun-Hung Lee , Nan-Tsu Lian
IPC分类号： H01L21/461
CPC分类号： H01L21/76802 , H01L21/31116 , H01L21/76807 , H01L21/76814 , H01L22/26
摘要： A method for multi-step dielectric etching includes discharge steps between each of the etching steps in order to help release accumulated charge on the wafer produced by the previous etching step. The discharge steps stabilize the plasma discharge in each transition between etching steps. Charge elimination occurs because the negative species is relatively higher at the beginning of plasma spiking and can reach the wafer surface to reduce the accumulated charge.
摘要翻译：一种用于多步电介质蚀刻的方法包括在每个蚀刻步骤之间的放电步骤，以便有助于释放由前一蚀刻步骤产生的晶片上的累积电荷。放电步骤在蚀刻步骤之间的每个转变中稳定等离子体放电。发生电荷消除是因为负极物质在等离子体尖峰开始时相对较高，并且可以到达晶片表面以减少累积电荷。

2. 发明申请

US20070167002A1 Method and apparatus for dielectric etching during integrated circuit fabrication 有权
标题翻译：在集成电路制造期间的电介质蚀刻的方法和装置
公开(公告)号：US20070167002A1
公开(公告)日：2007-07-19
申请号：US11326031
申请日：2006-01-04
申请人： Hong-Ji Lee , Chun-Hung Lee , Nan-Tsu Lian
发明人： Hong-Ji Lee , Chun-Hung Lee , Nan-Tsu Lian
IPC分类号： H01L21/4763
CPC分类号： H01L21/76802 , H01L21/31116 , H01L21/76807 , H01L21/76814 , H01L22/26
摘要： A method for multi-step dielectric etching includes discharge steps between each of the etching steps in order to help release accumulated charge on the wafer produced by the previous etching step. The discharge steps stabilize the plasma discharge in each transition between etching steps. Charge elimination occurs because the negative species is relatively higher at the beginning of plasma spiking and can reach the wafer surface to reduce the accumulated charge.
摘要翻译：一种用于多步电介质蚀刻的方法包括在每个蚀刻步骤之间的放电步骤，以便有助于释放由前一蚀刻步骤产生的晶片上的累积电荷。放电步骤在蚀刻步骤之间的每个转变中稳定等离子体放电。发生电荷消除是因为负极物质在等离子体尖峰开始时相对较高，并且可以到达晶片表面以减少累积电荷。

3. 发明申请

US20110104881A1 METHOD OF REDUCING WORDLINE SHORTING 有权
标题翻译：减少WORDLINE SHORTING的方法
公开(公告)号：US20110104881A1
公开(公告)日：2011-05-05
申请号：US12611614
申请日：2009-11-03
申请人： Hong-Ji Lee , Nan-Tsu Lian , Kuang-Chao Chen
发明人： Hong-Ji Lee , Nan-Tsu Lian , Kuang-Chao Chen
IPC分类号： H01L21/28
CPC分类号： H01L21/28247 , H01L21/28282 , H01L27/11568
摘要： A method of fabricating a memory device includes providing a substrate having an insulating layer, forming first, second, and third conductive layers on the insulating layer, forming a mask on the third conductive layer, etching through the third conductive layer and a first portion thickness of the second conductive layer using the mask to provide an etched sidewall portions of the third conductive layer and an etched upper surface of the second polysilicon layer, and forming a liner layer along the etched sidewall portions and the etched upper surface.
摘要翻译：一种制造存储器件的方法包括提供具有绝缘层的衬底，在绝缘层上形成第一，第二和第三导电层，在第三导电层上形成掩模，蚀刻通过第三导电层和第一部分厚度使用所述掩模提供所述第三导电层的蚀刻侧壁部分和所述第二多晶硅层的蚀刻的上表面，以及沿着蚀刻的侧壁部分和所蚀刻的上表面形成衬垫层。

4. 发明授权

US08445346B2 Method of reducing wordline shorting 有权
标题翻译：减少字线短路的方法
公开(公告)号：US08445346B2
公开(公告)日：2013-05-21
申请号：US12611614
申请日：2009-11-03
申请人： Hong-Ji Lee , Nan-Tsu Lian , Kuang-Chao Chen
发明人： Hong-Ji Lee , Nan-Tsu Lian , Kuang-Chao Chen
IPC分类号： H01L21/8247
CPC分类号： H01L21/28247 , H01L21/28282 , H01L27/11568
摘要： A method of fabricating a memory device includes providing a substrate having an insulating layer, forming first, second, and third conductive layers on the insulating layer, forming a mask on the third conductive layer, etching through the third conductive layer and a first portion thickness of the second conductive layer using the mask to provide an etched sidewall portions of the third conductive layer and an etched upper surface of the second polysilicon layer, and forming a liner layer along the etched sidewall portions and the etched upper surface.
摘要翻译：一种制造存储器件的方法包括提供具有绝缘层的衬底，在绝缘层上形成第一，第二和第三导电层，在第三导电层上形成掩模，蚀刻通过第三导电层和第一部分厚度使用所述掩模提供所述第三导电层的蚀刻侧壁部分和所述第二多晶硅层的蚀刻的上表面，以及沿着蚀刻的侧壁部分和所蚀刻的上表面形成衬垫层。

5. 发明申请

US20070264773A1 METHODS OF ETCHING STACKS HAVING METAL LAYERS AND HARD MASK LAYERS 有权
标题翻译：蚀刻具有金属层和硬掩模层的堆叠的方法
公开(公告)号：US20070264773A1
公开(公告)日：2007-11-15
申请号：US11382401
申请日：2006-05-09
申请人： Hong-Ji Lee , Chun-Hung Lee
发明人： Hong-Ji Lee , Chun-Hung Lee
IPC分类号： H01L21/336 , H01L21/302 , H01L21/461
CPC分类号： H01L21/32139 , H01L21/31116 , H01L21/32136
摘要： Methods which comprise: providing a stack to be etched, the stack comprising a metal interconnect layer disposed above a substrate, a barrier layer disposed above the metal interconnect layer, a hard mask layer disposed on the barrier layer, and a patterning layer disposed above the hard mask layer wherein the patterning layer defines a pattern above the hard mask layer; and etching the pattern through the hard mask layer and at least a portion of the barrier layer, wherein the etching through an interface between the hard mask layer and the barrier layer is carried out using a fluorine-containing etch recipe.
摘要翻译：包括：提供待蚀刻的堆叠的堆叠，所述堆叠包括设置在衬底上方的金属互连层，设置在所述金属互连层上方的势垒层，设置在所述阻挡层上的硬掩模层以及设置在所述阻挡层上方的图案形成层硬掩模层，其中图案化层限定硬掩模层上方的图案; 并且通过硬掩模层和阻挡层的至少一部分蚀刻图案，其中通过含氟蚀刻配方进行通过硬掩模层和阻挡层之间的界面的蚀刻。

6. 发明授权

US07435681B2 Methods of etching stacks having metal layers and hard mask layers 有权
标题翻译：蚀刻具有金属层和硬掩模层的堆叠的方法
公开(公告)号：US07435681B2
公开(公告)日：2008-10-14
申请号：US11382401
申请日：2006-05-09
申请人： Hong-Ji Lee , Chun-Hung Lee
发明人： Hong-Ji Lee , Chun-Hung Lee
IPC分类号： H01L21/461 , H01L21/302 , H01L21/44
CPC分类号： H01L21/32139 , H01L21/31116 , H01L21/32136
摘要： Methods which comprise: providing a stack to be etched, the stack comprising a metal interconnect layer disposed above a substrate, a barrier layer disposed above the metal interconnect layer, a hard mask layer disposed on the barrier layer, and a patterning layer disposed above the hard mask layer wherein the patterning layer defines a pattern above the hard mask layer; and etching the pattern through the hard mask layer and at least a portion of the barrier layer, wherein the etching through an interface between the hard mask layer and the barrier layer is carried out using a fluorine-containing etch recipe.
摘要翻译：包括：提供待蚀刻的堆叠的堆叠，所述堆叠包括设置在衬底上方的金属互连层，设置在所述金属互连层上方的势垒层，设置在所述阻挡层上的硬掩模层以及设置在所述阻挡层上方的图案形成层硬掩模层，其中图案化层限定硬掩模层上方的图案; 并且通过硬掩模层和阻挡层的至少一部分蚀刻图案，其中通过含氟蚀刻配方进行通过硬掩模层和阻挡层之间的界面的蚀刻。

7. 发明授权

US07410593B2 Plasma etching methods using nitrogen memory species for sustaining glow discharge 有权
标题翻译：使用氮记忆物质的等离子体蚀刻方法来维持辉光放电
公开(公告)号：US07410593B2
公开(公告)日：2008-08-12
申请号：US11359787
申请日：2006-02-22
申请人： Hong-Ji Lee , Shih-Ping Hong , An-Chyi Wei
发明人： Hong-Ji Lee , Shih-Ping Hong , An-Chyi Wei
IPC分类号： B44C1/22 , H01L21/302
CPC分类号： H01L21/3065
摘要： Methods are described which comprise: providing a plasma etching apparatus having an etching chamber; disposing a substrate to be etched in the chamber; introducing N2 gas and one or more process gases into the chamber; and etching the substrate, wherein the introduction of the N2 gas is stopped prior to etching, and wherein etching comprises an initial plasma ignition wherein at least a portion of the N2 gas remains present in the chamber during initial plasma ignition. Additional methods are described which comprise: providing a plasma etching apparatus having an etching chamber; disposing a substrate to be etched in the chamber; introducing N2 gas and one or more process gases into the chamber; applying power to an electrode in the chamber such that an N2 memory species is formed; and etching the substrate, where the introduction of the N2 gas into the chamber can be stopped prior to etching. Other methods are also described which comprise: providing a plasma etching apparatus having an etching chamber; disposing a substrate to be etched in the chamber; introducing N2 gas into the chamber; applying power to an electrode in the chamber such that an N2 memory species is formed; removing the applied power from the electrode in the chamber; stopping the introduction of the N2 gas into the chamber and introducing one or more process gases into the chamber; and etching the substrate.
摘要翻译：描述了包括：提供具有蚀刻室的等离子体蚀刻装置的方法; 将待蚀刻的基板设置在所述室中; 将N 2 O 2气体和一种或多种工艺气体引入所述室中; 以及蚀刻所述衬底，其中在蚀刻之前停止引入N 2 O 2气体，并且其中蚀刻包括初始等离子体点火，其中N 2 N 2 N 2的至少一部分初始等离子体点火期间气体保留在腔室中。描述了附加方法，其包括：提供具有蚀刻室的等离子体蚀刻装置; 将待蚀刻的基板设置在所述室中; 将N 2 O 2气体和一种或多种工艺气体引入所述室中; 向腔室中的电极施加功率，使得形成N 2种记忆物质; 并且在蚀刻之前可以停止引入N 2气体到腔室中的衬底。还描述了其它方法，其包括：提供具有蚀刻室的等离子体蚀刻装置; 将待蚀刻的基板设置在所述室中; 将N 2 O 2气体引入室中; 向腔室中的电极施加功率，使得形成N 2种记忆物质; 从室中的电极去除施加的功率; 停止将N 2 N 2气体引入室中并将一种或多种工艺气体引入室中; 并蚀刻衬底。

8. 发明申请

US20070193977A1 Plasma etching methods using nitrogen memory species for sustaining glow discharge 有权
标题翻译：使用氮记忆物质的等离子体蚀刻方法来维持辉光放电
公开(公告)号：US20070193977A1
公开(公告)日：2007-08-23
申请号：US11359787
申请日：2006-02-22
申请人： Hong-Ji Lee , Shih-Ping Hong , An-Chyi Wei
发明人： Hong-Ji Lee , Shih-Ping Hong , An-Chyi Wei
IPC分类号： C23F1/00 , C03C25/68 , H01L21/302
CPC分类号： H01L21/3065
摘要： Methods are described which comprise: providing a plasma etching apparatus having an etching chamber; disposing a substrate to be etched in the chamber; introducing N2 gas and one or more process gases into the chamber; and etching the substrate, wherein the introduction of the N2 gas is stopped prior to etching, and wherein etching comprises an initial plasma ignition wherein at least a portion of the N2 gas remains present in the chamber during initial plasma ignition. Additional methods are described which comprise: providing a plasma etching apparatus having an etching chamber; disposing a substrate to be etched in the chamber; introducing N2 gas and one or more process gases into the chamber; applying power to an electrode in the chamber such that an N2 memory species is formed; and etching the substrate, where the introduction of the N2 gas into the chamber can be stopped prior to etching. Other methods are also described which comprise: providing a plasma etching apparatus having an etching chamber; disposing a substrate to be etched in the chamber; introducing N2 gas into the chamber; applying power to an electrode in the chamber such that an N2 memory species is formed; removing the applied power from the electrode in the chamber; stopping the introduction of the N2 gas into the chamber and introducing one or more process gases into the chamber; and etching the substrate.
摘要翻译：描述了包括：提供具有蚀刻室的等离子体蚀刻装置的方法; 将待蚀刻的基板设置在所述室中; 将N 2 O 2气体和一种或多种工艺气体引入所述室中; 以及蚀刻所述衬底，其中在蚀刻之前停止引入N 2 O 2气体，并且其中蚀刻包括初始等离子体点火，其中N 2 N 2 N 2的至少一部分初始等离子体点火期间气体保留在腔室中。描述了附加方法，其包括：提供具有蚀刻室的等离子体蚀刻装置; 将待蚀刻的基板设置在所述室中; 将N 2 O 2气体和一种或多种工艺气体引入所述室中; 向腔室中的电极施加功率，使得形成N 2种记忆物质; 并且在蚀刻之前可以停止引入N 2气体到腔室中的衬底。还描述了其它方法，其包括：提供具有蚀刻室的等离子体蚀刻装置; 将待蚀刻的基板设置在所述室中; 将N 2 N 2气体引入所述室中; 向腔室中的电极施加功率，使得形成N 2种记忆物质; 从室中的电极去除施加的功率; 停止将N 2 N 2气体引入室中并将一种或多种工艺气体引入室中; 并蚀刻衬底。

9. 发明申请

US20110074030A1 METHOD FOR PREVENTING Al-Cu BOTTOM DAMAGE USING TiN LINER 有权
标题翻译：使用TiN衬垫防止Al-Cu底部损伤的方法
公开(公告)号：US20110074030A1
公开(公告)日：2011-03-31
申请号：US12570941
申请日：2009-09-30
申请人： Kuo Liang Wei , Hsu Sheng Yu , Hong-Ji Lee
发明人： Kuo Liang Wei , Hsu Sheng Yu , Hong-Ji Lee
IPC分类号： H01L23/48 , H01L21/768
CPC分类号： H01L23/53223 , H01L21/32136 , H01L21/32139 , H01L21/76852 , H01L2924/0002 , H01L2924/12044 , H01L2924/00
摘要： A semiconductor device and related method for fabricating the same include providing a stacked structure including an insulating base layer and lower and upper barrier layers with a conductive layer in between, etching the stacked structure to provide a plurality of conductive columns that each extend from the lower barrier layer, each of the conductive columns having an overlying upper barrier layer cap formed from the etched upper barrier layer, wherein the lower barrier layer is partially etched to provide a land region between each of the conductive lines, forming a liner layer over the etched stacked structure exposing the land region, and etching the liner layer and removing the exposed land region to form a plurality of conductive lines
摘要翻译：半导体器件及其制造方法包括提供包括绝缘基底层和下部和上部阻挡层之间的导电层的堆叠结构，蚀刻层叠结构以提供多个导电柱，每个导电柱从下部延伸阻挡层，每个导电柱具有由蚀刻的上阻挡层形成的覆盖的上阻挡层帽，其中下阻挡层被部分地蚀刻以在每个导电线之间提供焊盘区域，在蚀刻层叠结构，暴露所述焊盘区域，以及蚀刻所述衬垫层并去除所述暴露的焊盘区域以形成多条导电线

10. 发明申请

US20100167021A1 SEMICONDUCTOR STRUCTURE AND METHOD OF FABRICATING THE SAME 有权
标题翻译：半导体结构及其制造方法
公开(公告)号：US20100167021A1
公开(公告)日：2010-07-01
申请号：US12345305
申请日：2008-12-29
申请人： Hong-Ji Lee , Shih-Ping Hong , Fang-Hao Hsu
发明人： Hong-Ji Lee , Shih-Ping Hong , Fang-Hao Hsu
IPC分类号： B32B3/10 , G03F7/20
CPC分类号： H01L21/31116 , H01L21/0332 , H01L21/31122 , H01L21/32136 , H01L21/32137 , H01L21/32139
摘要： A method of forming a semiconductor structure is provided. First, a target layer and a mask layer are sequentially formed on a substrate. Thereafter, a first pattern transfer layer having a plurality of openings is formed on the mask layer. Afterwards, a second pattern transfer layer is formed in the openings of the first pattern transfer layer. The mask layer is then patterned, using the first pattern transfer layer and the second pattern transfer layer as a mask, so as to form a patterned mask layer. Further, the target layer is patterned using the patterned mask layer.
摘要翻译：提供一种形成半导体结构的方法。首先，在基板上依次形成目标层和掩模层。此后，在掩模层上形成具有多个开口的第一图案转印层。之后，在第一图案转印层的开口中形成第二图案转印层。然后使用第一图案转印层和第二图案转印层作为掩模将掩模层图案化，以形成图案化掩模层。此外，使用图案化掩模层对目标层进行图案化。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式