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1. 发明申请

US20130320463A1 PACKAGE STRUCTURE HAVING MEMS ELEMENT AND FABRICATION METHOD THEREOF 审中-公开
标题翻译：具有MEMS元件的包装结构及其制造方法
公开(公告)号：US20130320463A1
公开(公告)日：2013-12-05
申请号：US13588113
申请日：2012-08-17
申请人： Hong-Da Chang , Cheng-Hsiang Liu , Kuang-Wei Huang , Chun-Hung Lin , Hsin-Yi Liao
发明人： Hong-Da Chang , Cheng-Hsiang Liu , Kuang-Wei Huang , Chun-Hung Lin , Hsin-Yi Liao
IPC分类号： H01L29/84 , H01L21/60
CPC分类号： H01L24/19 , B81B7/007 , B81B2207/098 , H01L21/561 , H01L24/32 , H01L24/48 , H01L24/49 , H01L24/73 , H01L24/83 , H01L24/92 , H01L24/94 , H01L24/97 , H01L2223/54426 , H01L2224/12105 , H01L2224/32145 , H01L2224/48091 , H01L2224/48145 , H01L2224/48464 , H01L2224/49107 , H01L2224/49109 , H01L2224/73265 , H01L2224/83191 , H01L2224/92247 , H01L2224/94 , H01L2224/97 , H01L2225/06506 , H01L2225/06562 , H01L2924/00014 , H01L2924/12042 , H01L2924/1433 , H01L2924/1461 , H01L2924/181 , H01L2224/85 , H01L2924/00012 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A package structure includes: a substrate having a plurality of first conductive pads and a plurality of second conductive pads; an MEMS element disposed on the substrate; a cover member disposed on the MEMS element and having a metal layer formed thereon; a plurality of bonding wires electrically connected to the MEMS element and the second conductive pads of the substrate; a plurality of first wire segments, each having one end electrically connected to a corresponding one of the first conductive pads; and an encapsulant formed on the substrate and encapsulating the MEMS element, the cover member, the first wire segments and the bonding wires, wherein the other end of each of the first wire segments is exposed from the encapsulant. Compared with the prior art, the package structure of the present invention has improved overall yield and functionality.
摘要翻译：封装结构包括：具有多个第一导电焊盘和多个第二导电焊盘的衬底; 设置在所述基板上的MEMS元件; 盖构件，其设置在所述MEMS元件上并且在其上形成有金属层; 电连接到所述MEMS元件和所述基板的所述第二导电焊盘的多个接合线; 多个第一线段，每个第一线段的一端电连接到相应的一个第一导电焊盘; 以及形成在所述衬底上并封装所述MEMS元件，所述盖构件，所述第一线段和所述接合线的密封剂，其中所述第一线段中的每一个的另一端从所述密封剂暴露。与现有技术相比，本发明的封装结构具有改善的总产率和功能。

2. 发明授权

US08633048B2 Method for fabricating package structure having MEMS elements 有权
标题翻译：制造具有MEMS元件的封装结构的方法
公开(公告)号：US08633048B2
公开(公告)日：2014-01-21
申请号：US13314807
申请日：2011-12-08
申请人： Chen-Han Lin , Hong-Da Chang , Cheng-Hsiang Liu , Hsin-Yi Liao , Shih-Kuang Chiu
发明人： Chen-Han Lin , Hong-Da Chang , Cheng-Hsiang Liu , Hsin-Yi Liao , Shih-Kuang Chiu
IPC分类号： H01L21/00
CPC分类号： B81C1/00301 , B81C2203/0154 , H01L2224/48227 , H01L2924/1461 , H01L2924/16151 , H01L2924/16152 , H01L2924/3025 , H01L2924/00
摘要： A fabrication method of a package structure having MEMS elements includes: disposing a plate on top of a wafer having MEMS elements and second alignment keys; cutting the plate to form therein a plurality of openings exposing the second alignment keys; performing a wire bonding process and disposing block bodies corresponding to the second alignment keys, respectively; forming an encapsulant and partially removing the encapsulant and the block bodies from the top of the encapsulant; and aligning through the second alignment keys so as to form on the encapsulant a plurality of metal traces. The present invention eliminates the need to form through holes in a silicon substrate as in the prior art so as to reduce the fabrication costs. Further, since the plate only covers the MEMS elements and the encapsulant is partially removed, the overall thickness and size of the package structure are reduced.
摘要翻译：具有MEMS元件的封装结构的制造方法包括：将板放置在具有MEMS元件和第二对准键的晶片的顶部上; 切割板以在其中形成暴露第二对准键的多个开口; 执行引线接合处理并分别布置与第二对准键对应的块体; 形成密封剂并从密封剂的顶部部分地去除密封剂和块体; 并且通过第二对准键对齐，以在密封剂上形成多个金属迹线。本发明消除了如现有技术中在硅衬底中形成通孔的需要，从而降低制造成本。此外，由于板仅覆盖MEMS元件并且部分地去除了密封剂，因此减小了封装结构的整体厚度和尺寸。

3. 发明授权

US09133021B2 Wafer level package having a pressure sensor and fabrication method thereof 有权
标题翻译：具有压力传感器的晶片级封装及其制造方法
公开(公告)号：US09133021B2
公开(公告)日：2015-09-15
申请号：US13090852
申请日：2011-04-20
申请人： Hong-Da Chang , Hsin-Yi Liao , Chun-An Huang , Shih-Kuang Chiu , Chien-An Chen
发明人： Hong-Da Chang , Hsin-Yi Liao , Chun-An Huang , Shih-Kuang Chiu , Chien-An Chen
IPC分类号： H01L29/84 , B81C1/00
CPC分类号： B81C1/00301 , B81B2201/0264 , B81C1/00269 , B81C2203/0154 , H01L29/84 , H01L2224/48091 , H01L2924/10253 , H01L2924/1461 , H01L2924/00014 , H01L2924/00
摘要： A wafer level package having a pressure sensor and a fabrication method thereof are provided. A wafer having the pressure sensor is bonded to a lid, and electrical connecting pads are formed on the wafer. After the lid is cut, wire-bonding and packaging processes are performed. Ends of bonding wires are exposed and serve as an electrical connecting path. A bottom opening is formed on a bottom surface of the wafer, in order to form a pressure sensor path.
摘要翻译：提供了具有压力传感器及其制造方法的晶片级封装。将具有压力传感器的晶片接合到盖上，并且在晶片上形成电连接焊盘。在切割盖子之后，进行引线键合和封装处理。接合线的端部暴露并用作电连接路径。为了形成压力传感器路径，在晶片的底面上形成底部开口。

4. 发明申请

US20120292722A1 PACKAGE STRUCTURE HAVING MEMS ELEMENTS AND FABRICATION METHOD THEREOF 有权
标题翻译：具有MEMS元件的包装结构及其制造方法
公开(公告)号：US20120292722A1
公开(公告)日：2012-11-22
申请号：US13242720
申请日：2011-09-23
申请人： Chen-Han Lin , Hong-Da Chang , Hsin-Yi Liao , Shih-Kuang Chiu
发明人： Chen-Han Lin , Hong-Da Chang , Hsin-Yi Liao , Shih-Kuang Chiu
IPC分类号： H01L29/84 , H01L31/0224 , H01L31/18 , H01L21/78 , H01L31/0203 , H01L21/56
CPC分类号： B81B7/007 , B81B2207/098 , B81C2203/054 , H01L2224/48091 , H01L2924/1461 , H01L2924/16151 , H01L2924/16152 , H01L2924/3025 , H01L2924/00014 , H01L2924/00
摘要： A package structure having MEMS elements includes: a wafer having MEMS elements, electrical contacts and second alignment keys; a plate disposed over the MEMS elements and packaged airtight; transparent bodies disposed over the second alignment keys via an adhesive; an encapsulant disposed on the wafer to encapsulate the plate, the electrical contacts and the transparent bodies; bonding wires embedded in the encapsulant and each having one end connecting a corresponding one of the electrical contacts and the other end exposed from a top surface of the encapsulant; and metal traces disposed on the encapsulant and electrically connected to the electrical contacts via the bonding wires. The present invention eliminates the need to form through holes in a silicon substrate as in the prior art so as to reduce fabrication costs. Further, the present invention accomplishes wiring processes by using a common alignment device to thereby reduce equipment costs.
摘要翻译：具有MEMS元件的封装结构包括：具有MEMS元件，电触点和第二对准键的晶片; 设置在MEMS元件上并被气密封装的板; 通过粘合剂设置在第二对准键上方的透明体; 设置在晶片上以封装所述板，所述电触点和所述透明体的密封剂; 嵌入密封剂中的接合线，每个具有一端连接相应的一个电触点，另一端从该密封剂的顶表面露出; 以及设置在密封剂上并通过接合线电连接到电触头的金属迹线。本发明消除了如现有技术中在硅衬底中形成通孔的需要，以便降低制造成本。此外，本发明通过使用公共对准装置实现布线处理，从而降低设备成本。

5. 发明授权

US08525324B2 Semiconductor package and method of fabricating the same 有权
标题翻译：半导体封装及其制造方法
公开(公告)号：US08525324B2
公开(公告)日：2013-09-03
申请号：US13542026
申请日：2012-07-05
申请人： Hong-Da Chang , Hsin-Yi Liao
发明人： Hong-Da Chang , Hsin-Yi Liao
IPC分类号： H01L23/04 , H01L21/50
CPC分类号： B81C1/0023 , B81B2207/012 , B81B2207/098 , H01L2224/48091 , H01L2924/1461 , H01L2924/00014 , H01L2924/00
摘要： A semiconductor package is provided, which includes: a micro electro mechanical system (MEMS) chip; a cap provided on the MEMS chip; an electronic element provided on the cap including a plurality of first conductive pads and second conductive pads; a plurality of first conductive elements electrically connected to the first conductive pads and the MEMS chip; a plurality of second conductive elements formed on the second conductive pads, respectively; and an encapsulant formed on the MEMS chip covering the cap, the electronic element, the first conductive elements and the second conductive elements, with the second conductive elements being exposed from the encapsulant. Thus, the size of the semiconductor package is reduced. A method of fabricating the semiconductor package is also disclosed.
摘要翻译：提供了一种半导体封装，其包括：微机电系统（MEMS）芯片; 提供在MEMS芯片上的盖; 设置在所述盖上的电子元件包括多个第一导电焊盘和第二导电焊盘; 电连接到第一导电焊盘和MEMS芯片的多个第一导电元件; 分别形成在所述第二导电焊盘上的多个第二导电元件; 以及密封剂，其形成在覆盖所述帽，所述电子元件，所述第一导电元件和所述第二导电元件的所述MEMS芯片上，其中所述第二导电元件从所述密封剂暴露。因此，半导体封装的尺寸减小。还公开了制造半导体封装的方法。

6. 发明申请

US20130075888A1 SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME 有权
标题翻译：半导体封装及其制造方法
公开(公告)号：US20130075888A1
公开(公告)日：2013-03-28
申请号：US13542026
申请日：2012-07-05
申请人： Hong-Da Chang , Hsin-Yi Liao
发明人： Hong-Da Chang , Hsin-Yi Liao
IPC分类号： H01L23/04 , H01L21/50
CPC分类号： B81C1/0023 , B81B2207/012 , B81B2207/098 , H01L2224/48091 , H01L2924/1461 , H01L2924/00014 , H01L2924/00
摘要： A semiconductor package is provided, which includes: a micro electro mechanical system (MEMS) chip; a cap provided on the MEMS chip; an electronic element provided on the cap including a plurality of first conductive pads and second conductive pads; a plurality of first conductive elements electrically connected to the first conductive pads and the MEMS chip; a plurality of second conductive elements formed on the second conductive pads, respectively; and an encapsulant formed on the MEMS chip covering the cap, the electronic element, the first conductive elements and the second conductive elements, with the second conductive elements being exposed from the encapsulant. Thus, the size of the semiconductor package is reduced. A method of fabricating the semiconductor package is also disclosed.
摘要翻译：提供了一种半导体封装，其包括：微机电系统（MEMS）芯片; 提供在MEMS芯片上的盖; 设置在所述盖上的电子元件包括多个第一导电焊盘和第二导电焊盘; 电连接到第一导电焊盘和MEMS芯片的多个第一导电元件; 分别形成在所述第二导电焊盘上的多个第二导电元件; 以及密封剂，其形成在覆盖所述帽，所述电子元件，所述第一导电元件和所述第二导电元件的所述MEMS芯片上，其中所述第二导电元件从所述密封剂暴露。因此，半导体封装的尺寸减小。还公开了制造半导体封装的方法。

7. 发明申请

US20120001274A1 WAFER LEVEL PACKAGE HAVING A PRESSURE SENSOR AND FABRICATION METHOD THEREOF 有权
标题翻译：具有压力传感器的水平包装及其制造方法
公开(公告)号：US20120001274A1
公开(公告)日：2012-01-05
申请号：US13090852
申请日：2011-04-20
申请人： Hong-Da Chang , Hsin-Yi Liao , Chun-An Huang , Shih-Kuang Chiu , Chien-An Chen
发明人： Hong-Da Chang , Hsin-Yi Liao , Chun-An Huang , Shih-Kuang Chiu , Chien-An Chen
IPC分类号： H01L29/84 , H01L21/283
CPC分类号： B81C1/00301 , B81B2201/0264 , B81C1/00269 , B81C2203/0154 , H01L29/84 , H01L2224/48091 , H01L2924/10253 , H01L2924/1461 , H01L2924/00014 , H01L2924/00
摘要： A wafer level package having a pressure sensor and a fabrication method thereof are provided. A wafer having the pressure sensor is bonded to a lid, and electrical connecting pads are formed on the wafer. After the lid is cut, wire-bonding and packaging processes are performed. Ends of bonding wires are exposed and serve as an electrical connecting path. A bottom opening is formed on a bottom surface of the wafer, in order to form a pressure sensor path.
摘要翻译：提供了具有压力传感器及其制造方法的晶片级封装。将具有压力传感器的晶片接合到盖上，并且在晶片上形成电连接焊盘。在切割盖子之后，进行引线键合和封装处理。接合线的端部暴露并用作电连接路径。为了形成压力传感器路径，在晶片的底面上形成底部开口。

8. 发明授权

US08399940B2 Package structure having MEMS elements and fabrication method thereof 有权
标题翻译：具有MEMS元件的封装结构及其制造方法
公开(公告)号：US08399940B2
公开(公告)日：2013-03-19
申请号：US13242720
申请日：2011-09-23
申请人： Chen-Han Lin , Hong-Da Chang , Hsin-Yi Liao , Shih-Kuang Chiu
发明人： Chen-Han Lin , Hong-Da Chang , Hsin-Yi Liao , Shih-Kuang Chiu
IPC分类号： H01L29/84
CPC分类号： B81B7/007 , B81B2207/098 , B81C2203/054 , H01L2224/48091 , H01L2924/1461 , H01L2924/16151 , H01L2924/16152 , H01L2924/3025 , H01L2924/00014 , H01L2924/00
摘要： A package structure having MEMS elements includes: a wafer having MEMS elements, electrical contacts and second alignment keys; a plate disposed over the MEMS elements and packaged airtight; transparent bodies disposed over the second alignment keys via an adhesive; an encapsulant disposed on the wafer to encapsulate the plate, the electrical contacts and the transparent bodies; bonding wires embedded in the encapsulant and each having one end connecting a corresponding one of the electrical contacts and the other end exposed from a top surface of the encapsulant; and metal traces disposed on the encapsulant and electrically connected to the electrical contacts via the bonding wires. The present invention eliminates the need to form through holes in a silicon substrate as in the prior art so as to reduce fabrication costs. Further, the present invention accomplishes wiring processes by using a common alignment device to thereby reduce equipment costs.
摘要翻译：具有MEMS元件的封装结构包括：具有MEMS元件，电触点和第二对准键的晶片; 设置在MEMS元件上并被气密封装的板; 通过粘合剂设置在第二对准键上方的透明体; 设置在晶片上以封装所述板，所述电触点和所述透明体的密封剂; 嵌入密封剂中的接合线，每个具有一端连接相应的一个电触点，另一端从该密封剂的顶表面露出; 以及设置在密封剂上并通过接合线电连接到电触头的金属迹线。本发明消除了如现有技术中在硅衬底中形成通孔的需要，以便降低制造成本。此外，本发明通过使用公共对准装置实现布线处理，从而降低设备成本。

9. 发明授权

US08829672B2 Semiconductor package, package structure and fabrication method thereof 有权
标题翻译：半导体封装，封装结构及其制造方法
公开(公告)号：US08829672B2
公开(公告)日：2014-09-09
申请号：US13563052
申请日：2012-07-31
申请人： Yan-Heng Chen , Jung-Pang Huang , Hsin-Yi Liao , Shih-Kuang Chiu , Guang-Hwa Ma
发明人： Yan-Heng Chen , Jung-Pang Huang , Hsin-Yi Liao , Shih-Kuang Chiu , Guang-Hwa Ma
IPC分类号： H01L21/56 , H01L23/48 , H01L21/02 , H01L21/50 , H01L21/60 , H01L29/84 , H01L23/34
CPC分类号： H01L24/11 , H01L21/561 , H01L21/568 , H01L23/3107 , H01L23/3128 , H01L23/5389 , H01L24/14 , H01L24/19 , H01L24/24 , H01L24/81 , H01L24/96 , H01L25/105 , H01L2224/033 , H01L2224/0401 , H01L2224/04105 , H01L2224/12105 , H01L2224/1412 , H01L2224/16225 , H01L2224/24137 , H01L2224/48227 , H01L2224/81 , H01L2225/1035 , H01L2225/1058 , H01L2924/12042 , H01L2924/15311 , H01L2924/15321 , H01L2924/15331 , H01L2924/181 , H01L2924/18162 , H01L2924/00 , H01L2924/00012
摘要： A semiconductor package includes: a dielectric layer having opposite first and second surfaces; a semiconductor chip embedded in the dielectric layer and having a plurality of electrode pads; a plurality of first metal posts disposed on the electrode pads of the semiconductor chip, respectively, such that top ends of the first metal posts are exposed from the first surface; at least a second metal post penetrating the dielectric layer such that two opposite ends of the second metal post are exposed from the first and second surfaces, respectively; a first circuit layer formed on the first surface for electrically connecting the first and second metal posts; and a second circuit layer formed on the second surface for electrically connecting the second metal post. The semiconductor package dispenses with conventional laser ablation and electroplating processes for forming conductive posts in a molding compound, thereby saving fabrication time and cost.
摘要翻译：半导体封装包括：具有相反的第一和第二表面的电介质层; 嵌入在介电层中并具有多个电极焊盘的半导体芯片; 分别设置在半导体芯片的电极焊盘上的多个第一金属柱，使得第一金属柱的顶端从第一表面露出; 至少第二金属柱穿透介电层，使得第二金属柱的两个相对端分别从第一表面和第二表面露出; 第一电路层，形成在第一表面上，用于电连接第一和第二金属柱; 以及形成在所述第二表面上用于电连接所述第二金属柱的第二电路层。该半导体封装省去了用于在模塑料中形成导电柱的常规激光烧蚀和电镀工艺，从而节省制造时间和成本。

10. 发明申请

US20120313243A1 CHIP-SCALE PACKAGE 审中-公开
标题翻译： CHIP-SCALE包装
公开(公告)号：US20120313243A1
公开(公告)日：2012-12-13
申请号：US13221323
申请日：2011-08-30
申请人： Chiang-Cheng Chang , Hung-Wen Liu , Hsi-Chang Hsu , Hsin-Yi Liao , Shih-Kuang Chiu
发明人： Chiang-Cheng Chang , Hung-Wen Liu , Hsi-Chang Hsu , Hsin-Yi Liao , Shih-Kuang Chiu
IPC分类号： H01L23/498 , H01L23/48
CPC分类号： H01L23/3128 , H01L23/3114 , H01L24/19 , H01L2224/0401 , H01L2224/04105 , H01L2224/12105 , H01L2224/32225 , H01L2224/73267 , H01L2924/18162
摘要： A chip-scale package includes an encapsulating layer, a chip embedded in the encapsulating layer and having an active surface exposed from the encapsulating layer, a buffering dielectric layer formed on the encapsulating layer and the chip, a build-up dielectric layer formed on the buffering dielectric layer, and a circuit layer formed on the build-up dielectric layer and having conductive blind vias penetrating the build-up dielectric layer and being in communication with the openings of the buffering dielectric layer and electrically connected to the chip, wherein the build-up dielectric layer and the buffering dielectric layer are made of different materials. Therefore, delamination does not occur between the buffering dielectric layer and the encapsulating layer, because the buffering dielectric layer is securely bonded to the encapsulating layer and the buffering dielectric layer is evenly distributed on the encapsulating layer.
摘要翻译：芯片级封装包括封装层，嵌入封装层中的芯片，并且具有从封装层露出的有源表面，形成在封装层和芯片上的缓冲电介质层，形成在封装层上的积聚介电层缓冲电介质层和形成在积聚电介质层上的电路层，并且具有穿透积聚介电层并且与缓冲电介质层的开口连通并且电连接到芯片的导电盲孔，其中构建介电层和缓冲电介质层由不同的材料制成。因此，缓冲电介质层和封装层之间不会发生分层，因为缓冲电介质层牢固地结合到封装层，并且缓冲电介质层均匀地分布在封装层上。

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