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1. 发明申请

US20050027941A1 Method and apparatus for affinity-guided speculative helper threads in chip multiprocessors 有权
标题翻译：芯片多处理器中亲和力引导的投机辅助线程的方法和装置
公开(公告)号：US20050027941A1
公开(公告)日：2005-02-03
申请号：US10632431
申请日：2003-07-31
申请人： Hong Wang , Perry Wang , Jeffery Brown , Per Hammarlund , George Chrysos , Doron Orenstein , Steve Liao , John Shen
发明人： Hong Wang , Perry Wang , Jeffery Brown , Per Hammarlund , George Chrysos , Doron Orenstein , Steve Liao , John Shen
IPC分类号： G06F9/38 , G06F12/08 , G06F12/00
CPC分类号： G06F9/3842 , G06F9/383 , G06F9/3851 , G06F12/0862
摘要： Apparatus, system and methods are provided for performing speculative data prefetching in a chip multiprocessor (CMP). Data is prefetched by a helper thread that runs on one core of the CMP while a main program runs concurrently on another core of the CMP. Data prefetched by the helper thread is provided to the helper core. For one embodiment, the data prefetched by the helper thread is pushed to the main core. It may or may not be provided to the helper core as well. A push of prefetched data to the main core may occur during a broadcast of the data to all cores of an affinity group. For at least one other embodiment, the data prefetched by a helper thread is provided, upon request from the main core, to the main core from the helper core's local cache.
摘要翻译：提供了用于在芯片多处理器（CMP）中执行推测性数据预取的装置，系统和方法。数据由在CMP的一个核心上运行的辅助线程预取，而主程序在CMP的另一个核心上同时运行。由辅助线程预取的数据被提供给辅助核心。对于一个实施例，由辅助线程预取的数据被推送到主核心。它也可以也可以不被提供给辅助核心。在将数据广播到亲和组的所有核心的过程中，可能会将预取数据推送到主核心。对于至少另一个实施例，根据主核心的请求，从辅助核心的本地高速缓存提供由辅助线程预取的数据到主核心。

2. 发明申请

US20060294347A1 Programmable event driven yield mechanism which may activate service threads 有权
标题翻译：可编程事件驱动的产生机制，可以激活服务线程
公开(公告)号：US20060294347A1
公开(公告)日：2006-12-28
申请号：US11134687
申请日：2005-05-19
申请人： Xiang Zou , Hong Wang , Scott Rodgers , Darrell Boggs , Bryant Bigbee , Shivanandan Kaushik , Anil Aggarwal , Ittai Anati , Doron Orenstein , Per Hammarlund , John Shen , Larry Smith , James Crossland , Chris Newburn
发明人： Xiang Zou , Hong Wang , Scott Rodgers , Darrell Boggs , Bryant Bigbee , Shivanandan Kaushik , Anil Aggarwal , Ittai Anati , Doron Orenstein , Per Hammarlund , John Shen , Larry Smith , James Crossland , Chris Newburn
IPC分类号： G06F9/44
CPC分类号： G06F9/3851 , G06F9/30087 , G06F9/3009 , G06F9/4843 , G06F11/3409 , G06F11/348 , G06F2201/86 , G06F2201/88 , G06F2201/885
摘要： Method, apparatus, and system for a programmable event driven yield mechanism that may activate other threads. The yield mechanism may allow triggering of a service thread that may execute currently with a main thread upon occurrence of an architecturally-defined condition. The service thread may be activated, in response to the condition, with limited intervention of an operating system. In one embodiment, an apparatus includes execution resources to execute a plurality of instructions and a monitor to detect an architecturally-defined condition. The apparatus may include an event handler to handle a yield event generated when the architecturally-defined condition has been detected. An architectural mechanism, including processor instructions and channel registers, may be utilized to allow user-level code to enable the yield event mechanism. Other embodiments are also described and claimed.
摘要翻译：用于可激活其他线程的可编程事件驱动产量机制的方法，装置和系统。收益机制可以允许在出现体系结构定义的条件时触发可以执行当前与主线程的服务线程。响应于条件，可以在操作系统的有限干预下激活服务线程。在一个实施例中，装置包括执行多个指令的执行资源和监视器以检测体系结构定义的条件。该装置可以包括事件处理程序，用于处理当检测到体系结构定义的条件时产生的产出事件。可以使用包括处理器指令和通道寄存器在内的架构机制来允许用户级代码来实现产出事件机制。还描述和要求保护其他实施例。

3. 发明授权

US07849465B2 Programmable event driven yield mechanism which may activate service threads 有权
标题翻译：可编程事件驱动的产生机制，可以激活服务线程
公开(公告)号：US07849465B2
公开(公告)日：2010-12-07
申请号：US11134687
申请日：2005-05-19
申请人： Xiang Zou , Hong Wang , Scott Dion Rodgers , Darrell D. Boggs , Bryant Bigbee , Shivanandan Kaushik , Anil Aggarwal , Ittai Anati , Doron Orenstein , Per Hammarlund , John Shen , Larry O. Smith , James B. Crossland , Chris J. Newburn
发明人： Xiang Zou , Hong Wang , Scott Dion Rodgers , Darrell D. Boggs , Bryant Bigbee , Shivanandan Kaushik , Anil Aggarwal , Ittai Anati , Doron Orenstein , Per Hammarlund , John Shen , Larry O. Smith , James B. Crossland , Chris J. Newburn
IPC分类号： G06F9/46 , G06F13/24 , G06F7/38
CPC分类号： G06F9/3851 , G06F9/30087 , G06F9/3009 , G06F9/4843 , G06F11/3409 , G06F11/348 , G06F2201/86 , G06F2201/88 , G06F2201/885
摘要： Method, apparatus, and system for a programmable event driven yield mechanism that may activate other threads. The yield mechanism may allow triggering of a service thread that may execute currently with a main thread upon occurrence of an architecturally-defined condition. The service thread may be activated, in response to the condition, with limited intervention of an operating system. In one embodiment, an apparatus includes execution resources to execute a plurality of instructions and a monitor to detect an architecturally-defined condition. The apparatus may include an event handler to handle a yield event generated when the architecturally-defined condition has been detected. An architectural mechanism, including processor instructions and channel registers, may be utilized to allow user-level code to enable the yield event mechanism. Other embodiments are also described and claimed.
摘要翻译：用于可激活其他线程的可编程事件驱动产量机制的方法，装置和系统。收益机制可以允许在出现体系结构定义的条件时触发可以执行当前与主线程的服务线程。响应于条件，可以在操作系统的有限干预下激活服务线程。在一个实施例中，装置包括执行多个指令的执行资源和监视器以检测体系结构定义的条件。该装置可以包括事件处理程序，用于处理当检测到体系结构定义的条件时产生的产出事件。可以使用包括处理器指令和通道寄存器在内的架构机制来允许用户级代码来实现产出事件机制。还描述和要求保护其他实施例。

4. 发明授权

US07844801B2 Method and apparatus for affinity-guided speculative helper threads in chip multiprocessors 有权
标题翻译：芯片多处理器中亲和力引导的投机辅助线程的方法和装置
公开(公告)号：US07844801B2
公开(公告)日：2010-11-30
申请号：US10632431
申请日：2003-07-31
申请人： Hong Wang , Perry H. Wang , Jeffery A. Brown , Per Hammarlund , George Z. Chrysos , Doron Orenstein , Steve Shih-wei Liao , John P. Shen
发明人： Hong Wang , Perry H. Wang , Jeffery A. Brown , Per Hammarlund , George Z. Chrysos , Doron Orenstein , Steve Shih-wei Liao , John P. Shen
IPC分类号： G06F7/38 , G06F9/00 , G06F9/44
CPC分类号： G06F9/3842 , G06F9/383 , G06F9/3851 , G06F12/0862
摘要： Apparatus, system and methods are provided for performing speculative data prefetching in a chip multiprocessor (CMP). Data is prefetched by a helper thread that runs on one core of the CMP while a main program runs concurrently on another core of the CMP. Data prefetched by the helper thread is provided to the helper core. For one embodiment, the data prefetched by the helper thread is pushed to the main core. It may or may not be provided to the helper core as well. A push of prefetched data to the main core may occur during a broadcast of the data to all cores of an affinity group. For at least one other embodiment, the data prefetched by a helper thread is provided, upon request from the main core, to the main core from the helper core's local cache.
摘要翻译：提供了用于在芯片多处理器（CMP）中执行推测性数据预取的装置，系统和方法。数据由在CMP的一个核心上运行的辅助线程预取，而主程序在CMP的另一个核心上同时运行。由辅助线程预取的数据被提供给辅助核心。对于一个实施例，由辅助线程预取的数据被推送到主核心。它也可以也可以不被提供给辅助核心。在将数据广播到亲和组的所有核心的过程中，可能会将预取数据推送到主核心。对于至少另一个实施例，根据主核心的请求，从辅助核心的本地高速缓存提供由辅助线程预取的数据到主核心。

5. 发明申请

US20110035555A1 METHOD AND APPARATUS FOR AFFINITY-GUIDED SPECULATIVE HELPER THREADS IN CHIP MULTIPROCESSORS 有权
标题翻译：芯片多路由器中辅助引导的辅助线路的方法和装置
公开(公告)号：US20110035555A1
公开(公告)日：2011-02-10
申请号：US12909774
申请日：2010-10-21
申请人： Hong Wang , Perry H. Wang , Jeffery A. Brown , Per Hammarlund , George Z. Chrysos , Doron Orenstein , Steve Shih-wei Liao , John P. Shen
发明人： Hong Wang , Perry H. Wang , Jeffery A. Brown , Per Hammarlund , George Z. Chrysos , Doron Orenstein , Steve Shih-wei Liao , John P. Shen
IPC分类号： G06F12/08 , G06F9/44 , G06F12/00 , G06F9/312
CPC分类号： G06F9/3842 , G06F9/383 , G06F9/3851 , G06F12/0862
摘要： Apparatus, system and methods are provided for performing speculative data prefetching in a chip multiprocessor (CMP). Data is prefetched by a helper thread that runs on one core of the CMP while a main program runs concurrently on another core of the CMP. Data prefetched by the helper thread is provided to the helper core. For one embodiment, the data prefetched by the helper thread is pushed to the main core. It may or may not be provided to the helper core as well. A push of prefetched data to the main core may occur during a broadcast of the data to all cores of an affinity group. For at least one other embodiment, the data prefetched by a helper thread is provided, upon request from the main core, to the main core from the helper core's local cache.
摘要翻译：提供了用于在芯片多处理器（CMP）中执行推测性数据预取的装置，系统和方法。数据由在CMP的一个核心上运行的辅助线程预取，而主程序在CMP的另一个核心上同时运行。由辅助线程预取的数据被提供给辅助核心。对于一个实施例，由辅助线程预取的数据被推送到主核心。它也可以也可以不被提供给辅助核心。在将数据广播到亲和组的所有核心的过程中，可能会将预取数据推送到主核心。对于至少另一个实施例，根据主核心的请求，从辅助核心的本地高速缓存提供由辅助线程预取的数据到主核心。

6. 发明授权

US08078831B2 Method and apparatus for affinity-guided speculative helper threads in chip multiprocessors 有权
标题翻译：芯片多处理器中亲和力引导的投机辅助线程的方法和装置
公开(公告)号：US08078831B2
公开(公告)日：2011-12-13
申请号：US12909774
申请日：2010-10-21
申请人： Hong Wang , Perry H. Wang , Jeffery A. Brown , Per Hammarlund , George Z. Chrysos , Doron Orenstein , Steve Shih-wei Liao , John P. Shen
发明人： Hong Wang , Perry H. Wang , Jeffery A. Brown , Per Hammarlund , George Z. Chrysos , Doron Orenstein , Steve Shih-wei Liao , John P. Shen
IPC分类号： G06F15/00 , G06F15/76
CPC分类号： G06F9/3842 , G06F9/383 , G06F9/3851 , G06F12/0862
摘要： Apparatus, system and methods are provided for performing speculative data prefetching in a chip multiprocessor (CMP). Data is prefetched by a helper thread that runs on one core of the CMP while a main program runs concurrently on another core of the CMP. Data prefetched by the helper thread is provided to the helper core. For one embodiment, the data prefetched by the helper thread is pushed to the main core. It may or may not be provided to the helper core as well. A push of prefetched data to the main core may occur during a broadcast of the data to all cores of an affinity group. For at least one other embodiment, the data prefetched by a helper thread is provided, upon request from the main core, to the main core from the helper core's local cache.
摘要翻译：提供了用于在芯片多处理器（CMP）中执行推测性数据预取的装置，系统和方法。数据由在CMP的一个核心上运行的辅助线程预取，而主程序在CMP的另一个核心上同时运行。由辅助线程预取的数据被提供给辅助核心。对于一个实施例，由辅助线程预取的数据被推送到主核心。它也可以也可以不被提供给辅助核心。在将数据广播到亲和组的所有核心的过程中，可能会将预取数据推送到主核心。对于至少另一个实施例，根据主核心的请求，从辅助核心的本地高速缓存提供由辅助线程预取的数据到主核心。

7. 发明申请

US20060095807A1 Method and apparatus for varying energy per instruction according to the amount of available parallelism 有权
标题翻译：根据可用的并行度量来改变每个指令的能量的方法和装置
公开(公告)号：US20060095807A1
公开(公告)日：2006-05-04
申请号：US10952627
申请日：2004-09-28
申请人： Edward Grochowski , John Shen , Hong Wang , Doron Orenstein , Gad Sheaffer , Ronny Ronen , Murali Annavaram
发明人： Edward Grochowski , John Shen , Hong Wang , Doron Orenstein , Gad Sheaffer , Ronny Ronen , Murali Annavaram
IPC分类号： G06F1/30
CPC分类号： G06F9/3851 , G06F1/206 , G06F1/3203 , G06F1/329 , G06F9/3885 , G06F9/3891 , G06F9/3897 , Y02D10/16 , Y02D10/24 , Y02D50/20
摘要： A method and apparatus for changing the configuration of a multi-core processor is disclosed. In one embodiment, a throttle module (or throttle logic) may determine the amount of parallelism present in the currently-executing program, and change the execution of the threads of that program on the various cores. If the amount of parallelism is high, then the processor may be configured to run a larger amount of threads on cores configured to consume less power. If the amount of parallelism is low, then the processor may be configured to run a smaller amount of threads on cores configured for greater scalar performance.
摘要翻译：公开了一种用于改变多核处理器的配置的方法和装置。在一个实施例中，节气门模块（或节气门逻辑）可以确定当前执行的程序中存在的并行度量，并且改变该程序在各种核心上的线程的执行。如果并行量高，则处理器可以被配置为在被配置为消耗较少功率的核上运行更大量的线程。如果并行量较低，则处理器可能被配置为在配置为更高标量性能的核心上运行较少量的线程。

8. 发明授权

US07437581B2 Method and apparatus for varying energy per instruction according to the amount of available parallelism 有权
标题翻译：根据可用的并行度量来改变每个指令的能量的方法和装置
公开(公告)号：US07437581B2
公开(公告)日：2008-10-14
申请号：US10952627
申请日：2004-09-28
申请人： Edward Grochowski , John Shen , Hong Wang , Doron Orenstein , Gad S Sheaffer , Ronny Ronen , Murali M. Annavaram
发明人： Edward Grochowski , John Shen , Hong Wang , Doron Orenstein , Gad S Sheaffer , Ronny Ronen , Murali M. Annavaram
IPC分类号： G06F1/32 , G06F9/46
CPC分类号： G06F9/3851 , G06F1/206 , G06F1/3203 , G06F1/329 , G06F9/3885 , G06F9/3891 , G06F9/3897 , Y02D10/16 , Y02D10/24 , Y02D50/20
摘要： A method and apparatus for changing the configuration of a multi-core processor is disclosed. In one embodiment, a throttle module (or throttle logic) may determine the amount of parallelism present in the currently-executing program, and change the execution of the threads of that program on the various cores. If the amount of parallelism is high, then the processor may be configured to run a larger amount of threads on cores configured to consume less power. If the amount of parallelism is low, then the processor may be configured to run a smaller amount of threads on cores configured for greater scalar performance.
摘要翻译：公开了一种用于改变多核处理器的配置的方法和装置。在一个实施例中，节气门模块（或节气门逻辑）可以确定当前执行的程序中存在的并行度量，并且改变该程序在各种核心上的线程的执行。如果并行量高，则处理器可以被配置为在被配置为消耗较少功率的核上运行更大量的线程。如果并行量较低，则处理器可能被配置为在配置为更高标量性能的核心上运行较少量的线程。

9. 发明授权

US09569208B2 Compressed instruction format 有权
标题翻译：压缩指令格式
公开(公告)号：US09569208B2
公开(公告)日：2017-02-14
申请号：US14307468
申请日：2014-06-17
申请人： Robert Valentine , Doron Orenstein , Brett L. Toll
发明人： Robert Valentine , Doron Orenstein , Brett L. Toll
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： G06F9/30 , G06F9/30145 , G06F9/30149 , G06F9/3017 , G06F9/30174 , G06F9/30178 , G06F9/30185 , G06F9/3816 , G06F9/382
摘要： A technique for decoding an instruction in a variable-length instruction set. In one embodiment, an instruction encoding is described, in which legacy, present, and future instruction set extensions are supported, and increased functionality is provided, without expanding the code size and, in some cases, reducing the code size.
摘要翻译：一种解码可变长度指令集中的指令的技术。在一个实施例中，描述了指令编码，其中支持遗留，现在和将来的指令集扩展，并且提供增加的功能，而不扩展代码大小，并且在一些情况下减少代码大小。

10. 发明申请

US20100332794A1 UNPACKING PACKED DATA IN MULTIPLE LANES 有权
标题翻译：在多个土地上打包包装数据
公开(公告)号：US20100332794A1
公开(公告)日：2010-12-30
申请号：US12494667
申请日：2009-06-30
申请人： Asaf Hargil , Doron Orenstein
发明人： Asaf Hargil , Doron Orenstein
IPC分类号： G06F15/76
CPC分类号： G06F9/30145 , G06F9/30032 , G06F9/30036
摘要： Receiving an instruction indicating first and second operands. Each of the operands having packed data elements that correspond in respective positions. A first subset of the data elements of the first operand and a first subset of the data elements of the second operand each corresponding to a first lane. A second subset of the data elements of the first operand and a second subset of the data elements of the second operand each corresponding to a second lane. Storing result, in response to instruction, including: (1) in first lane, only lowest order data elements from first subset of first operand interleaved with corresponding lowest order data elements from first subset of second operand; and (2) in second lane, only highest order data elements from second subset of first operand interleaved with corresponding highest order data elements from second subset of second operand.
摘要翻译：接收指示第一和第二操作数的指令。每个操作数具有在相应位置对应的数据元素的打包。第一操作数的数据元素的第一子集和第二操作数的数据元素的第一子集，每个对应于第一通道。所述第一操作数的数据元素的第二子集和所述第二操作数的数据元素的第二子集分别对应于第二通道。存储结果，响应于指令，包括：（1）在第一通道中，仅来自第一操作数的第一子集的最低顺序数据元素与来自第二操作数的第一子集的相应最低数据元素交织; 和（2）在第二通道中，仅来自第一操作数的第二子集的最高阶数据元素与来自第二操作数的第二子集的对应最高阶数据元素交织。

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