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1. 发明授权

US08044723B2 Oscillator signal generation with spur mitigation in a wireless communication device 有权
标题翻译：在无线通信设备中产生振荡器信号并产生振荡
公开(公告)号：US08044723B2
公开(公告)日：2011-10-25
申请号：US11868824
申请日：2007-10-08
申请人： Hong Sun Kim , Jin Wook Kim , Gang Zhang , Jeremy Darren Dunworth , Timothy Paul Pals
发明人： Hong Sun Kim , Jin Wook Kim , Gang Zhang , Jeremy Darren Dunworth , Timothy Paul Pals
IPC分类号： H03L7/107
CPC分类号： H03L7/193 , H03L7/107 , H03L7/1976
摘要： Techniques for generating oscillator signals in a wireless communication device are described. A phase-locked loop (PLL) may be used to generate an oscillator signal for a selected frequency channel. Different PLL settings may be used for the blocks in the PLL for different frequency channels. The different PLL settings may be for different PLL loop bandwidths, different amounts of charge pump current, different frequency equations associated with different sets of high and low divider ratios, different frequency division schemes associated with different prescaler ratios and/or different integer divider ratios, high side or low side injection for a super-heterodyne receiver or transmitter, and/or different supply voltages for one or more circuit blocks such as an oscillator. A suitable set of PLL settings may be selected for each frequency channel such that adverse impact due to spurs can be mitigated.
摘要翻译：描述了在无线通信设备中产生振荡器信号的技术。可以使用锁相环（PLL）来产生所选频道的振荡器信号。对于不同的频率通道，PLL中的块可能使用不同的PLL设置。不同的PLL设置可能是针对不同的PLL环路带宽，不同的电荷泵浦电流量，与不同的高和低分频比组相关的不同频率方程，与不同的预分频比和/或不同的整数分频比相关的不同分频方案，用于超外差接收器或发射器的高侧或低侧注入，和/或用于一个或多个电路块（例如振荡器）的不同电源电压。可以为每个频道选择合适的一组PLL设置，从而可以减轻由于刺激引起的不利影响。

2. 发明申请

US20090072912A1 OSCILLATOR SIGNAL GENERATION WITH SPUR MITIGATION IN A WIRELESS COMMUNICATION DEVICE 有权
标题翻译：振荡器信号发生在无线通信设备中的缓和
公开(公告)号：US20090072912A1
公开(公告)日：2009-03-19
申请号：US11868824
申请日：2007-10-08
申请人： Hong Sun Kim , Jin Wook Kim , Gang Zhang , Jeremy Darren Dunworth , Timothy Paul Pals
发明人： Hong Sun Kim , Jin Wook Kim , Gang Zhang , Jeremy Darren Dunworth , Timothy Paul Pals
IPC分类号： H03L7/18 , H03L7/08 , H03L7/085 , H04B1/40 , H03L7/099
CPC分类号： H03L7/193 , H03L7/107 , H03L7/1976
摘要： Techniques for generating oscillator signals in a wireless communication device are described. A phase-locked loop (PLL) may be used to generate an oscillator signal for a selected frequency channel. Different PLL settings may be used for the blocks in the PLL for different frequency channels. The different PLL settings may be for different PLL loop bandwidths, different amounts of charge pump current, different frequency equations associated with different sets of high and low divider ratios, different frequency division schemes associated with different prescaler ratios and/or different integer divider ratios, high side or low side injection for a super-heterodyne receiver or transmitter, and/or different supply voltages for one or more circuit blocks such as an oscillator. A suitable set of PLL settings may be selected for each frequency channel such that adverse impact due to spurs can be mitigated.
摘要翻译：描述了在无线通信设备中产生振荡器信号的技术。可以使用锁相环（PLL）来产生所选频道的振荡器信号。对于不同的频率通道，PLL中的块可能使用不同的PLL设置。不同的PLL设置可以用于不同的PLL环路带宽，不同的电荷泵浦电流量，与不同的高和低分频比组相关的不同频率方程，与不同预分频器比率和/或不同的整数分频比相关的不同分频方案，用于超外差接收器或发射器的高侧或低侧注入，和/或用于一个或多个电路块（例如振荡器）的不同电源电压。可以为每个频道选择合适的一组PLL设置，从而可以减轻由于刺激引起的不利影响。

3. 发明申请

US20180090509A1 SEMICONDUCTOR MEMORY DEVICES 审中-公开
公开(公告)号：US20180090509A1
公开(公告)日：2018-03-29
申请号：US15822586
申请日：2017-11-27
申请人： Gang Zhang , Hyuk KIM , Yong-Hyun KWON , Sangwuk PARK
发明人： Gang Zhang , Hyuk KIM , Yong-Hyun KWON , Sangwuk PARK
IPC分类号： H01L27/092 , H01L27/12 , H01L23/522 , H01L27/118
CPC分类号： H01L27/11573 , H01L23/5226 , H01L27/0925 , H01L27/1157 , H01L27/11575 , H01L27/11582 , H01L27/1207 , H01L2027/11861 , H01L2924/1438
摘要： Provided is a semiconductor memory device. The semiconductor memory device includes a peripheral circuit gate pattern on a first substrate, an impurity region in the first substrate and spaced apart from the peripheral circuit gate pattern, a cell array structure on the peripheral circuit gate pattern, a second substrate between the peripheral circuit gate pattern and the cell array structure, and a via that is in contact with the impurity region and disposed between the first substrate and the second substrate. The via electrically connects the first and second substrates to each other.

4. 发明申请

US20160071855A1 Semiconductor Device 审中-公开
标题翻译：半导体器件
公开(公告)号：US20160071855A1
公开(公告)日：2016-03-10
申请号：US14841328
申请日：2015-08-31
申请人： Sang Wuk Park , Hyuk Kim , Kyoung Sub Shin , Gang Zhang
发明人： Sang Wuk Park , Hyuk Kim , Kyoung Sub Shin , Gang Zhang
IPC分类号： H01L27/115
CPC分类号： H01L27/11582 , H01L27/11524 , H01L27/11556 , H01L27/1157
摘要： A semiconductor device includes gate stacks disposed on a substrate and spaced apart from each other in a first direction, with a separation region interposed between the gate stacks; channel regions penetrating through the gate stacks and disposed within each of the gate stacks; and a guide region adjacent to the separation region, penetrating through at least a portion of the gate stack, and having a bent portion that is bent toward the separation region.
摘要翻译：半导体器件包括设置在衬底上并且在第一方向上彼此间隔开的栅极叠层，隔离区域插入在栅极堆叠之间; 沟道区域穿过栅极堆叠并设置在每个栅极堆叠内; 以及与所述分离区域相邻的引导区域，穿过所述栅极堆叠的至少一部分，并且具有朝向所述分离区域弯曲的弯曲部分。

5. 发明授权

US09153705B2 Vertical memory devices and methods of manufacturing the same 有权
标题翻译：垂直存储器件及其制造方法
公开(公告)号：US09153705B2
公开(公告)日：2015-10-06
申请号：US14187548
申请日：2014-02-24
申请人： Gang Zhang , Kyoung-Sub Shin
发明人： Gang Zhang , Kyoung-Sub Shin
IPC分类号： H01L27/115 , H01L29/792 , H01L29/78 , H01L27/105 , H01L27/24 , H01L29/66
CPC分类号： H01L29/792 , H01L27/1052 , H01L27/11575 , H01L27/11578 , H01L27/11582 , H01L27/2481 , H01L29/66833 , H01L29/7827 , H01L29/7926
摘要： A memory device includes a plurality of channels, a plurality of first charge storage sites coupled to first sides of respective ones of the channels, and a plurality of second charge storage sites coupled to second sides of respective ones of the channels. The first charge storage sites correspond to first memory cells and the second charge storage sites coupled to second memory cells. At least one of the channels is a dummy channel not connected to a bit line, and a blocking layer is contiguously formed around the first and second charge storage sites and the channels.
摘要翻译：存储器件包括多个通道，耦合到相应通道的第一侧的多个第一电荷存储位置以及耦合到相应通道的第二侧的多个第二电荷存储位置。第一电荷存储位置对应于第一存储器单元和耦合到第二存储器单元的第二电荷存储位置。通道中的至少一个是不连接到位线的虚拟通道，并且阻挡层围绕第一和第二电荷存储位置和通道连续地形成。

6. 发明授权

US08553827B2 ADC-based mixed-mode digital phase-locked loop 失效
标题翻译：基于ADC的混合模式数字锁相环
公开(公告)号：US08553827B2
公开(公告)日：2013-10-08
申请号：US12582661
申请日：2009-10-20
申请人： Gang Zhang
发明人： Gang Zhang
IPC分类号： H03D3/24
CPC分类号： H03L7/1072 , H03L7/093 , H03L7/1976
摘要： A Phase-Locked Loop (PLL) includes a Phase-to-Digital Converter (PDC), a programmable digital loop filter, a Digitally-Controlled Oscillator (DCO), and a loop divider. Within the PDC, phase information is converted into a stream of digital values by a charge pump and an Analog-to-Digital Converter (ADC). The stream of digital values is supplied to the digital loop filter which in turn supplies digital tuning words to the DCO. A number of types of ADCs can be used for the ADC including a continuous-time delta-sigma oversampling Digital ADC and a Successive Approximation ADC. The voltage signal on the charge pump output is a small amplitude midrange voltage signal. The small voltage amplitude of the signal leads to numerous advantages including improved charge pump linearity, reduced charge pump noise, and lower supply voltage operation of the overall PLL.
摘要翻译：锁相环（PLL）包括一个相位数转换器（PDC），一个可编程数字环路滤波器，一个数字控制振荡器（DCO）和一个环路分频器。在PDC中，相位信息由电荷泵和模数转换器（ADC）转换成数字值流。数字值流被提供给数字环路滤波器，数字环路滤波器又向DCO提供数字调谐字。 ADC可以使用多种类型的ADC，包括连续时间Δ-sigma过采样数字ADC和逐次逼近ADC。电荷泵输出上的电压信号是一个小幅度的中频电压信号。信号的小电压幅度导致许多优点，包括改善电荷泵线性度，降低电荷泵噪声，以及整个PLL的较低电源电压操作。

7. 发明授权

US07878385B2 Probe arrays and method for making 有权
标题翻译：探针阵列和制作方法
公开(公告)号：US07878385B2
公开(公告)日：2011-02-01
申请号：US11929539
申请日：2007-10-30
申请人： Ananda H. Kumar , Ezekiel J. J. Kruglick , Adam L. Cohen , Kieun Kim , Gang Zhang , Richard T. Chen , Christopher A. Bang , Vacit Arat , Michael S. Lockard , Uri Frodis , Pavel B. Lembrikov , Jeffrey A. Thompson
发明人： Ananda H. Kumar , Ezekiel J. J. Kruglick , Adam L. Cohen , Kieun Kim , Gang Zhang , Richard T. Chen , Christopher A. Bang , Vacit Arat , Michael S. Lockard , Uri Frodis , Pavel B. Lembrikov , Jeffrey A. Thompson
IPC分类号： B23K31/02
CPC分类号： B23K35/0222 , C23C18/1605 , C23C18/1651 , C25D1/003 , C25D1/12 , G01R1/06744 , G01R1/07307 , G01R1/07314 , G01R3/00 , H01L21/6835 , H01L24/11 , H01L24/12 , H01L24/16 , H01L24/81 , H01L24/95 , H01L2221/68313 , H01L2221/68354 , H01L2221/68363 , H01L2224/0401 , H01L2224/05568 , H01L2224/10126 , H01L2224/1147 , H01L2224/11831 , H01L2224/1184 , H01L2224/1191 , H01L2224/13017 , H01L2224/13018 , H01L2224/13076 , H01L2224/131 , H01L2224/1403 , H01L2224/81001 , H01L2224/81054 , H01L2224/81136 , H01L2224/8121 , H01L2224/8181 , H01L2224/81815 , H01L2924/00013 , H01L2924/0002 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/0102 , H01L2924/01022 , H01L2924/01024 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01045 , H01L2924/01047 , H01L2924/01049 , H01L2924/0105 , H01L2924/01073 , H01L2924/01074 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/01327 , H01L2924/014 , H01L2924/09701 , H01L2924/10253 , H01L2924/14 , H01L2924/1461 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/30107 , H01L2924/3011 , H01L2924/3025 , H01L2924/3651 , H01L2924/3841 , H01L2224/13099 , H01L2224/29099 , H01L2924/00 , H01L2224/05552 , H01L2924/00012
摘要： Embodiments of invention are directed to the formation of microprobes (i.e. compliant electrical or electronic contact elements) on a temporary substrate, dicing individual probe arrays, and then transferring the arrays to space transformers or other permanent substrates. Some embodiments of the invention transfer probes to permanent substrates prior to separating the probes from a temporary substrate on which the probes were formed while other embodiments do the opposite. Some embodiments, remove sacrificial material prior to transfer while other embodiments remove sacrificial material after transfer. Some embodiments are directed to the bonding of first and second electric components together using one or more solder bumps with enhanced aspect ratios (i.e. height to width ratios) obtained as a result of surrounding the bumps at least in part with rings of a retention material. The retention material may act be a solder mask material.
摘要翻译：本发明的实施例涉及在临时衬底上形成微探针（即柔性电气或电子接触元件），切割单独的探针阵列，然后将阵列转移到空间变压器或其它永久衬底。在将探针从其上形成探针的临时基底分离出来之前，本发明的一些实施方案将探针转移到永久性基底上，而其他实施方案相反。一些实施例，在转移之前去除牺牲材料，而其它实施例在转移后去除牺牲材料。一些实施例涉及使用一个或多个具有增强的纵横比（即，高度与宽度比）的焊料凸块来将第一和第二电气部件接合在一起，这是由于至少部分地由保持材料的环围绕凸块而得到的。保留材料可以用作焊接掩模材料。

8. 发明授权

US07864915B2 Low-power asynchronous counter and method 有权
标题翻译：低功耗异步计数器和方法
公开(公告)号：US07864915B2
公开(公告)日：2011-01-04
申请号：US12247970
申请日：2008-10-08
申请人： Gang Zhang
发明人： Gang Zhang
IPC分类号： H03K23/50
CPC分类号： H03L7/183 , H03K21/12 , H03L2207/50
摘要： Design techniques for a low-power asynchronous counter. In an exemplary embodiment, the clock inputs and signal outputs of a plurality of flip-flops are serially concatenated to implement an asynchronous counting mechanism. The signal outputs of the plurality of flip-flops are sampled by successively delayed versions of a reference signal. Further design techniques for generating successively delayed versions of the reference signal are disclosed. In an exemplary embodiment, the asynchronous counting techniques may be utilized in a high-speed counter for a digital-phase locked loop (DPLL).
摘要翻译：低功耗异步计数器的设计技术。在示例性实施例中，多个触发器的时钟输入和信号输出串联连接以实现异步计数机制。多个触发器的信号输出通过参考信号的连续延迟版本进行采样。公开了用于产生参考信号的连续延迟版本的进一步的设计技术。在示例性实施例中，可以在用于数字锁相环（DPLL）的高速计数器中使用异步计数技术。

9. 发明申请

US20100314258A1 Electrochemical Fabrication Processes Incorporating Non-Platable Metals and/or Metals that are Difficult to Plate On 审中-公开
标题翻译：掺入难以镀上的不可镀金属和/或金属的电化学制造工艺
公开(公告)号：US20100314258A1
公开(公告)日：2010-12-16
申请号：US12816914
申请日：2010-06-16
申请人： Adam L. Cohen , Michael S. Lockard , Gang Zhang
发明人： Adam L. Cohen , Michael S. Lockard , Gang Zhang
IPC分类号： C25D5/00
CPC分类号： C25D5/00 , B33Y10/00 , B81C99/0095 , B81C2201/0181 , C23C4/02 , C23C18/1605 , C23C18/1651 , C23C26/00 , C23C28/021 , C23C28/023 , C23C28/028 , C25D1/003
摘要： Embodiments are directed to electrochemically fabricating multi-layer three dimensional structures where each layer comprises at least one structural and at least one sacrificial material and wherein at least some metals or alloys are electrodeposited during the formation of some layers and at least some metals are deposited during the formation of some layers that are either difficult to electrodeposit and/or are difficult to electrodeposit onto. In some embodiments, the hard to electrodeposit metals (e.g. Ti, NiTi, W, Ta, Mo, etc.) may be deposited via chemical or physical vacuum deposition techniques while other techniques are used in other embodiments. In some embodiments, prior to electrodepositing metals, the surface of the previously formed layer is made to undergo appropriate preparation for receiving an electrodeposited material. Various surface preparation techniques are possible, including, for example, anodic activation, cathodic activation, and vacuum deposition of a seed layer and possibly an adhesion layer.
摘要翻译：实施例涉及电化学制造多层三维结构，其中每层包括至少一种结构和至少一种牺牲材料，并且其中至少一些金属或合金在形成一些层期间被电沉积，并且至少一些金属在形成难以电沉积和/或难以电沉积的一些层。在一些实施方案中，可以通过化学或物理真空沉积技术沉积难以电沉积的金属（例如Ti，NiTi，W，Ta，Mo等），而在其它实施方案中使用其它技术。在一些实施方案中，在电沉积金属之前，使先前形成的层的表面经历适当的准备以接收电沉积材料。各种表面处理技术是可能的，包括例如阳极活化，阴极活化和种子层以及可能的粘附层的真空沉积。

10. 发明申请

US20090239353A1 Methods For Forming Multi-layer Three-Dimensional Structures 有权
标题翻译：形成多层三维结构的方法
公开(公告)号：US20090239353A1
公开(公告)日：2009-09-24
申请号：US11548207
申请日：2006-10-10
申请人： Gang Zhang
发明人： Gang Zhang
IPC分类号： H01L21/30 , H01L21/306
CPC分类号： B81C1/0019 , B81C2201/019
摘要： The embodiments of the present invention are directed to the formation of multi-layer three-dimensional structures by forming and attaching a plurality of individual layers where each of the layers comprises one or more materials forming a desired pattern. In one embodiment, a multi-layer three-dimensional structure is formed by forming a plurality of individual layers and attaching at least them together. In another embodiment, a multi-layer three-dimensional structure is formed by 1) forming one or more individual layers, 2) attaching the one or more formed layers onto a substrate, 3) if desired, forming new structures on the attached one or more layers. In still another embodiment, a multi-layer three-dimensional structure is formed by 1) attaching a layer of a material onto a substrate; 2) processing the attached layer to form a desired pattern; 3) attaching another layer of a material onto the previously formed layer; 4) processing the new attached layer to form a desired pattern, and 5) if desired, repeating the steps of 3) and 4) one or more times.
摘要翻译：本发明的实施例涉及通过形成和附接多个单独层来形成多层三维结构，其中每个层包括形成期望图案的一种或多种材料。在一个实施例中，通过形成多个单独的层并至少将它们连接在一起而形成多层三维结构。在另一个实施方案中，通过以下方式形成多层三维结构：1）形成一个或多个单独的层，2）将一个或多个成形层附着到基底上，3）如果需要，在附着的层上形成新的结构多层在又一实施例中，通过以下方式形成多层三维结构：1）将材料层附着在基板上; 2）处理附着层以形成期望的图案; 3）将另一层材料附着在预先形成的层上; 4）处理新附着层以形成期望的图案，以及5）如果需要，重复步骤3）和4）一次或多次。

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