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1. 发明授权

US09015015B2 System for supporting robot hardware design and method thereof 有权
标题翻译：支持机器人硬件设计的系统及其方法
公开(公告)号：US09015015B2
公开(公告)日：2015-04-21
申请号：US13513417
申请日：2010-12-01
申请人： Mu Sung Choi , Kwang Woong Yang , Eun Chol Shin , Hong Seok Kim
发明人： Mu Sung Choi , Kwang Woong Yang , Eun Chol Shin , Hong Seok Kim
IPC分类号： G06G7/48 , G06F17/50 , G05B19/4097 , G05B15/02
CPC分类号： G06F17/50 , G05B15/02 , G05B19/4097
摘要： The present invention relates to a system and a method for supporting robotic hardware design, and the method comprises: loading a template which has information on the mechanical structure, operating mechanism, power transmission and motion data of robot modules; modifying the information for use in a simulator for further designing the robot modules; analyzing the behavior of each robot module according to respective motion data; applying the resulting data to modify each robot module according to simulation API; and controlling the selection/combination of robot parts for simulator assembly according to API and the resulting templates, databases on which robot parts are required and databases for information on selection/combination of robot parts and assembly of each robot module. The above system and method provide an optimal way to design robot hardware and reduce the time required for robot hardware design.
摘要翻译：本发明涉及一种用于支持机器人硬件设计的系统和方法，该方法包括：加载具有关于机器人模块的机械结构，操作机构，功率传输和运动数据的信息的模板; 修改用于模拟器的信息以进一步设计机器人模块; 根据各自的运动数据分析每个机器人模块的行为; 根据仿真API应用结果数据修改每个机器人模块; 并根据API和所得到的模板，需要机器人部件的数据库和关于机器人部件的选择/组合以及每个机器人模块的组装的信息的数据库来控制用于模拟器组装的机器人部件的选择/组合。上述系统和方法提供了设计机器人硬件的最佳方式，并缩短了机器人硬件设计所需的时间。

2. 发明授权

US06593790B2 Power-up/power-down detection circuit 有权
标题翻译：上电/掉电检测电路
公开(公告)号：US06593790B2
公开(公告)日：2003-07-15
申请号：US09245747
申请日：1999-02-08
申请人： Hong Seok Kim
发明人： Hong Seok Kim
IPC分类号： H03K302
CPC分类号： H03K17/223
摘要： A power-up detector for detecting power-up and power supply voltage bump conditions includes a current mirror connected to the power supply. A pair of series connected resistors are connected between the current mirror and ground thereby providing a bias point at a junction of the series connected resistors. A field effect transistor having a source-drain circuit is connected between the current mirror and ground for providing an output signal to an inverter. The field effect transistor being is controlled by the voltage at bias point between the series connected resistors.
摘要翻译：用于检测上电和电源电压突发条件的上电检测器包括连接到电源的电流镜。一对串联的电阻器连接在电流镜和地之间，从而在串联连接的电阻的结点处提供偏置点。具有源极 - 漏极电路的场效应晶体管连接在电流镜和地之间，以向逆变器提供输出信号。场效应晶体管由串联连接的电阻之间的偏压点处的电压控制。

3. 发明授权

US5715199A Back bias voltage generating circuit 失效
标题翻译：背偏置电压发生电路
公开(公告)号：US5715199A
公开(公告)日：1998-02-03
申请号：US771663
申请日：1996-12-23
申请人： Hong Seok Kim
发明人： Hong Seok Kim
IPC分类号： G11C5/14 , G11C7/00
CPC分类号： G11C5/146
摘要： A back bias voltage generating circuit of a semiconductor memory device which is capable of reducing noise generated during the operation of a circuit affecting the operation of a sense amplifier. The back bias voltage generating circuit includes: a back bias voltage oscillator which outputs a pulse signal having a constant period; a back bias voltage oscillator phase shifter which phase-shifts the pulse signal from the back bias voltage oscillator and outputs a plurality of phase-shifted pulse signals; a plurality of back bias voltage pump drivers which are driven by the plurality of phase-shifted pulse signals outputted from the back bias voltage oscillator phase shifter; a plurality of back bias voltage pumpers which generate a back bias voltage by control signals generated from the plurality of back bias voltage pump drivers; and a back bias voltage enable controller which inputs the back bias voltage and a sense amplifier enable signal for controlling the back bias voltage oscillator, to halt the back bias voltage pumpers, when a sense amplifier operates, but applies a signal detecting the back bias voltage to the back bias voltage oscillator, when the sense amplifier does not operate.
摘要翻译：一种半导体存储器件的背偏压生成电路，其能够降低在影响读出放大器的动作的电路工作期间产生的噪声。背偏置电压产生电路包括：背偏置电压振荡器，其输出具有恒定周期的脉冲信号; 背偏置电压振荡器移相器，其将来自后偏置电压振荡器的脉冲信号相移，并输出多个相移脉冲信号; 多个背偏压电压泵驱动器，由从背偏压晶体振荡器相移器输出的多个相移脉冲信号驱动; 多个背偏压电压泵，通过从多个背偏压泵驱动器产生的控制信号产生背偏压; 以及反馈偏置电压使能控制器，其在读出放大器工作时输入背偏置电压和用于控制背偏压振荡器的读出放大器使能信号，以停止背偏压泵浦器件，但是施加检测反偏压的信号到背偏置电压振荡器，当读出放大器不工作时。

4. 发明申请

US20120265498A1 System for Supporting Robot Hardware Design and Method Thereof 有权
标题翻译：支持机器人硬件设计及方法的系统
公开(公告)号：US20120265498A1
公开(公告)日：2012-10-18
申请号：US13513417
申请日：2010-12-01
申请人： Mu Sung Choi , Kwang Woong Yang , Eun Chol Shin , Hong Seok Kim
发明人： Mu Sung Choi , Kwang Woong Yang , Eun Chol Shin , Hong Seok Kim
IPC分类号： G06F17/50
CPC分类号： G06F17/50 , G05B15/02 , G05B19/4097
摘要： The present invention relates to a system and a method for supporting robotic hardware design, and the method comprises: loading a template which has information on the mechanical structure, operating mechanism, power transmission and motion data of robot modules; modifying the information for use in a simulator for further designing the robot modules; analyzing the behavior of each robot module according to respective motion data; applying the resulting data to modify each robot module according to simulation API; and controlling the selection/combination of robot parts for simulator assembly according to API and the resulting templates, databases on which robot parts are required and databases for information on selection/combination of robot parts and assembly of each robot module. The above system and method provide an optimal way to design robot hardware and reduce the time required for robot hardware design.
摘要翻译：本发明涉及一种用于支持机器人硬件设计的系统和方法，该方法包括：加载具有关于机器人模块的机械结构，操作机构，功率传输和运动数据的信息的模板; 修改用于模拟器的信息以进一步设计机器人模块; 根据各自的运动数据分析每个机器人模块的行为; 根据仿真API应用结果数据修改每个机器人模块; 并根据API和所得到的模板，需要机器人部件的数据库和关于机器人部件的选择/组合以及每个机器人模块的组装的信息的数据库来控制用于模拟器组装的机器人部件的选择/组合。上述系统和方法提供了设计机器人硬件的最佳方式，并缩短了机器人硬件设计所需的时间。

5. 发明授权

US5883603A Method for adjusting radiation direction of antenna 失效
标题翻译：调整天线辐射方向的方法
公开(公告)号：US5883603A
公开(公告)日：1999-03-16
申请号：US918225
申请日：1997-08-25
申请人： Hong Seok Kim
发明人： Hong Seok Kim
IPC分类号： H01Q3/00 , H01Q3/34 , H01Q3/44 , H01Q13/28 , H01Q13/00
CPC分类号： H01Q13/28 , H01Q3/34 , H01Q3/443
摘要： A method for adjusting the radiation direction of an antenna, which uses a plurality of uniformly spaced diffraction gratings formed in the waveguide of the antenna while adjusting the maximum radiation direction of radiation waves emerging from the diffraction gratings and varying the length of crystal lattices in the diffraction gratings, thereby achieving an improvement in the directivity of the radiation waves and an adjustment in the radiation direction of radiation waves. In accordance with this method, it is possible to vary the radiation direction of an electronic wave passing through the antenna by varying the interval of crystal lattices in a region where the diffraction gratings exist. Accordingly, it is possible to obtain a narrow beam width characteristic. The diffraction gratings are made of a piezo-electric material. Using the characteristic of such a piezo-electric material, it is possible to vary the interval of crystal lattices in the diffraction grating region in an electrical manner, thereby adjusting the radiation direction of beams.
摘要翻译：一种用于调整天线的辐射方向的方法，其使用形成在天线的波导中的多个均匀间隔的衍射光栅，同时调节从衍射光栅出射的辐射波的最大辐射方向并改变在衍射光栅中的晶格的长度衍射光栅，从而实现辐射波的方向性的改善和辐射波的辐射方向的调整。根据该方法，可以通过改变存在衍射光栅的区域中的晶格间隔来改变通过天线的电子波的辐射方向。因此，可以获得窄的波束宽度特性。衍射光栅由压电材料制成。使用这种压电材料的特性，可以以电气方式改变衍射光栅区域中的晶格间隔，从而调节光束的辐射方向。

6. 发明授权

US5641592A Method for fabricating phase shift mask 失效
标题翻译：制造相移掩模的方法
公开(公告)号：US5641592A
公开(公告)日：1997-06-24
申请号：US563261
申请日：1995-11-28
申请人： Hong Seok Kim
发明人： Hong Seok Kim
IPC分类号： G03F1/29 , G03F1/32 , G03F1/68 , H01L21/027 , G03F9/00
CPC分类号： G03F1/32 , G03F1/26
摘要： A method for fabricating a half-tone mask having a main chip region and a guard-board region, in which a deposition on entire surface by electrolytic process is made possible to simplify the fabricating process, including the steps of providing a transparent substrate, forming a half-tone mask on the transparent substrate, and selectively forming light shielding layers in the guard-board region of the half-tone mask.
摘要翻译：一种制造具有主芯片区域和保护板区域的半色调掩模的方法，其中通过电解处理在整个表面上的沉积成为可能以简化制造工艺，包括以下步骤：提供透明基板，成形半透明掩模，并且在半色调掩模的保护板区域中选择性地形成遮光层。

7. 发明授权

US06753120B2 Alignment measuring method of photolithography process 有权
标题翻译：光刻工艺的对准测量方法
公开(公告)号：US06753120B2
公开(公告)日：2004-06-22
申请号：US10151163
申请日：2002-05-21
申请人： Hong Seok Kim
发明人： Hong Seok Kim
IPC分类号： G03F900
CPC分类号： G03F7/705 , G03F7/70633
摘要： The invention relates to an alignment measuring method of a photolithography process by which a misalignment degree for each shot region of a wafer is indexed to improve the accuracy of determining the possibility of overlay defects. The method includes: measuring the overlay state of each pattern image transcribed to every shot region of a wafer; counting the number of shot regions judged as overlay defects with the misalignment amount of each measured shot region; calculating in percentage the number of shot regions judged as overlay defects against the number of total shot regions of the wafer; and comparing the calculated percentage value with a preset value to determine the possibility of rework. Accordingly, it is possible to estimate the misalignment amount of the unmeasured shot regions with that of the sampled and measured shot regions, determine the possibility of overlay defects of each shot region and determine quickly and conveniently the need to rework, thereby shortening the time of manufacturing semiconductor devices, improving reliability of judgment on rework due to exclusion of a worker's personal judgment and making progress in cost effectiveness of rework and manufactured yield.
摘要翻译：本发明涉及一种光刻工艺的对准测量方法，通过该对准测量方法将晶片的每个照射区域的未对准度分度，以提高确定覆盖缺陷可能性的准确性。该方法包括：测量转录到晶片的每个照射区域的每个图案图像的覆盖状态; 以每个测量的射击区域的未对准量计算被判定为覆盖缺陷的射击区域的数量; 以判定为覆盖缺陷的拍摄区域的数量与晶片的总拍摄区域数量的百分比计算; 并将计算的百分比值与预设值进行比较，以确定返工的可能性。因此，可以估计未测量的拍摄区域与采样和测量的拍摄区域的未对准量，确定每个拍摄区域的重叠缺陷的可能性，并且快速方便地确定对返工的需要，从而缩短制造半导体器件，提高由于排除工人个人判断而对返工的判断的可靠性，并且在返工和制造成品率的成本效益方面取得进展。

8. 发明授权

US5923595A Synchronous DRAM including an output data latch circuit being controlled by burst address 失效
标题翻译：包括由突发地址控制的输出数据锁存电路的同步DRAM
公开(公告)号：US5923595A
公开(公告)日：1999-07-13
申请号：US65908
申请日：1998-04-24
申请人： Hong Seok Kim
发明人： Hong Seok Kim
IPC分类号： G11C11/407 , G11C7/10 , G11C11/401 , G11C11/408 , G11C11/409 , G11C11/413 , G11C16/04
CPC分类号： G11C7/106 , G11C7/1051 , G11C7/1072
摘要： A synchronous DRAM for high-speed operation does not apply a burst address to a column address buffer under SDRAM's burst mode operation which receives only an initial address from an external part and produces a next address within a chip, but does reduce a signal path of the SDRAM by directly applying the burst address to a register storing the prefetched data, thereby enhancing operation speed. The SDRAM for high-speed operation includes: a mode register for programming a burst length; a column address buffer and latch means controlling an operation of the column decoder by a column active signal; a burst length counter means which generates a burst address as long as a programmed burst length to the mode register after receiving a burst start address; a burst control means for controlling the burst length counter means; and data latch means which temporarily stores the data transmitted to the global I/O line, and transmits the stored data to the data output buffer by controlling the burst address.
摘要翻译：用于高速操作的同步DRAM在SDRAM的突发模式操作下对列地址缓冲器不应用突发地址，其仅从外部部分仅接收初始地址并产生芯片内的下一个地址，而是减少信号路径通过直接将该突发地址应用于存储预取数据的寄存器，从而提高操作速度。用于高速操作的SDRAM包括：用于对突发长度进行编程的模式寄存器; 列地址缓冲器和锁存装置，通过列活动信号控制列解码器的操作; 突发长度计数器装置，其在接收到突发起始地址之后产生与模式寄存器的编程突发长度一样长的脉冲串地址; 用于控制突发长度计数器装置的突发控制装置; 以及临时存储发送到全局I / O线的数据的数据锁存装置，并且通过控制突发地址将所存储的数据发送到数据输出缓冲器。

9. 发明授权

US5818213A Back bias voltage detection circuit for semiconductor memory device 失效
标题翻译：用于半导体存储器件的背偏压检测电路
公开(公告)号：US5818213A
公开(公告)日：1998-10-06
申请号：US525276
申请日：1995-09-08
申请人： Hong Seok Kim
发明人： Hong Seok Kim
IPC分类号： G11C5/14 , G11C29/50 , G05F3/16
CPC分类号： G11C29/028 , G11C29/50 , G11C5/143 , G11C2029/5004
摘要： A back bias voltage detection circuit used for a semiconductor memory device wherein a threshold voltage of an NMOS transistor is varied by the back bias voltage. The threshold voltage of the NMOS transistor is detected by comparison to a reference voltage and the back bias voltage is adjusted according to the threshold voltage, with variable amplification of the back bias voltage. This control of the back bias voltage provides more effective control of the threshold voltage of the NMOS transistor.
摘要翻译：一种用于半导体存储器件的背偏置电压检测电路，其中NMOS晶体管的阈值电压由背偏压改变。通过与参考电压进行比较来检测NMOS晶体管的阈值电压，并且根据阈值电压调节背偏置电压，并且可靠地放大背偏置电压。背偏置电压的这种控制提供了对NMOS晶体管的阈值电压的更有效的控制。

10. 发明授权

US06291850B1 Structure of cylindrical capacitor electrode with layer of hemispherical grain silicon 有权
标题翻译：具有半球形晶粒硅层的圆柱形电容器电极的结构
公开(公告)号：US06291850B1
公开(公告)日：2001-09-18
申请号：US09435366
申请日：1999-11-08
申请人： Byung Jae Choi , Kwan Goo Rha , Hong Seok Kim , Jae Young An
发明人： Byung Jae Choi , Kwan Goo Rha , Hong Seok Kim , Jae Young An
IPC分类号： H01L27108
CPC分类号： H01L28/84 , H01L27/10852 , H01L28/75 , H01L28/91
摘要： A structure of a lower electrode of a capacitor includes a first lower electrode, second lower electrodes formed at both sides of the first lower electrode and electrically connected to and higher than the first lower electrode, and a Hemispherical Grain-Silicon (HSG-Si) layer formed on a top surface of the first lower electrode and inside walls of the second lower electrodes.
摘要翻译：电容器的下电极的结构包括：第一下电极，形成在第一下电极的两侧并与第一下电极电连接并高于第一下电极的第二下电极，以及半球晶格硅（HSG-Si）层形成在第一下电极的顶表面和第二下电极的内壁上。

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