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1. 发明授权

US08345487B2 Method of setting read voltage minimizing read data errors 有权
标题翻译：设置读取电压最小化读取数据错误的方法
公开(公告)号：US08345487B2
公开(公告)日：2013-01-01
申请号：US12774814
申请日：2010-05-06
申请人： Yong June Kim , Jae Hong Kim , Jun Jin Kong , Hong Rak Son , Seung-Hwan Song
发明人： Yong June Kim , Jae Hong Kim , Jun Jin Kong , Hong Rak Son , Seung-Hwan Song
IPC分类号： G11C11/413
CPC分类号： G11C11/5642 , G11C29/00 , G11C2211/5634
摘要： A method setting a read voltage to minimize data read errors in a semiconductor memory device including multi-bit memory cells. In the method, a read voltage associated with a minimal number of read data error is set based on a statistic value of a voltage distribution corresponding to each one of a plurality of voltage states.
摘要翻译：一种设置读取电压以最小化包括多位存储器单元的半导体存储器件中的数据读取错误的方法。在该方法中，基于与多个电压状态中的每一个相对应的电压分布的统计值来设置与最小数量的读取数据错误相关联的读取电压。

2. 发明申请

US20100020620A1 Memory device and method of programming thereof 有权
标题翻译：存储器件及其编程方法
公开(公告)号：US20100020620A1
公开(公告)日：2010-01-28
申请号：US12453964
申请日：2009-05-28
申请人： Yong June Kim , Kyoung Lae Cho , Jae Hong Kim , Jun Jin Kong , Hong Rak Son
发明人： Yong June Kim , Kyoung Lae Cho , Jae Hong Kim , Jun Jin Kong , Hong Rak Son
IPC分类号： G11C16/04 , G06F12/00
CPC分类号： G11C11/5628 , G11C7/1006
摘要： Example embodiments may provide a memory device and memory data programming method. The memory device according to example embodiments may encode a first data page to generate at least one first codeword and encode a second data page to generate a second codeword. The memory device may generate the first codeword with at least one of a maximum value of a number of successive ones and a second maximum value of a number of successive zeros. The memory device may program the at least one first codeword and the at least one second codeword to a plurality of multi-bit cells.
摘要翻译：示例性实施例可以提供存储器设备和存储器数据编程方法。根据示例性实施例的存储器件可编码第一数据页以产生至少一个第一码字，并对第二数据页进行编码以产生第二码字。存储器装置可以利用连续零个数的最大值和连续零数的第二最大值中的至少一个来生成第一码字。存储器件可以将至少一个第一代码字和至少一个第二代码字编程到多个多位单元。

3. 发明授权

US08004891B2 Memory device and method of programming thereof 有权
标题翻译：存储器件及其编程方法
公开(公告)号：US08004891B2
公开(公告)日：2011-08-23
申请号：US12453964
申请日：2009-05-28
申请人： Yong June Kim , Kyoung Lae Cho , Jae Hong Kim , Jun Jin Kong , Hong Rak Son
发明人： Yong June Kim , Kyoung Lae Cho , Jae Hong Kim , Jun Jin Kong , Hong Rak Son
IPC分类号： G11C16/04
CPC分类号： G11C11/5628 , G11C7/1006
摘要： Example embodiments may provide a memory device and memory data programming method. The memory device according to example embodiments may encode a first data page to generate at least one first codeword and encode a second data page to generate a second codeword. The memory device may generate the first codeword with at least one of a maximum value of a number of successive ones and a second maximum value of a number of successive zeros. The memory device may program the at least one first codeword and the at least one second codeword to a plurality of multi-bit cells.
摘要翻译：示例性实施例可以提供存储器设备和存储器数据编程方法。根据示例性实施例的存储器件可编码第一数据页以产生至少一个第一码字，并对第二数据页进行编码以产生第二码字。存储器装置可以利用连续零个数的最大值和连续零数的第二最大值中的至少一个来生成第一码字。存储器件可以将至少一个第一代码字和至少一个第二代码字编程到多个多位单元。

4. 发明授权

US07978521B2 Memory device and method of programming thereof 有权
标题翻译：存储器件及其编程方法
公开(公告)号：US07978521B2
公开(公告)日：2011-07-12
申请号：US12453594
申请日：2009-05-15
申请人： Hong Rak Son , Jae Hong Kim , Jun Jin Kong
发明人： Hong Rak Son , Jae Hong Kim , Jun Jin Kong
IPC分类号： G11C16/04
CPC分类号： G11C13/0069 , G11C13/0004 , G11C13/0061 , G11C16/04 , G11C29/02 , G11C29/021 , G11C29/24 , G11C2013/0073 , G11C2013/009 , G11C2013/0092
摘要： The method of programming data in a memory device includes applying a plurality of pulses to a plurality of memory cells, at least one of the plurality of pulses being a positive pulse having a positive voltage and at least one of the plurality of pulses being a negative pulse having a negative voltage, and a temporal interval existing between subsequent pulses of the plurality of pulses, and controlling at least one of a width of at least one of the temporal intervals and a magnitude of at least one of the plurality of pulses.
摘要翻译：在存储器件中编程数据的方法包括将多个脉冲施加到多个存储器单元，所述多个脉冲中的至少一个是具有正电压的正脉冲，并且所述多个脉冲中的至少一个是负的具有负电压的脉冲和存在于所述多个脉冲的后续脉冲之间的时间间隔，并且控制所述多个脉冲中的至少一个时间间隔中的至少一个的幅度和至少一个的幅度中的至少一个。

5. 发明授权

US09158500B2 Device and method for processing data including generating a pseudo random number sequence 有权
标题翻译：用于处理数据的装置和方法，包括产生伪随机数序列
公开(公告)号：US09158500B2
公开(公告)日：2015-10-13
申请号：US13537297
申请日：2012-06-29
申请人： Ki Jun Lee , Jun Jin Kong , Yong June Kim , Jae Hong Kim , Hong Rak Son , Jung Soo Chung , Seong Hyeong Choi
发明人： Ki Jun Lee , Jun Jin Kong , Yong June Kim , Jae Hong Kim , Hong Rak Son , Jung Soo Chung , Seong Hyeong Choi
IPC分类号： G06F7/58
CPC分类号： G06F7/584 , G06F2207/583
摘要： A data processing device which includes a conversion circuit and a pseudo random number generator including a series connection of plural shift registers. The conversion circuit receives a pseudo random number sequence from an output of one of the plural shift registers excluding a last shift register of the series connection, and converts first data to second data using the received pseudo random number sequence.
摘要翻译：一种数据处理装置，包括转换电路和包括多个移位寄存器的串联连接的伪随机数发生器。转换电路从除串行连接的最后一个移位寄存器之外的多个移位寄存器中的一个的输出接收伪随机数序列，并且使用接收到的伪随机数序列将第一数据转换为第二数据。

6. 发明申请

US20100251077A1 STORAGE DEVICE AND DATA STORAGE SYSTEM INCLUDING OF THE SAME 审中-公开
标题翻译：存储设备和包括其的数据存储系统
公开(公告)号：US20100251077A1
公开(公告)日：2010-09-30
申请号：US12729285
申请日：2010-03-23
申请人： Yong June Kim , Jae Hong Kim , Jun Jin Kong , Hong Rak Son
发明人： Yong June Kim , Jae Hong Kim , Jun Jin Kong , Hong Rak Son
IPC分类号： G06F12/02 , H03M13/05 , G06F11/10
CPC分类号： G06F11/1048
摘要： A storage device includes a controller unit and a memory cell array. The controller unit is for outputting data through a first data path or a second data path according to a property of externally supplied input data. The memory cell array includes a first memory and a second memory, and receives and stores the data from the controller unit output through the first and second data paths. The first memory has a different memory cell structure than the second memory.
摘要翻译：存储装置包括控制器单元和存储单元阵列。控制器单元用于根据外部提供的输入数据的属性通过第一数据路径或第二数据路径输出数据。存储单元阵列包括第一存储器和第二存储器，并且通过第一和第二数据路径接收并存储来自控制器单元输出的数据。第一存储器具有与第二存储器不同的存储单元结构。

7. 发明申请

US20100008146A1 Memory device and method of programming thereof 有权
标题翻译：存储器件及其编程方法
公开(公告)号：US20100008146A1
公开(公告)日：2010-01-14
申请号：US12453594
申请日：2009-05-15
申请人： Hong Rak Son , Jae Hong Kim , Jun Jin Kong
发明人： Hong Rak Son , Jae Hong Kim , Jun Jin Kong
IPC分类号： G11C11/34 , G11C16/04
CPC分类号： G11C13/0069 , G11C13/0004 , G11C13/0061 , G11C16/04 , G11C29/02 , G11C29/021 , G11C29/24 , G11C2013/0073 , G11C2013/009 , G11C2013/0092
摘要： The method of programming data in a memory device includes applying a plurality of pulses to a plurality of memory cells, at least one of the plurality of pulses being a positive pulse having a positive voltage and at least one of the plurality of pulses being a negative pulse having a negative voltage, and a temporal interval existing between subsequent pulses of the plurality of pulses, and controlling at least one of a width of at least one of the temporal intervals and a magnitude of at least one of the plurality of pulses.
摘要翻译：在存储器件中编程数据的方法包括将多个脉冲施加到多个存储器单元，所述多个脉冲中的至少一个是具有正电压的正脉冲，并且所述多个脉冲中的至少一个是负的具有负电压的脉冲和存在于所述多个脉冲的后续脉冲之间的时间间隔，并且控制所述多个脉冲中的至少一个时间间隔中的至少一个的幅度和至少一个的幅度中的至少一个。

8. 发明授权

US09875044B2 Data storage device compensating for initial threshold voltage distribution shift, method of operating the same, and data processing system including the same 有权
公开(公告)号：US09875044B2
公开(公告)日：2018-01-23
申请号：US14800783
申请日：2015-07-16
申请人： Dong Hwan Lee , Jun Jin Kong , Chang Kyu Seol , Hong Rak Son
发明人： Dong Hwan Lee , Jun Jin Kong , Chang Kyu Seol , Hong Rak Son
IPC分类号： G06F3/00 , G06F3/06 , G06F17/30 , G06F12/02 , G06F21/79 , G11C16/04
CPC分类号： G06F3/0619 , G06F3/065 , G06F3/0653 , G06F3/068 , G06F12/0246 , G06F17/3033 , G06F17/30867 , G06F21/79 , G11C16/0466
摘要： A method is provided for operating a data storage device capable of compensating for an initial threshold voltage shift of multiple memory cells. The method includes generating a first compression value for a first write address corresponding to a first write request input during a first time interval among different time intervals, and storing the first compression value in a first table among multiple tables.

9. 发明授权

US09009390B2 Method for changing read parameter for improving read performance and apparatuses using the same 有权
标题翻译：用于改变读取参数以提高读取性能的方法和使用其的装置
公开(公告)号：US09009390B2
公开(公告)日：2015-04-14
申请号：US13238749
申请日：2011-09-21
申请人： Seong Hyeog Choi , Hong Rak Son , Kyoung Lae Cho , Jun Jin Kong , Sang Hoon Lee
发明人： Seong Hyeog Choi , Hong Rak Son , Kyoung Lae Cho , Jun Jin Kong , Sang Hoon Lee
IPC分类号： G06F13/00 , G06F13/28 , G11C16/02 , G11C16/06 , G11C29/42 , G11C16/00 , G11C11/56 , G11C16/34
CPC分类号： G11C16/02 , G06F13/00 , G11C11/5642 , G11C16/00 , G11C16/06 , G11C16/3418 , G11C16/349 , G11C29/42
摘要： A memory system including a non-volatile memory device and a memory controller is provided. When a read operation on a first data initially output from the non-volatile memory device during a first read operation is successful, the memory controller may change a read voltage for reading a second data stored in the non-volatile memory device during a second read operation.
摘要翻译：提供了包括非易失性存储器件和存储器控制器的存储器系统。当在第一次读取操作期间最初从非易失性存储器件输出的第一数据的读取操作成功时，存储器控制器可以在第二次读取期间改变用于读取存储在非易失性存储器件中的第二数据的读取电压操作。

10. 发明授权

US08441862B2 Program method of multi-bit memory device and data storage system using the same 有权
标题翻译：多位存储器件和数据存储系统的程序方法使用相同
公开(公告)号：US08441862B2
公开(公告)日：2013-05-14
申请号：US13080809
申请日：2011-04-06
申请人： Hong Rak Son , Han Woong Yoo , Jaehong Kim , Jun Jin Kong
发明人： Hong Rak Son , Han Woong Yoo , Jaehong Kim , Jun Jin Kong
IPC分类号： G11C16/06
CPC分类号： G11C11/5628 , G11C16/3436
摘要： Provided is a program method of a multi-bit memory device with memory cells arranged in rows and columns. The program method includes a programming each memory cell of the first group of memory cells to a state within a first group of states according to a verify voltage level of a first group of verify voltage levels within a first range of levels, and programming each memory cell of the second group of memory cells to a state within a second group of states according to a verify voltage level of a second group of verify voltage levels within a second range of levels. The lowest verify voltage level in the second range of levels is higher than the highest verify voltage level in the first range of levels. A first voltage difference between adjacent verify voltage levels within the first range of levels is different from a second voltage difference between the highest verify voltage level of the second group of verify voltage levels and the lowest verify voltage level of the third group of verify voltage levels.
摘要翻译：提供了具有排列成行和列的存储单元的多位存储器件的编程方法。程序方法包括根据第一级别的第一组验证电压电平的验证电压电平将第一组存储器单元的每个存储器单元编程到第一组状态内的状态，以及编程每个存储器第二组存储器单元的单元根据在第二级别范围内的第二组验证电压电平的验证电压电平而处于第二组状态内的状态。第二级别的最低验证电压电平高于第一级别范围内的最高验证电压电平。在第一级别范围内的相邻验证电压电平之间的第一电压差不同于第二组验证电压电平的最高验证电压电平与第三组验证电压电平的最低验证电压电平之间的第二电压差。

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