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1. 发明申请

US20060043587A1 Apparatus and method for reducing signal cross talk between wire bonds of semiconductor packages 审中-公开
标题翻译：用于减少半导体封装的引线键合之间的信号串扰的装置和方法
公开(公告)号：US20060043587A1
公开(公告)日：2006-03-02
申请号：US10931682
申请日：2004-08-31
申请人： Hong Lim , Wee Liew , Chengyu Guo
发明人： Hong Lim , Wee Liew , Chengyu Guo
IPC分类号： H01L23/48
CPC分类号： H01L23/49838 , H01L23/49816 , H01L23/50 , H01L23/552 , H01L24/48 , H01L24/49 , H01L2223/6611 , H01L2224/48091 , H01L2224/48227 , H01L2224/48235 , H01L2224/48247 , H01L2224/48253 , H01L2224/48465 , H01L2224/49171 , H01L2924/00014 , H01L2924/01013 , H01L2924/01029 , H01L2924/01082 , H01L2924/01322 , H01L2924/014 , H01L2924/15311 , H01L2924/181 , H01L2924/30107 , H01L2924/3025 , H01L2924/00 , H01L2224/45099 , H01L2224/05599 , H01L2924/00012
摘要： A semiconductor package for reducing signal cross talk between wire bonds of semiconductor packages by using a tier of input-output power bond pads between two tiers of signal bond pads. The package includes a substrate having a first surface and a second surface and a die attach area on the first surface of the substrate. A first tier of signal contacts is arranged around the periphery of the die attach on the first surface of the substrate. A second tier of signal contacts is arranged around the periphery of the die attach area on the first surface of the substrate. A power contact tier is also arranged around the periphery of the die attach area on the first surface of the substrate. The power contact tier is arranged between the first tier of signal contacts and the second tier of signal contacts to reduce signal noise and cross talk between the signal bond wires of the first tier and the second tier.
摘要翻译：一种用于通过使用两层信号接合焊盘之间的一层输入 - 输出功率接合焊盘来减少半导体封装的引线键合之间的信号串扰的半导体封装。该封装包括具有第一表面和第二表面的衬底以及衬底的第一表面上的管芯附着区域。第一级信号触点设置在芯片的周边附近在基板的第一表面上。第二层信号触点设置在基板的第一表面上的管芯附接区域的周边周围。功率接触层也布置在基板的第一表面上的管芯附着区域的周边周围。功率接触层布置在第一层信号触点和第二层信号触点之间，以降低第一层和第二层的信号接合线之间的信号噪声和串扰。

2. 发明申请

US20100059865A1 Package with Power and Ground Through Via 有权
标题翻译：通过电源和接地的封装
公开(公告)号：US20100059865A1
公开(公告)日：2010-03-11
申请号：US12206786
申请日：2008-09-09
申请人： Qwai H. Low , Chengyu Guo
发明人： Qwai H. Low , Chengyu Guo
IPC分类号： H01L23/538
CPC分类号： H01L23/49816 , H01L23/3128 , H01L23/481 , H01L23/49838 , H01L24/29 , H01L24/32 , H01L24/48 , H01L24/73 , H01L2224/13099 , H01L2224/2929 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/484 , H01L2224/73257 , H01L2224/73265 , H01L2224/83194 , H01L2224/92125 , H01L2924/00014 , H01L2924/00015 , H01L2924/01014 , H01L2924/01023 , H01L2924/01031 , H01L2924/01032 , H01L2924/01033 , H01L2924/01057 , H01L2924/01082 , H01L2924/07811 , H01L2924/10252 , H01L2924/10253 , H01L2924/10329 , H01L2924/12041 , H01L2924/14 , H01L2924/15311 , H01L2924/15312 , H01L2924/181 , H01L2224/48233 , H01L2224/45099 , H01L2924/0665 , H01L2924/00 , H01L2924/00012
摘要： A wire bond design integrated circuit with a substrate having a front side and an opposing back side. Circuitry is disposed on the font side. Electrically conductive vias are disposed through the substrate from the front side to the back side, and are electrically connected to the circuitry such that the electrically conductive vias provide power and ground services only for the circuitry. Bonding pads are disposed on the front side, and are electrically connected to the circuitry such that the bonding pads provide signal communication only for the circuitry.
摘要翻译：一种引线键合设计集成电路，其具有前侧和相对背侧的基板。电路放置在字体侧。导电通孔从前侧到后侧设置穿过基板，并且电连接到电路，使得导电通孔仅为电路提供电力和接地服务。接合焊盘设置在前侧，并且电连接到电路，使得接合焊盘仅提供用于电路的信号通信。

3. 发明授权

US08350379B2 Package with power and ground through via 有权
标题翻译：通过电源和接地的封装
公开(公告)号：US08350379B2
公开(公告)日：2013-01-08
申请号：US12206786
申请日：2008-09-09
申请人： Qwai H. Low , Chengyu Guo
发明人： Qwai H. Low , Chengyu Guo
IPC分类号： H01L23/04
CPC分类号： H01L23/49816 , H01L23/3128 , H01L23/481 , H01L23/49838 , H01L24/29 , H01L24/32 , H01L24/48 , H01L24/73 , H01L2224/13099 , H01L2224/2929 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/484 , H01L2224/73257 , H01L2224/73265 , H01L2224/83194 , H01L2224/92125 , H01L2924/00014 , H01L2924/00015 , H01L2924/01014 , H01L2924/01023 , H01L2924/01031 , H01L2924/01032 , H01L2924/01033 , H01L2924/01057 , H01L2924/01082 , H01L2924/07811 , H01L2924/10252 , H01L2924/10253 , H01L2924/10329 , H01L2924/12041 , H01L2924/14 , H01L2924/15311 , H01L2924/15312 , H01L2924/181 , H01L2224/48233 , H01L2224/45099 , H01L2924/0665 , H01L2924/00 , H01L2924/00012
摘要： A wire bond design integrated circuit with a substrate having a front side and an opposing back side. Circuitry is disposed on the font side. Electrically conductive vias are disposed through the substrate from the front side to the back side, and are electrically connected to the circuitry such that the electrically conductive vias provide power and ground services only for the circuitry. Bonding pads are disposed on the front side, and are electrically connected to the circuitry such that the bonding pads provide signal communication only for the circuitry.
摘要翻译：一种引线键合设计集成电路，其具有前侧和相对背侧的基板。电路放置在字体侧。导电通孔从前侧到后侧设置穿过基板，并且电连接到电路，使得导电通孔仅为电路提供电力和接地服务。接合焊盘设置在前侧，并且电连接到电路，使得接合焊盘仅提供用于电路的信号通信。

4. 发明授权

US06687133B1 Ground plane on 2 layer PBGA 有权
标题翻译： 2层PBGA接地层
公开(公告)号：US06687133B1
公开(公告)日：2004-02-03
申请号：US10295711
申请日：2002-11-15
申请人： Wee K. Liew , Hong T. Lim , Chengyu Guo
发明人： Wee K. Liew , Hong T. Lim , Chengyu Guo
IPC分类号： H05K710
CPC分类号： H01L23/50 , H01L23/49816 , H01L24/48 , H01L2224/05599 , H01L2224/45099 , H01L2224/48091 , H01L2224/48227 , H01L2224/85399 , H01L2924/00014 , H01L2924/01078 , H01L2924/14 , H01L2924/15173 , H01L2924/15311 , H01L2924/181 , H01L2924/3011 , H01L2224/45015 , H01L2924/207 , H01L2924/00 , H01L2924/00012
摘要： A two layer PBGA which includes a metal ground plane at its bottom layer. The ground plane is preferably a metal plane which is connected to ground through a metal connection to a ball pad at the center of the package and a ball pad proximate the edge of the package. The ground plane is voided around the signal and power balls, via and “dog bones”. The PBGA is configured such that the ground plane serves effectively the same function as the second layer ground plane in a conventional four layer PBGA. The PBGA provides a cheaper alternative to the generally more expensive four layer PBGA, and provides better cross talk performance (especially for high frequency signaling) as well as better thermal performance as a result of having more metal at the bottom layer of the package.
摘要翻译：双层PBGA，其底层包括金属接地层。接地平面优选地是金属平面，该平面通过金属连接连接到在封装中心的球垫和接近封装边缘的球垫。地平面在信号和电源球，通孔和“狗骨头”周围无效。 PBGA被配置为使得接地平面在传统的四层PBGA中有效地起到与第二层接地层相同的功能。 PBGA为通常更昂贵的四层PBGA提供了更便宜的替代方案，并且由于在封装的底层具有更多的金属，所以提供了更好的串扰性能（特别是用于高频信号）以及更好的热性能。

5. 发明授权

US07325216B2 Method and computer program for spreading trace segments in an integrated circuit package design 失效
标题翻译：用于在集成电路封装设计中扩展迹线段的方法和计算机程序
公开(公告)号：US07325216B2
公开(公告)日：2008-01-29
申请号：US11271991
申请日：2005-11-09
申请人： Chengyu Guo
发明人： Chengyu Guo
IPC分类号： G06F17/50
CPC分类号： G06F17/5077
摘要： A method of routing an integrated circuit package includes receiving as input a placement and routing of at least a portion of an integrated circuit package design, selecting a set of at least three trace segments from the placement and routing that includes at least one inner trace segment routed between two outer trace segments, calculating an inner line function for the inner trace segment that is equally spaced from one of an adjacent line function, an adjacent outer line function, and an adjacent outer trace segment on each side of the inner line function, calculating a pair of end points for the inner line function, and generating as output a new routing that reroutes the inner trace segment collinearly with the inner line function and terminates the inner trace segment by the pair of end points.
摘要翻译：布线集成电路封装的方法包括：接收作为输入的集成电路封装设计的至少一部分的放置和布线，从放置和布线中选择至少三个迹线段的集合，其包括至少一个内部迹线段在两个外部跟踪段之间布线，计算与内部线功能的每一侧上的相邻线函数，相邻外部线函数和相邻外部跟踪段之间相等间隔的内部跟踪段的内部线函数，计算内线功能的一对端点，并产生一条新的路由，该路由重新路由内部跟踪段与内部线路功能，并通过一对端点终止内部跟踪段。

6. 发明申请

US20070104029A1 Method and computer program for spreading trace segments in an integrated circuit package design 失效
标题翻译：用于在集成电路封装设计中扩展迹线段的方法和计算机程序
公开(公告)号：US20070104029A1
公开(公告)日：2007-05-10
申请号：US11271991
申请日：2005-11-09
申请人： Chengyu Guo
发明人： Chengyu Guo
IPC分类号： G01V1/00
CPC分类号： G06F17/5077
摘要： A method of routing an integrated circuit package includes receiving as input a placement and routing of at least a portion of an integrated circuit package design, selecting a set of at least three trace segments from the placement and routing that includes at least one inner trace segment routed between two outer trace segments, calculating an inner line function for the inner trace segment that is equally spaced from one of an adjacent line function, an adjacent outer line function, and an adjacent outer trace segment on each side of the inner line function, calculating a pair of end points for the inner line function, and generating as output a new routing that reroutes the inner trace segment collinearly with the inner line function and terminates the inner trace segment by the pair of end points.
摘要翻译：布线集成电路封装的方法包括：接收作为输入的集成电路封装设计的至少一部分的放置和布线，从放置和布线中选择至少三个迹线段的集合，其包括至少一个内部迹线段在两个外部跟踪段之间布线，计算与内部线功能的每一侧上的相邻线函数，相邻外部线函数和相邻外部跟踪段之间相等间隔的内部跟踪段的内部线函数，计算内线功能的一对端点，并产生一条新的路由，该路由重新路由内部跟踪段与内部线路功能，并通过一对端点终止内部跟踪段。

7. 发明授权

US06897555B1 Integrated circuit package and method for a PBGA package having a multiplicity of staggered power ring segments for power connection to integrated circuit die 有权
标题翻译：用于PBGA封装的集成电路封装和方法，其具有用于与集成电路管芯连接的多个交错的功率环段
公开(公告)号：US06897555B1
公开(公告)日：2005-05-24
申请号：US10626366
申请日：2003-07-23
申请人： Hong Tee Lim , Wee Keong Liew , Chengyu Guo
发明人： Hong Tee Lim , Wee Keong Liew , Chengyu Guo
IPC分类号： H01L23/498 , H01L23/50 , H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L24/49 , H01L23/49827 , H01L23/49838 , H01L23/50 , H01L24/45 , H01L24/48 , H01L2224/05554 , H01L2224/32225 , H01L2224/45144 , H01L2224/48011 , H01L2224/48091 , H01L2224/48227 , H01L2224/48233 , H01L2224/484 , H01L2224/48599 , H01L2224/49171 , H01L2224/49175 , H01L2224/73265 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01033 , H01L2924/01079 , H01L2924/014 , H01L2924/14 , H01L2924/15311 , H01L2924/16152 , H01L2924/3011 , H01L2924/20653 , H01L2924/20654 , H01L2924/20655 , H01L2924/20656 , H01L2924/20657 , H01L2924/00 , H01L2224/85399 , H01L2224/05599
摘要： A BGA package having a multiplicity of power segments configured for power connection to integrated circuit die is disclosed. The BGA package substrate includes an integrated circuit die and a ground ring. The substrate also includes a first power ring with a plurality of spaced apart first power ring segments arranged around the die. A second power ring having a plurality of spaced apart conductive second ring segments is also formed around the die. A plurality of vias that penetrate through the substrate are provided to accommodate electrical connections to the segments of the first and second power rings and to the ground ring. The package includes bonding wires for connecting the die to the first and second ring segments and ground ring. Additionally, the package is commonly encapsulated to protect the die and wires. In some implementations, the conductive first ring segments are arranged in staggered configuration relative to the conductive second ring segments with each of the first ring segments having a conductive tab configured so that it passes through spaces between the conductive second ring segments. The tabs electrically connecting the first ring segments to vias.
摘要翻译：公开了一种具有多个功率段的BGA封装，其被配置用于与集成电路裸片的功率连接。 BGA封装衬底包括集成电路管芯和接地环。衬底还包括第一动力环，其具有围绕模具布置的多个间隔开的第一动力环段。具有多个间隔开的导电的第二环段的第二功率环也围绕模具形成。提供穿过基板的多个通孔以容纳到第一和第二电源环和接地环的段的电连接。该封装包括用于将管芯连接到第一和第二环段和接地环的接合线。另外，封装通常被封装以保护管芯和电线。在一些实施方案中，导电的第一环段相对于导电的第二环段布置成交错的构造，其中每个第一环段具有导电突出部，其被配置成使其穿过导电的第二环段之间的空间。所述接片将所述第一环段电连接到通孔。

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