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1. 发明申请

US20100215314A1 Apparatus Having an Embedded 3D Hybrid Integration for Optoelectronic Interconnects 有权
标题翻译：具有用于光电互连的嵌入式3D混合集成的装置
公开(公告)号：US20100215314A1
公开(公告)日：2010-08-26
申请号：US12709279
申请日：2010-02-19
申请人： Hon Shing Lau , Shi-Wei Lee , Matthew Ming Fai Yuen , Jingshen Wu , Chi Chuen Lo , Haibo Fan , Haibin Chen
发明人： Hon Shing Lau , Shi-Wei Lee , Matthew Ming Fai Yuen , Jingshen Wu , Chi Chuen Lo , Haibo Fan , Haibin Chen
IPC分类号： G02B6/12 , G02B6/42
CPC分类号： G02B6/43 , G02B6/4214 , H05K1/0274 , H05K2201/10121
摘要： An optoelectronic apparatus is described herein, including a transmitter, a receiver, and an optical waveguide, all of which are embedded in a PCB. The transmitter includes a laser generator and other circuits for generating electrical and optical signals, which are transmitted through the waveguide to the receiver. The receiver includes circuits and detectors for detecting and converting the optical signals to electrical signals. The circuit and optical components of the transmitter and receiver are integrated in 3D hybrid chip sets where the chip components are stacked in a 3D structure. Because all of the circuit and optical components are embedded in the PCB, the apparatus is made very compact and suitable for implementation in portable products.
摘要翻译：本文描述了一种光电子器件，包括发射器，接收器和光波导，所有这些都嵌入在PCB中。发射机包括激光发生器和用于产生电信号和光信号的其它电路，其通过波导传输到接收器。接收器包括用于检测和将光信号转换成电信号的电路和检测器。发射器和接收器的电路和光学部件集成在3D混合芯片组中，其中芯片组件以3D结构堆叠。由于所有电路和光学元件均嵌入在PCB中，因此该设备非常紧凑，适用于便携式产品。

2. 发明授权

US09057853B2 Apparatus having an embedded 3D hybrid integration for optoelectronic interconnects 有权
标题翻译：具有用于光电互连的嵌入式3D混合集成的装置
公开(公告)号：US09057853B2
公开(公告)日：2015-06-16
申请号：US12709279
申请日：2010-02-19
申请人： Hon Shing Lau , Shi-Wei Lee , Matthew Ming Fai Yuen , Jingshen Wu , Chi Chuen Lo , Haibo Fan , Haibin Chen
发明人： Hon Shing Lau , Shi-Wei Lee , Matthew Ming Fai Yuen , Jingshen Wu , Chi Chuen Lo , Haibo Fan , Haibin Chen
IPC分类号： G02B6/43 , H05K1/02 , G02B6/42
CPC分类号： G02B6/43 , G02B6/4214 , H05K1/0274 , H05K2201/10121
摘要： An optoelectronic apparatus is described herein, including a transmitter, a receiver, and an optical waveguide, all of which are embedded in a PCB. The transmitter includes a laser generator and other circuits for generating electrical and optical signals, which are transmitted through the waveguide to the receiver. The receiver includes circuits and detectors for detecting and converting the optical signals to electrical signals. The circuit and optical components of the transmitter and receiver are integrated in 3D hybrid chip sets where the chip components are stacked in a 3D structure. Because all of the circuit and optical components are embedded in the PCB, the apparatus is made very compact and suitable for implementation in portable products.
摘要翻译：这里描述了一种光电子器件，包括发射器，接收器和光波导，它们都嵌入在PCB中。发射机包括激光发生器和用于产生电信号和光信号的其它电路，其通过波导传输到接收器。接收器包括用于检测和将光信号转换成电信号的电路和检测器。发射器和接收器的电路和光学部件集成在3D混合芯片组中，其中芯片组件以3D结构堆叠。由于所有电路和光学元件均嵌入在PCB中，因此该设备非常紧凑，适用于便携式产品。

3. 发明授权

US08604603B2 Apparatus having thermal-enhanced and cost-effective 3D IC integration structure with through silicon via interposers 有权
标题翻译：具有通过插入器通过硅的热增强和具有成本效益的3D IC集成结构的装置
公开(公告)号：US08604603B2
公开(公告)日：2013-12-10
申请号：US12709291
申请日：2010-02-19
申请人： Hon Shing Lau , Shi-Wei Lee , Matthew Ming Fai Yuen , Jingshen Wu , Chi Chuen Lo , Haibo Fan , Haibin Chen
发明人： Hon Shing Lau , Shi-Wei Lee , Matthew Ming Fai Yuen , Jingshen Wu , Chi Chuen Lo , Haibo Fan , Haibin Chen
IPC分类号： H01L29/72
CPC分类号： H01L23/5384 , H01L23/055 , H01L23/433 , H01L23/5385 , H01L24/16 , H01L24/32 , H01L24/48 , H01L24/73 , H01L25/0652 , H01L25/18 , H01L2224/16225 , H01L2224/32 , H01L2224/32225 , H01L2224/32245 , H01L2224/48091 , H01L2224/48225 , H01L2224/48227 , H01L2224/48235 , H01L2224/73204 , H01L2224/73253 , H01L2224/73265 , H01L2225/0651 , H01L2225/06517 , H01L2225/06548 , H01L2225/06572 , H01L2225/06589 , H01L2924/00011 , H01L2924/00014 , H01L2924/01019 , H01L2924/10253 , H01L2924/14 , H01L2924/1432 , H01L2924/1433 , H01L2924/14335 , H01L2924/1434 , H01L2924/1436 , H01L2924/1437 , H01L2924/1461 , H01L2924/15153 , H01L2924/1517 , H01L2924/15311 , H01L2924/1532 , H01L2924/19041 , H01L2924/19043 , H01L2924/19105 , H01L2924/19106 , H01L2924/00 , H01L2224/0401 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： An apparatus having a three-dimensional integrated circuit structure is described herein. The apparatus include an interposer for carrying a plurality of high and low-power chips. The high-power chips are attached and connected to one side of the interposer, while the low-power chips are attached and connected to the other side of the interposer. In generally, the high-power chips produce more heat than does the low-power chip during their operations. The interposer further include through silicon vias and redistribution layers for connecting the chips on both surfaces. In addition, the interposer assembly is attached and connected to a substrate layer, which is in turn attached and connected to a printed circuit board. In order to provide improve thermal management, the interposer surface carrying the high-power chips are oriented away from the circuit board. A heat spreader is attached to the back sides of the high-power chips for dissipating the heat.
摘要翻译：本文描述了具有三维集成电路结构的装置。该装置包括用于承载多个高功率和低功率芯片的插入器。高功率芯片被连接并连接到插入器的一侧，而低功率芯片被附接并连接到插入器的另一侧。一般来说，高功率芯片在运行时产生比低功率芯片更多的热量。插入器还包括通过硅通孔和用于连接两个表面上的芯片的再分配层。此外，插入器组件附接并连接到衬底层，衬底层又连接并连接到印刷电路板。为了提供改进的热管理，承载大功率芯片的插入器表面远离电路板。散热器附着在大功率芯片的背面以散热。

4. 发明申请

US20100213600A1 Apparatus having thermal-enhanced and cost-effective 3D IC integration structure with through silicon via interposers 有权
标题翻译：具有通过插入器通过硅的热增强和具有成本效益的3D IC集成结构的装置
公开(公告)号：US20100213600A1
公开(公告)日：2010-08-26
申请号：US12709291
申请日：2010-02-19
申请人： Hon Shing Lau , Shi-Wei Lee , Matthew Ming Fai Yuen , Jingshen Wu , Chi Chuen Lo , Haibo Fan , Haibin Chen
发明人： Hon Shing Lau , Shi-Wei Lee , Matthew Ming Fai Yuen , Jingshen Wu , Chi Chuen Lo , Haibo Fan , Haibin Chen
IPC分类号： H01L23/34 , H01L21/60 , H01L23/498
CPC分类号： H01L23/5384 , H01L23/055 , H01L23/433 , H01L23/5385 , H01L24/16 , H01L24/32 , H01L24/48 , H01L24/73 , H01L25/0652 , H01L25/18 , H01L2224/16225 , H01L2224/32 , H01L2224/32225 , H01L2224/32245 , H01L2224/48091 , H01L2224/48225 , H01L2224/48227 , H01L2224/48235 , H01L2224/73204 , H01L2224/73253 , H01L2224/73265 , H01L2225/0651 , H01L2225/06517 , H01L2225/06548 , H01L2225/06572 , H01L2225/06589 , H01L2924/00011 , H01L2924/00014 , H01L2924/01019 , H01L2924/10253 , H01L2924/14 , H01L2924/1432 , H01L2924/1433 , H01L2924/14335 , H01L2924/1434 , H01L2924/1436 , H01L2924/1437 , H01L2924/1461 , H01L2924/15153 , H01L2924/1517 , H01L2924/15311 , H01L2924/1532 , H01L2924/19041 , H01L2924/19043 , H01L2924/19105 , H01L2924/19106 , H01L2924/00 , H01L2224/0401 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： An apparatus having a three-dimensional integrated circuit structure is described herein. The apparatus include an interposer for carrying a plurality of high and low-power chips. The high-power chips are attached and connected to one side of the interposer, while the low-power chips are attached and connected to the other side of the interposer. In generally, the high-power chips produce more heat than does the low-power chip during their operations. The interposer further include through silicon vias and redistribution layers for connecting the chips on both surfaces. In addition, the interposer assembly is attached and connected to a substrate layer, which is in turn attached and connected to a printed circuit board. In order to provide improve thermal management, the interposer surface carrying the high-power chips are oriented away from the circuit board. A heat spreader is attached to the back sides of the high-power chips for dissipating the heat.
摘要翻译：本文描述了具有三维集成电路结构的装置。该装置包括用于承载多个高功率和低功率芯片的插入器。高功率芯片被连接并连接到插入器的一侧，而低功率芯片被附接并连接到插入器的另一侧。一般来说，高功率芯片在运行时产生比低功率芯片更多的热量。插入器还包括通过硅通孔和用于连接两个表面上的芯片的再分配层。此外，插入器组件附接并连接到衬底层，衬底层又连接并连接到印刷电路板。为了提供改进的热管理，承载大功率芯片的插入器表面远离电路板。散热器附着在大功率芯片的背面以散热。

5. 发明申请

US20120223741A1 POWER REDUCING LOGIC AND NON-DESTRUCTIVE LATCH CIRCUITS AND APPLICATIONS 有权
标题翻译：减少电力和非破坏性电缆及其应用
公开(公告)号：US20120223741A1
公开(公告)日：2012-09-06
申请号：US13467171
申请日：2012-05-09
申请人： Hon Shing Lau , Scott Siers , Ruchira Liyanage
发明人： Hon Shing Lau , Scott Siers , Ruchira Liyanage
IPC分类号： H03K19/00
CPC分类号： H03K19/0016
摘要： In some embodiments, a logic circuit is provided that has a plurality of gates with gate inputs. Also provided is one or more latch circuits coupled to the logic circuit to provide operational data when in an operational mode and to cause at least some of the gate inputs to be at values resulting in reduced leakage during a sleep mode. Additionally provided are embodiments of non-destructive latch circuits, which may be used to implement the latch circuits just discussed. Other embodiments are disclosed and/or claimed herein.
摘要翻译：在一些实施例中，提供了具有多个具有栅极输入的栅极的逻辑电路。还提供了一个或多个锁存电路，其耦合到逻辑电路以在处于操作模式时提供操作数据，并且使至少一些栅极输入处于导致睡眠模式期间减少的泄漏的值。另外提供了非破坏性锁存电路的实施例，其可以用于实现刚刚讨论的锁存电路。在此公开和/或要求保护的其它实施例。

6. 发明授权

US5949726A Bias scheme to reduce burn-in test time for semiconductor memory while preventing junction breakdown 失效
标题翻译：减少半导体存储器的老化测试时间，同时防止结点故障的偏置方案
公开(公告)号：US5949726A
公开(公告)日：1999-09-07
申请号：US120360
申请日：1998-07-22
申请人： Jiunn-Chin Tseng , Hon Shing Lau
发明人： Jiunn-Chin Tseng , Hon Shing Lau
IPC分类号： G11C29/50 , G11C7/00
CPC分类号： G11C29/50
摘要： This invention describes a biasing scheme that reduces burn-in testing time as well as the number of cycles through the burn-in test for a semiconductor memory. The magnitude of a substrate back bias is reduced when a semiconductor memory device is taken into burn-in at a first value of an external applied voltage. When the memory device is brought out of burn-in, the substrate back bias is returned to the original operating level at a second value of the external applied voltage. The reduction of the substrate back bias allows for a higher external voltage to stress the semiconductor memory without forcing breakdown and results in a shorter test time. The burn-in test is entered at a higher magnitude of the external applied voltage than the voltage at which burn-in testing is exited. This helps to reduce the number of cycles through the burn-in test by providing a stronger external bias.
摘要翻译：本发明描述了通过半导体存储器的老化测试来减少老化测试时间以及循环次数的偏置方案。当以外部施加电压的第一值将半导体存储器件置于老化状态时，衬底反向偏压的幅度减小。当存储器件脱离老化时，衬底反向偏压以外部施加电压的第二值返回到初始工作电平。衬底反向偏置的减小允许更高的外部电压对半导体存储器施加压力，而不会强制击穿并导致较短的测试时间。老化测试在外部施加电压的大幅度下进入，而不是进行老化测试的电压。这有助于通过提供更强的外部偏压来减少老化测试的周期数。

7. 发明授权

US08305112B2 Power reducing logic and non-destructive latch circuits and applications 有权
标题翻译：降压逻辑和非破坏性锁存电路和应用
公开(公告)号：US08305112B2
公开(公告)日：2012-11-06
申请号：US12847248
申请日：2010-07-30
申请人： Hon Shing Lau , Scott Siers , Ruchira Liyanage
发明人： Hon Shing Lau , Scott Siers , Ruchira Liyanage
IPC分类号： H03K19/096
CPC分类号： H03K19/0016
摘要： In some embodiments, a logic circuit is provided that has a plurality of gates with gate inputs. Also provided is one or more latch circuits coupled to the logic circuit to provide operational data when in an operational mode and to cause at least some of the gate inputs to be at values resulting in reduced leakage during a sleep mode. Additionally provided are embodiments of non-destructive latch circuits, which may be used to implement the latch circuits just discussed. Other embodiments are disclosed and/or claimed herein.
摘要翻译：在一些实施例中，提供了具有多个具有栅极输入的栅极的逻辑电路。还提供了一个或多个锁存电路，其耦合到逻辑电路以在处于操作模式时提供操作数据，并且使至少一些栅极输入处于导致睡眠模式期间减少的泄漏的值。另外提供了非破坏性锁存电路的实施例，其可以用于实现刚刚讨论的锁存电路。在此公开和/或要求保护的其它实施例。

8. 发明授权

US09490807B2 Power reducing logic and non-destructive latch circuits and applications 有权
公开(公告)号：US09490807B2
公开(公告)日：2016-11-08
申请号：US13467171
申请日：2012-05-09
申请人： Hon Shing Lau , Scott Siers , Ruchira Liyanage
发明人： Hon Shing Lau , Scott Siers , Ruchira Liyanage
IPC分类号： H03K19/096 , H03K19/00
CPC分类号： H03K19/0016
摘要： In some embodiments, a logic circuit is provided that has a plurality of gates with gate inputs. Also provided is one or more latch circuits coupled to the logic circuit to provide operational data when in an operational mode and to cause at least some of the gate inputs to be at values resulting in reduced leakage during a sleep mode. Additionally provided are embodiments of non-destructive latch circuits, which may be used to implement the latch circuits just discussed. Other embodiments are disclosed and/or claimed herein.

9. 发明授权

US07761694B2 Execution unit for performing shuffle and other operations 有权
标题翻译：执行洗牌和其他操作的执行单元
公开(公告)号：US07761694B2
公开(公告)日：2010-07-20
申请号：US11478884
申请日：2006-06-30
申请人： Mohammad Abdallah , Hon Shing Lau , Shou-Wen Fu , Aviel Timor , Tal Gat
发明人： Mohammad Abdallah , Hon Shing Lau , Shou-Wen Fu , Aviel Timor , Tal Gat
IPC分类号： G06F7/38 , G06F7/00
CPC分类号： G06F9/30032 , G06F9/30036
摘要： In one embodiment, the present invention includes a method for receiving first and second data operands in a common execution unit and manipulating the operands responsive to an instruction to generate an output according to local control signals of a local controller of the execution unit. Various instruction types such as shuffle and shift operations may be performed in the common execution unit in a single cycle. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，本发明包括一种用于在公共执行单元中接收第一和第二数据操作数的方法，并且响应于根据执行单元的本地控制器的本地控制信号产生输出的指令操纵操作数。可以在单个周期中在公共执行单元中执行诸如随机播放和移位操作的各种指令类型。描述和要求保护其他实施例。

10. 发明授权

US08421502B2 Power reducing logic and non-destructive latch circuits and applications 有权
标题翻译：降压逻辑和非破坏性锁存电路和应用
公开(公告)号：US08421502B2
公开(公告)日：2013-04-16
申请号：US11270912
申请日：2005-11-10
申请人： Hon Shing Lau , Scott Siers , Ruchira Liyanage
发明人： Hon Shing Lau , Scott Siers , Ruchira Liyanage
IPC分类号： H03K19/00
CPC分类号： H03K19/0016
摘要： In some embodiments, a logic circuit is provided that has a plurality of gates with gate inputs. Also provided is one or more latch circuits coupled to the logic circuit to provide operational data when in an operational mode and to cause at least some of the gate inputs to be at values resulting in reduced leakage during a sleep mode. Additionally provided are embodiments of non-destructive latch circuits, which may be used to implement the latch circuits just discussed. Other embodiments are disclosed and/or claimed herein.
摘要翻译：在一些实施例中，提供了具有多个具有栅极输入的栅极的逻辑电路。还提供了一个或多个锁存电路，其耦合到逻辑电路以在处于操作模式时提供操作数据，并且使至少一些栅极输入处于导致睡眠模式期间减少的泄漏的值。另外提供了非破坏性锁存电路的实施例，其可以用于实现刚刚讨论的锁存电路。在此公开和/或要求保护的其它实施例。

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