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1. 发明授权

US5266850A Clock delay trim adjustment with stopping feature for eliminating differential delay between clock signal and analog signal 失效
标题翻译：时钟延迟微调调整具有停止功能，可消除时钟信号和模拟信号之间的差分延迟
公开(公告)号：US5266850A
公开(公告)日：1993-11-30
申请号：US907766
申请日：1992-06-30
申请人： Hoan A. Au , Arvind M. Patel , Robert A. Rutledge , Bum S. So , Albert S. Su
发明人： Hoan A. Au , Arvind M. Patel , Robert A. Rutledge , Bum S. So , Albert S. Su
IPC分类号： G11B20/10 , G11B20/14 , H04L7/00 , H04L7/033 , H04N5/04
CPC分类号： G11B20/10037 , G11B20/10009 , G11B20/1403 , H04L7/0008 , H04L7/0334
摘要： Method and circuitry for phase synchronizing an analog input signal with a clock signal by sensing clock delay error, adjusting in increments clock delay trim of a delay element that initially has an arbitrary delay setting, and stopping adjustment after differential delay between the signals has been eliminated.
摘要翻译：用于通过检测时钟延迟误差来将模拟输入信号与时钟信号相位同步的方法和电路，调整最初具有任意延迟设置的延迟元件的时钟延迟微调以及信号之间的差分延迟之后的停止调整已被消除。

2. 发明授权

US5430745A Prejudging current state in a decoder for coded signal processing channels 失效
标题翻译：对解码器中的编码信号处理通道进行预判定
公开(公告)号：US5430745A
公开(公告)日：1995-07-04
申请号：US198202
申请日：1994-02-17
申请人： Arvind M. Patel , Robert A. Rutledge , Bum S. So
发明人： Arvind M. Patel , Robert A. Rutledge , Bum S. So
IPC分类号： G11B20/10 , G11B20/14 , H03M5/14 , G06F11/10
CPC分类号： G11B20/1426 , G11B20/10009 , H03M5/145
摘要： Decoder for processing digital sample values corresponding to an incoming read signal representative of coded binary data. Functional expressions of digital sample values are precomputed for a preselected number of sample values ahead of a current sample value. To provide binary decision outputs, preselected functional expressions are compared against binary representations of corresponding thresholds that are conditioned by the sign of a selected functional expression comprising at least one preselected digital sample value. These outputs, the sign of the selected functional expression, the current value and previous value of decoded data, and the current value of detected phase, are all used to determine the next value of decoded data and next value of detected phase. These next values become the current values of decoded data and detected phase for the next clock cycle. The binary representations input to the comparators and the binary decision outputs of the comparators are inverted only if the selected functional expression has a preselected sign.
摘要翻译：解码器，用于处理对应于代表编码二进制数据的传入读取信号的数字样本值。数字样本值的功能表达式预先计算出当前样本值之前的预选数量的样本值。为了提供二进制判决输出，将预选的功能表达式与由包括至少一个预选数字样本值的所选功能表达式的符号调节的对应阈值的二进制表示进行比较。这些输出，所选功能表达式的符号，解码数据的当前值和先前值以及检测相位的当前值都用于确定解码数据的下一个值和检测相位的下一个值。这些下一个值将成为下一个时钟周期的解码数据和检测相位的当前值。输入到比较器的二进制表示和比较器的二进制判定输出仅在所选择的功能表达式具有预选符号时被反转。

3. 发明授权

US5559840A Digital timing recovery method and apparatus for a coded data channel 失效
标题翻译：用于编码数据信道的数字定时恢复方法和装置
公开(公告)号：US5559840A
公开(公告)日：1996-09-24
申请号：US312727
申请日：1994-09-27
申请人： Constantin M. Melas , Arvind M. Patel , Robert A. Rutledge , Bum S. So
发明人： Constantin M. Melas , Arvind M. Patel , Robert A. Rutledge , Bum S. So
IPC分类号： G11B20/14 , H04L7/00
CPC分类号： G11B20/10037 , G11B20/1403
摘要： A digital timing recovery circuit for rapid acquisition and synchronization of sampling clock phase in a data playback signal processing channel. The filtered playback signal in a (1,7)ML coded playback channel is sampled at the rate of one sample per bit window and the digitized sample values are processed with a (1,7)ML decoding procedure to produce decoded bits. A digital timing recovery circuit of this invention uses the digitized sample values directly to control the sampling clock phase by computing a digital phase error signal (PES) that is a constant function of phase error independent of data pattern. The PES depends only on the adjacent samples before and after a peak signal value. These "side-samples" contain maximal timing information because they occur at the steepest slope of the read-back signal and are thus most sensitive to clock phase error. Both side-samples of every pulse are weighted uniformly, independent of data pattern, thereby maximizing available phase information and ensuring the rapid acquisition and convergence of the sampling clock phase.
摘要翻译：数字定时恢复电路，用于在数据重放信号处理通道中快速采集和同步采样时钟相位。（1,7）ML编码回放通道中的滤波回放信号以每比特窗口一个样本的速率被采样，并且用（1,7）ML解码过程处理数字化样本值以产生解码比特。本发明的数字定时恢复电路通过计算独立于数据模式的相位误差的常数函数的数字相位误差信号（PES）来直接使用数字化采样值来控制采样时钟相位。 PES仅取决于峰值信号值之前和之后的相邻样本。这些“侧样本”包含最大定时信息，因为它们出现在回读信号的最陡坡处，因此对时钟相位误差最为敏感。每个脉冲的两个样本均匀地加权，与数据模式无关，从而最大化可用的相位信息，并确保采样时钟相位的快速采集和收敛。

4. 发明授权

US5491698A Setting optimal boundary thresholds in a decoder for coded signal processing channels 失效
标题翻译：在编码信号处理通道的解码器中设置最优边界阈值
公开(公告)号：US5491698A
公开(公告)日：1996-02-13
申请号：US169817
申请日：1993-12-16
申请人： Arvind M. Patel , Robert A. Rutledge , Bum S. So
发明人： Arvind M. Patel , Robert A. Rutledge , Bum S. So
IPC分类号： G06F11/08 , G11B20/10 , G11B20/14 , G11B20/18 , H03M7/14 , H03M13/00
CPC分类号： G11B20/10009 , G11B20/1426
摘要： To improve data detection reliability in a coded maximum likelihood signal processing channel, two counters count the number of times actual values of linear functions of digital sample values corresponding to one and another preselected data patterns are within m units above and m units below, respectively, a preselected decision boundary used to determine whether detected data corresponding to a coded sequence of runlength limited code is a "1" or a "0". A difference count has a magnitude and sign denoting difference between counts in the two counters. After N occurrences of each preselected data pattern irrespective of how far from the boundary, the boundary is adjusted upwardly or downwardly, provided the difference count at least equals +S or at most -S, respectively.
摘要翻译：为了提高编码最大似然信号处理通道中的数据检测可靠性，两个计数器计数对应于一个和另一个预选数据模式的数字样本值的线性函数的实际值分别在m单位以内和m单位以下的次数，用于确定与游程受限码的编码序列相对应的检测数据是“1”还是“0”的预选判定边界。差异计数具有表示两个计数器中的计数之间的差异的幅度和符号。在每次预先选择的数据模式发生N次之后，如果差值计数至少等于+ S或至多-S，则该边界被向上或向下调整。

5. 发明授权

US5282216A High data rate decoding method for coding signal processing channels 失效
标题翻译：用于编码信号处理通道的高数据速率解码方法
公开(公告)号：US5282216A
公开(公告)日：1994-01-25
申请号：US920027
申请日：1992-07-27
申请人： Arvind M. Patel , Robert A. Rutledge , Bum S. So
发明人： Arvind M. Patel , Robert A. Rutledge , Bum S. So
IPC分类号： G11B20/18 , G11B5/09 , G11B20/10 , G11B20/14 , H03M13/00
CPC分类号： G11B20/10009
摘要： A method for processing, in a signal processing channel, digital values corresponding to a digitized incoming analog signal representative of coded binary data. A state-dependent sequence detection algorithm includes two groups of appropriate functional expressions of digital sample values, which expressions are identical but offset one sample position from each other. During each iterating step with successive pairs of clock cycles, the value of each expression in the two groups of expressions is precomputed from a preselected number of sample values ahead of a then current sample value; preselected ones of these expression values are compared against an appropriate threshold, which is the same for corresponding expressions of each group, to provide respective binary decision outputs corresponding to each of the two groups; and the current state value then advances to two next successive state values. A pipelined configuration is utilized in which a different number of sample values, greater than said preselected number, is used ahead of the current sample value to allow sufficient time for precomputing said groups of expressions.
摘要翻译：一种用于在信号处理通道中处理与代表二进制数据的数字化输入模拟信号相对应的数字值的方法。状态依赖的序列检测算法包括数字样本值的两组适当的功能表达式，这些表达式是相同的，但彼此偏移一个样本位置。在具有连续的时钟周期对的每个迭代步骤期间，两组表达式中的每个表达式的值从当前样本值之前的预选数量的样本值预先计算; 将这些表达值中的预选择的值与对每个组的相应表达式相同的适当阈值进行比较，以提供对应于两组中的每一个的相应二进制判定输出; 并且当前状态值然后前进到两个下一个连续的状态值。使用流水线配置，其中在当前采样值之前使用大于所述预选数量的不同数量的采样值，以允许足够的时间预先计算所述表达组。

6. 发明授权

US5291500A Eight-sample look-ahead for coded signal processing channels 失效
标题翻译：编码信号处理通道的八个样本前瞻
公开(公告)号：US5291500A
公开(公告)日：1994-03-01
申请号：US526878
申请日：1990-05-22
申请人： Arvind M. Patel , Robert A. Rutledge
发明人： Arvind M. Patel , Robert A. Rutledge
IPC分类号： H03M7/46 , G11B20/10 , G11B20/14 , H03M5/14 , H03M7/14 , G06F11/10
CPC分类号： G11B20/10009 , G11B20/1488
摘要： A signal processing channel and method are described for processing digital sample values corresponding to an incoming analog signal representative of coded binary data. An eight-sample look-ahead algorithm is used to precompute the values of functional expressions for a baseline check and for a peak-position check. These precomputed values are compared against appropriate thresholds to provide respective binary decision outputs which, with state values corresponding to the current state, are used to determine state values for the next state, which become the current state values for the next iteration of the clock cycle. During each of a series of successive clock cycles, one successive bit of coded binary data corresponding to said current sample value is decoded, and at the next clock cycle, the computed next state becomes the new current state. Sensitivity to missing or extra-bit errors is minimized and full advantage of a (1,7) run-length-limited code constraint is achieved. A phase check is not necessary.
摘要翻译：描述信号处理通道和方法来处理对应于代表编码二进制数据的输入模拟信号的数字采样值。使用八样本预测算法预先计算基线检查和峰位置检查的功能表达式的值。将这些预计算值与适当的阈值进行比较，以提供相应的二进制判定输出，其中使用与当前状态相对应的状态值来确定下一状态的状态值，其将成为下一次周期性迭代的当前状态值。在一系列连续时钟周期的每一个期间，对应于所述当前采样值的一个连续位的编码二进制数据被解码，并且在下一个时钟周期，所计算的下一个状态变为新的当前状态。对丢失或额外位错误的敏感度最小化，并实现（1,7）游程长度限制代码约束的全部优势。不需要相位检查。

7. 发明授权

US5353170A Error recovery data storage system and method with two position read verification 失效
标题翻译：错误恢复数据存储系统和方法具有两个位置读取验证
公开(公告)号：US5353170A
公开(公告)日：1994-10-04
申请号：US64297
申请日：1993-05-19
申请人： Kwok W. Fung , Robert L. Kwok , Arvind M. Patel , Robert A. Rutledge
发明人： Kwok W. Fung , Robert L. Kwok , Arvind M. Patel , Robert A. Rutledge
IPC分类号： G11B5/09 , G11B5/012 , G11B19/04 , G11B20/18 , G11B5/584
CPC分类号： G11B5/012 , G11B19/04
摘要： A direct access storage device (DASD) system uses a read/write head having a wide transducer write element and a narrow magneto-resistive read element. In order to avoid mistakenly reading a incompletely erased old data field, the system uses a verification procedure. Data are read at two positions along the data track which are separated by a radial distance D. This distance D is selected to be greater than the width of any incompletely erased data record. If the data read at the two read positions are equal, then the data are deemed to be correct and are sent to a host system.
摘要翻译：直接访问存储设备（DASD）系统使用具有宽的换能器写入元件和窄的磁阻读取元件的读/写头。为了避免错误地读取不完全清除的旧数据字段，系统使用验证过程。在数据轨道的两个位置上读取数据，这两个位置被径向距离D分隔。该距离D被选择为大于任何不完全擦除的数据记录的宽度。如果在两个读取位置读取的数据相等，则认为数据是正确的，并被发送到主机系统。

8. 发明授权

US4035767A Error correction code and apparatus for the correction of differentially encoded quadrature phase shift keyed data (DQPSK) 失效
标题翻译：用于校正差分编码的正交相移键控数据（DQPSK）的纠错码和装置
公开(公告)号：US4035767A
公开(公告)日：1977-07-12
申请号：US662493
申请日：1976-03-01
申请人： Chin Long Chen , Robert A. Rutledge
发明人： Chin Long Chen , Robert A. Rutledge
IPC分类号： H04L27/18 , H03M13/23 , H04L1/00 , G06F11/12
CPC分类号： H04L1/0059
摘要： This specification describes a convolutional code and apparatus for the correction of errors in differentially encoded quadrature phase shift keyed data (DQPSK). In each sequence of forty bits 24 are information bits and the remainder are parity bits. Two parity bits are generated for each three information bit set in the sequence in accordance with the following equations:P.sub.8.sup.a = i.sub.8.sup.a .sym.i.sub.8.sup.b .sym.i.sub.6.sup.b .sym.i.sub.1.sup.b .sym.i.sub.3.sup.c .sym.i.sub.2.sup.cP.sub.8.sup.b = i.sub.8.sup.a .sym.i.sub.6.sup.a .sym.i.sub.3.sup.a .sym.i.sub.5.sup.b .sym.i.sub.8.sup.c .sym.i.sub.4.sup.cwhere i.sub.8.sup.a, i.sub.8.sup.b and i.sub.8.sup.c are the three information bits in the set associated with the parity bits P.sub.8.sup.a and P.sub.8.sup.b while the other information bits are from the seven sets of the sequence preceding the set associated with the parity bits.
摘要翻译：本说明书描述了用于校正差分编码的正交相移键控数据（DQPSK）中的误差的卷积码和装置。在四十位24的每个序列中都是信息位，余数是奇偶校验位。根据以下等式，在序列中设置的每个三个信息比特生成两个奇偶校验位：

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