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1. 发明申请

US20050105315A1 Content addressable memory (CAM) capable of finding errors in a CAM cell array and a method thereof 失效
标题翻译：能够在CAM单元阵列中发现错误的内容可寻址存储器（CAM）及其方法
公开(公告)号：US20050105315A1
公开(公告)日：2005-05-19
申请号：US10973806
申请日：2004-10-26
申请人： Ho-Geun Shin , Young-Hyun Jun
发明人： Ho-Geun Shin , Young-Hyun Jun
IPC分类号： G11C15/00 , G11C29/08
CPC分类号： G11C29/08 , G11C15/00
摘要： A method of finding errors in a content addressable memory (CAM) and a CAM cell array, the CAM being capable of finding errors in the CAM cell array, is disclosed. The CAM includes the CAM cell array having a plurality of CAM cells and a match line state storing unit. The match line state storing unit is connected to a word line and a match line of the plurality of CAM cells and has a plurality of state cells in which a logic level of stored data is changed according to a logic level of the match line. Errors in the CAM cell array are found by reading data stored in the plurality of state cells. The data stored in the plurality of state cells are matched when there are no errors in the CAM cell array.
摘要翻译：公开了一种在内容可寻址存储器（CAM）和CAM单元阵列中发现错误的方法，CAM能够在CAM单元阵列中发现错误。 CAM包括具有多个CAM单元的CAM单元阵列和匹配线状态存储单元。匹配线状态存储单元连接到多个CAM单元的字线和匹配线，并且具有根据匹配线的逻辑电平改变存储数据的逻辑电平的多个状态单元。通过读取存储在多个状态单元中的数据来发现CAM单元阵列中的错误。当CAM单元阵列中没有错误时，存储在多个状态单元中的数据是匹配的。

2. 发明授权

US07061783B2 Content addressable memory (CAM) capable of finding errors in a CAM cell array and a method thereof 失效
标题翻译：能够在CAM单元阵列中发现错误的内容可寻址存储器（CAM）及其方法
公开(公告)号：US07061783B2
公开(公告)日：2006-06-13
申请号：US10973806
申请日：2004-10-26
申请人： Ho-Geun Shin , Young-Hyun Jun
发明人： Ho-Geun Shin , Young-Hyun Jun
IPC分类号： G11C15/00 , G11C8/00
CPC分类号： G11C29/08 , G11C15/00
摘要： A method of finding errors in a content addressable memory (CAM) and a CAM cell array, the CAM being capable of finding errors in the CAM cell array, is disclosed. The CAM includes the CAM cell array having a plurality of CAM cells and a match line state storing unit. The match line state storing unit is connected to a word line and a match line of the plurality of CAM cells and has a plurality of state cells in which a logic level of stored data is changed according to a logic level of the match line. Errors in the CAM cell array are found by reading data stored in the plurality of state cells. The data stored in the plurality of state cells are matched when there are no errors in the CAM cell array.
摘要翻译：公开了一种在内容可寻址存储器（CAM）和CAM单元阵列中发现错误的方法，CAM能够在CAM单元阵列中发现错误。 CAM包括具有多个CAM单元的CAM单元阵列和匹配线状态存储单元。匹配线状态存储单元连接到多个CAM单元的字线和匹配线，并且具有根据匹配线的逻辑电平改变存储数据的逻辑电平的多个状态单元。通过读取存储在多个状态单元中的数据来发现CAM单元阵列中的错误。当CAM单元阵列中没有错误时，存储在多个状态单元中的数据是匹配的。

3. 发明申请

US20050201132A1 Content addressable memory (CAM) cell for operating at a high speed 审中-公开
标题翻译：内容可寻址存储器（CAM）单元，用于高速运行
公开(公告)号：US20050201132A1
公开(公告)日：2005-09-15
申请号：US11069719
申请日：2005-03-01
申请人： Ho-Geun Shin , Uk-Rae Cho , Jong-Soo Seo
发明人： Ho-Geun Shin , Uk-Rae Cho , Jong-Soo Seo
IPC分类号： G11C15/04 , G11C15/00
CPC分类号： G11C15/04
摘要： Provided is a content addressable memory (CAM) cell for operating at a high speed. The CAM cell includes a bit line pair consisting of a bit line and an inverted bit line, first and second memory cells, a match line, and first and second comparators. The first memory cell includes a first storage unit for storing data and first connectors for connecting the bit line pair to the first storage unit and for transmitting data input through the bit line pair to the first storage unit. The second memory cell includes a second storage unit for storing data and second connectors for connecting the bit line pair to the second storage unit and for transmitting the data input through the bit line pair to the second storage unit. The first comparator is connected to the match line and the first storage unit and connects the match line to a first voltage or disconnects the match line from the first voltage in response to search data input through a search line and the data stored in the first storage unit. The second comparator is connected to the match line and the second storage unit and connects the match line to the first voltage or disconnects the match line from the first voltage in response to the search data input through an inverted search line and the data stored in the second storage unit.
摘要翻译：提供了用于高速操作的内容可寻址存储器（CAM）单元。 CAM单元包括由位线和反相位线组成的位线对，第一和第二存储器单元，匹配线以及第一和第二比较器。第一存储单元包括用于存储数据的第一存储单元和用于将位线对连接到第一存储单元的第一连接器，以及用于将通过位线对输入的数据发送到第一存储单元。第二存储单元包括用于存储数据的第二存储单元和用于将位线对连接到第二存储单元的第二连接器，并用于将通过位线对输入的数据传送到第二存储单元。第一比较器连接到匹配线和第一存储单元，并且将匹配线连接到第一电压，或者响应于通过搜索线输入的搜索数据和第一存储器中存储的数据，将匹配线与第一电压断开单元。第二比较器连接到匹配线和第二存储单元，并且响应于通过反向搜索线输入的搜索数据和存储在第一电压中的数据，将匹配线连接到第一电压或者将匹配线从第一电压断开，第二存储单元。

4. 发明授权

US07363554B2 Method of detecting errors in a priority encoder and a content addressable memory adopting the same 失效
标题翻译：检测优先编码器和采用该优先编码器的内容寻址存储器中的错误的方法
公开(公告)号：US07363554B2
公开(公告)日：2008-04-22
申请号：US10973613
申请日：2004-10-26
申请人： Ho-Geun Shin
发明人： Ho-Geun Shin
IPC分类号： G11C29/00 , G11C7/00
CPC分类号： G11C29/024 , G11C15/00 , G11C29/02
摘要： A method of detecting errors in a priority encoder and a content addressable memory (CAM) adopting the same are provided. The CAM includes a CAM cell array, a priority encoder, and a shift register unit. The priority encoder tests the CAM cell array to determine if the CAM cell array has errors by comparing search data with data stored in the CAM cell array. The shift register unit, in response to a clock signal, transmits first through mth test data to the priority encoder to test the priority encoder. Then, the logic levels of the first through mth test data are sequentially changed in synchronization with the clock signal. If there are no errors in the priority encoder, the priority encoder sequentially outputs word line addresses of a most significant bit through a least significant bit of the CAM cell array.
摘要翻译：提供了一种检测优先编码器和采用该优先编码器的内容可寻址存储器（CAM）中的错误的方法。 CAM包括CAM单元阵列，优先编码器和移位寄存器单元。优先编码器通过将搜索数据与存储在CAM单元阵列中的数据进行比较来测试CAM单元阵列来确定CAM单元阵列是否存在错误。移位寄存器单元响应于时钟信号，将第一至第m个测试数据发送到优先编码器以测试优先编码器。然后，与时钟信号同步地顺序地改变第一至第测试数据的逻辑电平。如果优先编码器没有错误，则优先编码器通过CAM单元阵列的最低有效位顺序输出最高有效位的字线地址。

5. 发明申请

US20050094451A1 Method of detecting errors in a priority encoder and a content addressable memory adopting the same 失效
标题翻译：检测优先编码器和采用该优先编码器的内容寻址存储器中的错误的方法
公开(公告)号：US20050094451A1
公开(公告)日：2005-05-05
申请号：US10973613
申请日：2004-10-26
申请人： Ho-Geun Shin
发明人： Ho-Geun Shin
IPC分类号： G11C15/04 , G11C15/00 , G11C29/02 , G11C29/56 , G11C29/00
CPC分类号： G11C29/024 , G11C15/00 , G11C29/02
摘要： A method of detecting errors in a priority encoder and a content addressable memory (CAM) adopting the same are provided. The CAM includes a CAM cell array, a priority encoder, and a shift register unit. The priority encoder tests the CAM cell array to determine if the CAM cell array has errors by comparing search data with data stored in the CAM cell array. The shift register unit, in response to a clock signal, transmits first through mth test data to the priority encoder to test the priority encoder. Then, the logic levels of the first through mth test data are sequentially changed in synchronization with the clock signal. If there are no errors in the priority encoder, the priority encoder sequentially outputs word line addresses of a most significant bit through a least significant bit of the CAM cell array.
摘要翻译：提供了一种检测优先编码器和采用该优先编码器的内容可寻址存储器（CAM）中的错误的方法。 CAM包括CAM单元阵列，优先编码器和移位寄存器单元。优先编码器通过将搜索数据与存储在CAM单元阵列中的数据进行比较来测试CAM单元阵列来确定CAM单元阵列是否存在错误。移位寄存器单元响应于时钟信号，将第一至第m个测试数据发送到优先编码器以测试优先编码器。然后，与时钟信号同步地顺序地改变第一至第测试数据的逻辑电平。如果优先编码器没有错误，则优先编码器通过CAM单元阵列的最低有效位顺序输出最高有效位的字线地址。

6. 发明授权

US5999390A Input buffer circuit for semiconductor device 失效
标题翻译：半导体器件的输入缓冲电路
公开(公告)号：US5999390A
公开(公告)日：1999-12-07
申请号：US122076
申请日：1998-07-24
申请人： Baek-Hyung Cho , Choong-Keun Kwak , Ho-Geun Shin
发明人： Baek-Hyung Cho , Choong-Keun Kwak , Ho-Geun Shin
IPC分类号： H01L27/04 , G01R31/28 , G01R31/3185 , H01L21/822 , H01L21/8238 , H01L27/092 , H03K19/003 , H03K19/0175 , H02H3/18
CPC分类号： H03K19/00315
摘要： A CMOS input buffer for semiconductor devices, that is capable of protecting its MOS transistors from gate oxide breakdown due to the application of high voltage greater than a normal power supply voltage.
摘要翻译：用于半导体器件的CMOS输入缓冲器，其能够通过施加大于正常电源电压的高电压来保护其MOS晶体管免受栅极氧化物击穿。

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